diff options
author | Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> | 2013-05-02 13:32:09 +0000 |
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committer | Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> | 2013-05-02 13:32:09 +0000 |
commit | 12c433c86e6ddccfc9521d19096e403be0eb3905 (patch) | |
tree | 963f1369081421eea8fe61e8c713ef107aedd66c /gcc/config | |
parent | 218e25a5b9a05b72fca27a9e288e6adf33de458a (diff) |
Backport from trunk r198030.
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@198536 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/arm/arm.md | 179 |
1 files changed, 151 insertions, 28 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b88694f9ef5..1893a909255 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -839,7 +839,7 @@ ;; This is the canonicalization of addsi3_compare0_for_combiner when the ;; addend is a constant. -(define_insn "*cmpsi2_addneg" +(define_insn "cmpsi2_addneg" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 1 "s_register_operand" "r,r") @@ -1396,7 +1396,7 @@ (set_attr "type" "simple_alu_imm,*,*")] ) -(define_insn "*subsi3_compare" +(define_insn "subsi3_compare" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I") (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))) @@ -8690,7 +8690,7 @@ (set_attr "type" "f_sel<vfp_type>")] ) -(define_insn "*movsicc_insn" +(define_insn_and_split "*movsicc_insn" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") (if_then_else:SI (match_operator 3 "arm_comparison_operator" @@ -8703,10 +8703,45 @@ mvn%D3\\t%0, #%B2 mov%d3\\t%0, %1 mvn%d3\\t%0, #%B1 - mov%d3\\t%0, %1\;mov%D3\\t%0, %2 - mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 - mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 - mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" + # + # + # + #" + ; alt4: mov%d3\\t%0, %1\;mov%D3\\t%0, %2 + ; alt5: mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 + ; alt6: mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 + ; alt7: mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" + "&& reload_completed" + [(const_int 0)] + { + enum rtx_code rev_code; + enum machine_mode mode; + rtx rev_cond; + + emit_insn (gen_rtx_COND_EXEC (VOIDmode, + operands[3], + gen_rtx_SET (VOIDmode, + operands[0], + operands[1]))); + + rev_code = GET_CODE (operands[3]); + mode = GET_MODE (operands[4]); + if (mode == CCFPmode || mode == CCFPEmode) + rev_code = reverse_condition_maybe_unordered (rev_code); + else + rev_code = reverse_condition (rev_code); + + rev_cond = gen_rtx_fmt_ee (rev_code, + VOIDmode, + operands[4], + const0_rtx); + emit_insn (gen_rtx_COND_EXEC (VOIDmode, + rev_cond, + gen_rtx_SET (VOIDmode, + operands[0], + operands[2]))); + DONE; + } [(set_attr "length" "4,4,4,4,8,8,8,8") (set_attr "conds" "use") (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") @@ -9675,27 +9710,64 @@ (set_attr "type" "alu_shift,alu_shift_reg")]) -(define_insn "*and_scc" +(define_insn_and_split "*and_scc" [(set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (match_operator:SI 1 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") (const_int 0)]) - (match_operand:SI 2 "s_register_operand" "r")))] + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:SI 3 "s_register_operand" "r")))] "TARGET_ARM" - "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" + "#" ; "mov%D1\\t%0, #0\;and%d1\\t%0, %3, #1" + "&& reload_completed" + [(cond_exec (match_dup 5) (set (match_dup 0) (const_int 0))) + (cond_exec (match_dup 4) (set (match_dup 0) + (and:SI (match_dup 3) (const_int 1))))] + { + enum machine_mode mode = GET_MODE (operands[2]); + enum rtx_code rc = GET_CODE (operands[1]); + + /* Note that operands[4] is the same as operands[1], + but with VOIDmode as the result. */ + operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); + if (mode == CCFPmode || mode == CCFPEmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); + operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); + } [(set_attr "conds" "use") (set_attr "insn" "mov") (set_attr "length" "8")] ) -(define_insn "*ior_scc" +(define_insn_and_split "*ior_scc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (ior:SI (match_operator:SI 2 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") (const_int 0)]) - (match_operand:SI 1 "s_register_operand" "0,?r")))] + (ior:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:SI 3 "s_register_operand" "0,?r")))] "TARGET_ARM" "@ - orr%d2\\t%0, %1, #1 - mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" + orr%d1\\t%0, %3, #1 + #" + "&& reload_completed + && REGNO (operands [0]) != REGNO (operands[3])" + ;; && which_alternative == 1 + ; mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1 + [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3))) + (cond_exec (match_dup 4) (set (match_dup 0) + (ior:SI (match_dup 3) (const_int 1))))] + { + enum machine_mode mode = GET_MODE (operands[2]); + enum rtx_code rc = GET_CODE (operands[1]); + + /* Note that operands[4] is the same as operands[1], + but with VOIDmode as the result. */ + operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); + if (mode == CCFPmode || mode == CCFPEmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); + operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); + } [(set_attr "conds" "use") (set_attr "length" "4,8")] ) @@ -10402,24 +10474,75 @@ "") ;; ??? The conditional patterns above need checking for Thumb-2 usefulness -(define_insn "*negscc" +(define_insn_and_split "*negscc" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operator 3 "arm_comparison_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")]))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "* - if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) - return \"mov\\t%0, %1, asr #31\"; - - if (GET_CODE (operands[3]) == NE) - return \"subs\\t%0, %1, %2\;mvnne\\t%0, #0\"; + "#" + "&& reload_completed" + [(const_int 0)] + { + rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); - output_asm_insn (\"cmp\\t%1, %2\", operands); - output_asm_insn (\"mov%D3\\t%0, #0\", operands); - return \"mvn%d3\\t%0, #0\"; - " + if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) + { + /* Emit mov\\t%0, %1, asr #31 */ + emit_insn (gen_rtx_SET (VOIDmode, + operands[0], + gen_rtx_ASHIFTRT (SImode, + operands[1], + GEN_INT (31)))); + DONE; + } + else if (GET_CODE (operands[3]) == NE) + { + /* Emit subs\\t%0, %1, %2\;mvnne\\t%0, #0 */ + if (CONST_INT_P (operands[2])) + emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2], + GEN_INT (- INTVAL (operands[2])))); + else + emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2])); + + emit_insn (gen_rtx_COND_EXEC (VOIDmode, + gen_rtx_NE (SImode, + cc_reg, + const0_rtx), + gen_rtx_SET (SImode, + operands[0], + GEN_INT (~0)))); + DONE; + } + else + { + /* Emit: cmp\\t%1, %2\;mov%D3\\t%0, #0\;mvn%d3\\t%0, #0 */ + emit_insn (gen_rtx_SET (VOIDmode, + cc_reg, + gen_rtx_COMPARE (CCmode, operands[1], operands[2]))); + enum rtx_code rc = GET_CODE (operands[3]); + + rc = reverse_condition (rc); + emit_insn (gen_rtx_COND_EXEC (VOIDmode, + gen_rtx_fmt_ee (rc, + VOIDmode, + cc_reg, + const0_rtx), + gen_rtx_SET (VOIDmode, operands[0], const0_rtx))); + rc = GET_CODE (operands[3]); + emit_insn (gen_rtx_COND_EXEC (VOIDmode, + gen_rtx_fmt_ee (rc, + VOIDmode, + cc_reg, + const0_rtx), + gen_rtx_SET (VOIDmode, + operands[0], + GEN_INT (~0)))); + DONE; + } + FAIL; + } [(set_attr "conds" "clob") (set_attr "length" "12")] ) |