* cfgloop.c, config/alpha/alpha.c, config/bfin/bfin.c,

	config/i386/athlon.md, config/ia64/ia64.md,
	config/rs6000/rs6000.c, config/s390/s390.c, config/spu/spu.md,
	df-problems.c, df.h, fold-const.c, ipa-cp.c, ipa-inline.c,
	ipa-prop.h, see.c, struct-equiv.c, tree-inline.c,
	tree-ssa-loop-niter.c, tree-vect-analyze.c,
	tree-vect-transform.c: Fix comment typos.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@122080 138bc75d-0d04-0410-961f-82ee72b054a4

7 files changed, 8 insertions, 8 deletions

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index dcaa647047a..e0ece7561b8 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -4434,7 +4434,7 @@ emit_insxl (enum machine_mode mode, rtx op1, rtx op2)
   return ret;
 }
 
-/* Expand an an atomic fetch-and-operate pattern.  CODE is the binary operation
+/* Expand an atomic fetch-and-operate pattern.  CODE is the binary operation
    to perform.  MEM is the memory on which to operate.  VAL is the second 
    operand of the binary operator.  BEFORE and AFTER are optional locations to
    return the value of MEM either before of after the operation.  SCRATCH is
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 7f964638742..e71305a7eb0 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -1537,7 +1537,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
    For args passed entirely in registers or entirely in memory, zero.
 
    Refer VDSP C Compiler manual, our ABI.
-   First 3 words are in registers. So, if a an argument is larger
+   First 3 words are in registers. So, if an argument is larger
    than the registers available, it will span the register and
    stack.   */
 
diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md
index 708507f4224..04b1e1e2d34 100644
--- a/gcc/config/i386/athlon.md
+++ b/gcc/config/i386/athlon.md
@@ -603,7 +603,7 @@
 			 "athlon-direct,athlon-fploadk8,athlon-fstore")
 ;; On AMDFAM10 all double, single and integer packed and scalar SSEx data
 ;; loads  generated are direct path, latency of 2 and do not use any FP
-;; executions units. No seperate entries for movlpx/movhpx loads, which
+;; executions units. No separate entries for movlpx/movhpx loads, which
 ;; are direct path, latency of 4 and use the FADD/FMUL FP execution units,
 ;; as they will not be generated.
 (define_insn_reservation "athlon_sseld_amdfam10" 2
@@ -637,7 +637,7 @@
 			 "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
 ;; On AMDFAM10 all double, single and integer packed SSEx data stores
 ;; generated are all double path, latency of 2 and use the FSTORE FP
-;; execution unit. No entries seperate for movupx/movdqu, which are
+;; execution unit. No entries separate for movupx/movdqu, which are
 ;; vector path, latency of 3 and use the FSTORE*2 FP execution unit,
 ;; as they will not be generated.
 (define_insn_reservation "athlon_ssest_amdfam10" 2
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index d60900717c4..23a29747868 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -476,7 +476,7 @@
 
 ;; Define register predicate prefix.
 ;; We can generate speculative loads only for general and fp registers - this
-;; is constrainted in ia64.c: ia64_speculate_insn ().
+;; is constrained in ia64.c: ia64_speculate_insn ().
 (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")])
 
 (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")])
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 76669093887..3835a9a5928 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -12705,7 +12705,7 @@ emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
   emit_insn (fn (res, mem, val));
 }
 
-/* Expand an an atomic fetch-and-operate pattern.  CODE is the binary operation
+/* Expand an atomic fetch-and-operate pattern.  CODE is the binary operation
    to perform.  MEM is the memory on which to operate.  VAL is the second
    operand of the binary operator.  BEFORE and AFTER are optional locations to
    return the value of MEM either before of after the operation.  SCRATCH is
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 26484664b54..1ef4510b15b 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -4228,7 +4228,7 @@ s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx ne
 }
 
 /* Expand an atomic operation CODE of mode MODE.  MEM is the memory location
-   and VAL the value to play with.  If AFTER is true then store the the value
+   and VAL the value to play with.  If AFTER is true then store the value
    MEM holds after the operation, if AFTER is false then store the value MEM
    holds before the operation.  If TARGET is zero then discard that value, else
    store it to TARGET.  */
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 8dbeadff098..523ecec5798 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -56,7 +56,7 @@
     "pipe0, fp, nothing*5")
 
 ;; The behavior of the double precision is that both pipes stall
-;; for 6 cycles and the the rest of the operation pipelines for
+;; for 6 cycles and the rest of the operation pipelines for
 ;; 7 cycles.  The simplest way to model this is to simply ignore
 ;; the 6 cyle stall.
 (define_insn_reservation "FPD" 7 (eq_attr "type" "fpd")