2009-01-03 Diego Novillo <dnovillo@google.com>

	Mainline merge @142987.

	* configure.ac (ACX_PKGVERSION): Update revision merge string.
	* configure: Regenerate.




git-svn-id: https://gcc.gnu.org/svn/gcc/branches/lto@143031 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 74 insertions, 17 deletions

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 1d9247fb4a2..a218065e55c 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -327,6 +327,24 @@ Alternatively, if a MPFR source distribution is found in a subdirectory
 of your GCC sources named @file{mpfr}, it will be built together with
 GCC@.
 
+@item Parma Polyhedra Library (PPL) version 0.10
+
+Necessary to build GCC with the Graphite loop optimizations.
+It can be downloaded from @uref{http://www.cs.unipr.it/ppl/Download/}.
+
+The @option{--with-ppl} configure option should be used if PPL is not
+installed in your default library search path.
+
+@item CLooG-PPL version 0.15
+
+Necessary to build GCC with the Graphite loop optimizations.  It can
+be downloaded from @uref{ftp://gcc.gnu.org/pub/gcc/infrastructure/}.
+The code in @file{cloog-ppl-0.15.tar.gz} comes from a branch of CLooG
+available from @uref{http://repo.or.cz/w/cloog-ppl.git}.  CLooG-PPL
+should be configured with @option{--with-ppl}.
+
+The @option{--with-cloog} configure option should be used if CLooG is
+not installed in your default library search path.
 
 @item @command{jar}, or InfoZIP (@command{zip} and @command{unzip})
 
@@ -1428,6 +1446,26 @@ GCC, you can explicitly specify the directory where they are installed
 shorthand assumptions are not correct, you can use the explicit
 include and lib options directly.
 
+@item --with-ppl=@var{pathname}
+@itemx --with-ppl-include=@var{pathname}
+@itemx --with-ppl-lib=@var{pathname}
+@itemx --with-cloog=@var{pathname}
+@itemx --with-cloog-include=@var{pathname}
+@itemx --with-cloog-lib=@var{pathname}
+If you do not have PPL (the Parma Polyhedra Library) and the CLooG
+libraries installed in a standard location and you want to build GCC,
+you can explicitly specify the directory where they are installed
+(@samp{--with-ppl=@var{pplinstalldir}},
+@samp{--with-cloog=@var{clooginstalldir}}). The
+@option{--with-ppl=@var{pplinstalldir}} option is shorthand for
+@option{--with-ppl-lib=@var{pplinstalldir}/lib} and
+@option{--with-ppl-include=@var{pplinstalldir}/include}.  Likewise the
+@option{--with-cloog=@var{clooginstalldir}} option is shorthand for
+@option{--with-cloog-lib=@var{clooginstalldir}/lib} and
+@option{--with-cloog-include=@var{clooginstalldir}/include}.  If these
+shorthand assumptions are not correct, you can use the explicit
+include and lib options directly.
+
 @item --with-debug-prefix-map=@var{map}
 Convert source directory names using @option{-fdebug-prefix-map} when
 building runtime libraries.  @samp{@var{map}} is a space-separated
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2cd38c74f0b..6a03d61d2af 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -338,7 +338,7 @@ Objective-C and Objective-C++ Dialects}.
 -finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg -fipa-pta @gol 
 -fipa-pure-const -fipa-reference -fipa-struct-reorg @gol
 -fipa-type-escape -fira -fira-algorithm=@var{algorithm} @gol
--fira-coalesce -fno-ira-share-save-slots @gol
+-fira-region=@var{region} -fira-coalesce -fno-ira-share-save-slots @gol
 -fno-ira-share-spill-slots -fira-verbose=@var{n} @gol
 -fivopts -fkeep-inline-functions -fkeep-static-consts @gol
 -floop-block -floop-interchange -floop-strip-mine -fltrans -fltrans-driver @gol
@@ -5728,17 +5728,25 @@ allocation.  It is a default if @acronym{IRA} has been ported for the
 target.
 
 @item -fira-algorithm=@var{algorithm}
-Use specified algorithm for the integrated register allocator.  The
-@var{algorithm} argument should be one of @code{regional}, @code{CB},
-or @code{mixed}.  The second algorithm specifies Chaitin-Briggs
-coloring, the first one specifies regional coloring based on
-Chaitin-Briggs coloring, and the third one which is the default
-specifies a mix of Chaitin-Briggs and regional algorithms where loops
-with small register pressure are ignored.  The first algorithm can
-give best result for machines with small size and irregular register
-set, the second one is faster and generates decent code and the
-smallest size code, and the mixed algorithm usually give the best
-results in most cases and for most architectures.
+Use specified coloring algorithm for the integrated register
+allocator.  The @var{algorithm} argument should be @code{priority} or
+@code{CB}.  The first algorithm specifies Chow's priority coloring,
+the second one specifies Chaitin-Briggs coloring.  The second
+algorithm can be unimplemented for some architectures.  If it is
+implemented, it is the default because Chaitin-Briggs coloring as a
+rule generates a better code.
+
+@item -fira-region=@var{region}
+Use specified regions for the integrated register allocator.  The
+@var{region} argument should be one of @code{all}, @code{mixed}, or
+@code{one}.  The first value means using all loops as register
+allocation regions, the second value which is the default means using
+all loops except for loops with small register pressure as the
+regions, and third one means using all function as a single region.
+The first value can give best result for machines with small size and
+irregular register set, the third one results in faster and generates
+decent code and the smallest size code, and the default value usually
+give the best results in most cases and for most architectures.
 
 @item -fira-coalesce
 @opindex fira-coalesce
@@ -8632,7 +8640,8 @@ example, if a cross-compiler was configured with @samp{configure
 arm-elf}, meaning to compile for an arm processor with elf binaries,
 then you would specify @option{-b arm-elf} to run that cross compiler.
 Because there are other options beginning with @option{-b}, the
-configuration must contain a hyphen.
+configuration must contain a hyphen, or @option{-b} alone should be one
+argument followed by the configuration in the next argument.
 
 @item -V @var{version}
 @opindex V
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 3505dea45af..50767a2036f 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2050,9 +2050,18 @@ Any MMX register.
 @item x
 Any SSE register.
 
+@item Yz
+First SSE register (@code{%xmm0}).
+
 @ifset INTERNALS
-@item Y
-Any SSE2 register.
+@item Y2
+Any SSE register, when SSE2 is enabled.
+
+@item Yi
+Any SSE register, when SSE2 and inter-unit moves are enabled.
+
+@item Ym
+Any MMX register, when inter-unit moves are enabled.
 @end ifset
 
 @item I
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 672f6d178a3..3d3a52955bd 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1005,7 +1005,7 @@ the test
 
 @item variable @var{tool_timeout} defined by the set of tests
 
-@item @var{gcc,,timeout} set in the target board
+@item @var{gcc},@var{timeout} set in the target board
 
 @item 300
 @end itemize
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 7dfb46b3a0d..5a76a6e5e69 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -2841,7 +2841,8 @@ options have been processed. It is then re-examined by every call to
 The default implementation returns @code{IRA_COVER_CLASSES}, if defined,
 otherwise there is no default implementation.  You must define either this
 macro or @code{IRA_COVER_CLASSES} in order to use the integrated register
-allocator for the target.
+allocator with Chaitin-Briggs coloring. If the macro is not defined,
+the only available coloring algorithm is Chow's priority coloring.
 @end deftypefn
 
 @defmac IRA_COVER_CLASSES