2008-04-24 Kenneth Zadeck <zadeck@naturalbridge.com>

	Merge with mainline @134626.



git-svn-id: https://gcc.gnu.org/svn/gcc/branches/lto@134646 138bc75d-0d04-0410-961f-82ee72b054a4

12 files changed, 381 insertions, 146 deletions

diff --git a/gcc/doc/c-tree.texi b/gcc/doc/c-tree.texi
index d7276894432..1f019763d09 100644
--- a/gcc/doc/c-tree.texi
+++ b/gcc/doc/c-tree.texi
@@ -1508,7 +1508,7 @@ whose @code{TREE_VALUE} represents a type.
 
 @item TYPE_NOTHROW_P
 This predicate holds when the exception-specification of its arguments
-if of the form `@code{()}'.
+is of the form `@code{()}'.
 
 @item DECL_ARRAY_DELETE_OPERATOR_P
 This predicate holds if the function an overloaded
diff --git a/gcc/doc/cpp.texi b/gcc/doc/cpp.texi
index 1963ebcf1f5..b98aef2bd68 100644
--- a/gcc/doc/cpp.texi
+++ b/gcc/doc/cpp.texi
@@ -11,7 +11,7 @@
 @copying
 @c man begin COPYRIGHT
 Copyright @copyright{} 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
-1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
 Free Software Foundation, Inc.
 
 Permission is granted to copy, distribute and/or modify this document
@@ -3857,9 +3857,10 @@ and stick to it.
 @item The mapping of physical source file multi-byte characters to the
 execution character set.
 
-Currently, CPP requires its input to be ASCII or UTF-8.  The execution
-character set may be controlled by the user, with the
-@option{-fexec-charset} and @option{-fwide-exec-charset} options.
+The input character set can be specified using the
+@option{-finput-charset} option, while the execution character set may
+be controlled using the @option{-fexec-charset} and
+@option{-fwide-exec-charset} options.
 
 @item Identifier characters.
 @anchor{Identifier characters}
diff --git a/gcc/doc/cppopts.texi b/gcc/doc/cppopts.texi
index dbc8f0e6e67..4b02a87cb8e 100644
--- a/gcc/doc/cppopts.texi
+++ b/gcc/doc/cppopts.texi
@@ -682,6 +682,14 @@ Like @samp{D}, but emit only the macro names, not their expansions.
 @opindex dI
 Output @samp{#include} directives in addition to the result of
 preprocessing.
+
+@item U
+@opindex dU
+Like @samp{D} except that only macros that are expanded, or whose
+definedness is tested in preprocessor directives, are output; the
+output is delayed until the use or test of the macro; and
+@samp{#undef} directives are also output for macros tested but
+undefined at the time.
 @end table
 
 @item -P
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index b28d9dfd35d..7cae1a4e070 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2299,16 +2299,33 @@ is used.  @xref{C Dialect Options,,Options
 Controlling C Dialect}.
 
 @item function_vector
-@cindex calling functions through the function vector on H8/300, M16C, and M32C processors
+@cindex calling functions through the function vector on H8/300, M16C, M32C and SH2A processors
 Use this attribute on the H8/300, H8/300H, and H8S to indicate that the specified
 function should be called through the function vector.  Calling a
 function through the function vector will reduce code size, however;
 the function vector has a limited size (maximum 128 entries on the H8/300
 and 64 entries on the H8/300H and H8S) and shares space with the interrupt vector.
 
+In SH2A target, this attribute declares a function to be called using the
+TBR relative addressing mode.  The argument to this attribute is the entry
+number of the same function in a vector table containing all the TBR
+relative addressable functions.  For the successful jump, register TBR
+should contain the start address of this TBR relative vector table.
+In the startup routine of the user application, user needs to care of this
+TBR register initialization.  The TBR relative vector table can have at
+max 256 function entries.  The jumps to these functions will be generated
+using a SH2A specific, non delayed branch instruction JSR/N @@(disp8,TBR).
 You must use GAS and GLD from GNU binutils version 2.7 or later for
 this attribute to work correctly.
 
+Please refer the example of M16C target, to see the use of this
+attribute while declaring a function,
+
+In an application, for a function being called once, this attribute will
+save at least 8 bytes of code; and if other successive calls are being
+made to the same function, it will save 2 bytes of code per each of these
+calls.
+
 On M16C/M32C targets, the @code{function_vector} attribute declares a
 special page subroutine call function. Use of this attribute reduces
 the code size by 2 bytes for each call generated to the
@@ -2722,6 +2739,19 @@ number of registers available if used in conjunction with the
 attribute is incompatible with nested functions; this is considered a
 hard error.
 
+@item resbank
+@cindex @code{resbank} attribute
+On the SH2A target, this attribute enables the high-speed register
+saving and restoration using a register bank for @code{interrupt_handler}
+routines.  Saving to the bank is performed automatcially after the CPU
+accepts an interrupt that uses a register bank.
+
+The nineteen 32-bit registers comprising general register R0 to R14,
+control register GBR, and system registers MACH, MACL, and PR and the
+vector table address offset are saved into a register bank.  Register
+banks are stacked in first-in last-out (FILO) sequence.  Restoration
+from the bank is executed by issuing a RESBANK instruction.
+
 @item returns_twice
 @cindex @code{returns_twice} attribute
 The @code{returns_twice} attribute tells the compiler that a function may
@@ -7983,6 +8013,27 @@ depending on the size of @code{unsigned long}.
 Generates the @code{popcntq} machine instruction.
 @end table
 
+The following built-in functions are available when @option{-maes} is
+used.  All of them generate the machine instruction that is part of the
+name.
+
+@smallexample
+v2di __builtin_ia32_aesenc128 (v2di, v2di)
+v2di __builtin_ia32_aesenclast128 (v2di, v2di)
+v2di __builtin_ia32_aesdec128 (v2di, v2di)
+v2di __builtin_ia32_aesdeclast128 (v2di, v2di)
+v2di __builtin_ia32_aeskeygenassist128 (v2di, const int)
+v2di __builtin_ia32_aesimc128 (v2di)
+@end smallexample
+
+The following built-in function is available when @option{-mpclmul} is
+used.
+
+@table @code
+@item v2di __builtin_ia32_pclmulqdq128 (v2di, v2di, const int)
+Generates the @code{pclmulqdq} machine instruction.
+@end table
+
 The following built-in functions are available when @option{-msse4a} is used.
 All of them generate the machine instruction that is part of the name.
 
diff --git a/gcc/doc/gcc.texi b/gcc/doc/gcc.texi
index e52d79a6543..baf4173c787 100644
--- a/gcc/doc/gcc.texi
+++ b/gcc/doc/gcc.texi
@@ -170,7 +170,7 @@ Introduction, gccint, GNU Compiler Collection (GCC) Internals}.
 
 @include funding.texi
 @include gnu.texi
-@include gpl.texi
+@include gpl_v3.texi
 
 @c ---------------------------------------------------------------------
 @c GFDL
diff --git a/gcc/doc/gccint.texi b/gcc/doc/gccint.texi
index 2f699472f5b..47e02214f09 100644
--- a/gcc/doc/gccint.texi
+++ b/gcc/doc/gccint.texi
@@ -156,7 +156,7 @@ Additional tutorial information is linked to from
 
 @include funding.texi
 @include gnu.texi
-@include gpl.texi
+@include gpl_v3.texi
 
 @c ---------------------------------------------------------------------
 @c GFDL
diff --git a/gcc/doc/include/gpl_v3.texi b/gcc/doc/include/gpl_v3.texi
index 6e7ea63fefe..31806777366 100644
--- a/gcc/doc/include/gpl_v3.texi
+++ b/gcc/doc/include/gpl_v3.texi
@@ -1,4 +1,19 @@
+@ignore
+@c Set file name and title for man page.
+@setfilename gpl
+@settitle GNU General Public License
+@c man begin SEEALSO
+gfdl(7), fsf-funding(7).
+@c man end
+@c man begin COPYRIGHT
+Copyright @copyright{} 2007 Free Software Foundation, Inc.
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+@c man end
+@end ignore
 @node Copying
+@c man begin DESCRIPTION
 @unnumbered GNU General Public License
 @center Version 3, 29 June 2007
 
@@ -715,3 +730,4 @@ library, you may consider it more useful to permit linking proprietary
 applications with the library.  If this is what you want to do, use
 the GNU Lesser General Public License instead of this License.  But
 first, please read @url{http://www.gnu.org/philosophy/why-not-lgpl.html}.
+@c man end
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 45d982c52eb..027b1692bd9 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -285,7 +285,7 @@ requirements.
 Necessary to uncompress GCC @command{tar} files when source code is
 obtained via FTP mirror sites.
 
-@item GNU make version 3.79.1 (or later)
+@item GNU make version 3.80 (or later)
 
 You must have GNU make installed to build GCC@.
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 87f1252d585..59b7c822d23 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -341,8 +341,9 @@ Objective-C and Objective-C++ Dialects}.
 -fno-toplevel-reorder -fno-trapping-math -fno-zero-initialized-in-bss @gol
 -fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls @gol
 -fpeel-loops -fpredictive-commoning -fprefetch-loop-arrays @gol
--fprofile-generate -fprofile-use -fprofile-values -freciprocal-math @gol
--fregmove -frename-registers -freorder-blocks @gol
+-fprofile-dir=@var{path} -fprofile-generate -fprofile-generate=@var{path} @gol
+-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol
+-freciprocal-math -fregmove -frename-registers -freorder-blocks @gol
 -freorder-blocks-and-partition -freorder-functions @gol
 -frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
 -frounding-math -frtl-abstract-sequences -fsched2-use-superblocks @gol
@@ -554,6 +555,7 @@ Objective-C and Objective-C++ Dialects}.
 -mno-wide-multiply  -mrtd  -malign-double @gol
 -mpreferred-stack-boundary=@var{num} -mcx16 -msahf -mrecip @gol
 -mmmx  -msse  -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 @gol
+-maes -mpclmul @gol
 -msse4a -m3dnow -mpopcnt -mabm -msse5 @gol
 -mthreads  -mno-align-stringops  -minline-all-stringops @gol
 -mpush-args  -maccumulate-outgoing-args  -m128bit-long-double @gol
@@ -744,7 +746,7 @@ See RS/6000 and PowerPC Options.
 -m5-compact  -m5-compact-nofpu @gol
 -mb  -ml  -mdalign  -mrelax @gol
 -mbigtable  -mfmovd  -mhitachi -mrenesas -mno-renesas -mnomacsave @gol
--mieee  -misize  -minline-ic_invalidate -mpadstruct  -mspace @gol
+-mieee  -mbitops  -misize  -minline-ic_invalidate -mpadstruct  -mspace @gol
 -mprefergot  -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
 -mdivsi3_libfunc=@var{name}  @gol
 -madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
@@ -930,21 +932,27 @@ C++ header file to be turned into a precompiled header.
 
 @item @var{file}.f
 @itemx @var{file}.for
-@itemx @var{file}.FOR
+@itemx @var{file}.ftn
 Fixed form Fortran source code which should not be preprocessed.
 
 @item @var{file}.F
+@itemx @var{file}.FOR
 @itemx @var{file}.fpp
 @itemx @var{file}.FPP
+@itemx @var{file}.FTN
 Fixed form Fortran source code which must be preprocessed (with the traditional
 preprocessor).
 
 @item @var{file}.f90
 @itemx @var{file}.f95
+@itemx @var{file}.f03
+@itemx @var{file}.f08
 Free form Fortran source code which should not be preprocessed.
 
 @item @var{file}.F90
 @itemx @var{file}.F95
+@itemx @var{file}.F03
+@itemx @var{file}.F08
 Free form Fortran source code which must be preprocessed (with the
 traditional preprocessor).
 
@@ -961,7 +969,7 @@ instantiation), or a library unit renaming declaration (a package,
 generic, or subprogram renaming declaration).  Such files are also
 called @dfn{specs}.
 
-@itemx @var{file}.adb
+@item @var{file}.adb
 Ada source code file containing a library unit body (a subprogram or
 package body).  Such files are also called @dfn{bodies}.
 
@@ -4431,7 +4439,7 @@ dbg_cnt(dce) will return true only for first 10 invocations
 and dbg_cnt(tail_call) will return false always.
 
 @item -d@var{letters}
-@item -fdump-rtl-@var{pass}
+@itemx -fdump-rtl-@var{pass}
 @opindex d
 Says to make debugging dumps during compilation at times specified by
 @var{letters}.    This is used for debugging the RTL-based passes of the
@@ -4451,16 +4459,16 @@ letters for use in @var{letters} and @var{pass}, and their meanings:
 @opindex dA
 Annotate the assembler output with miscellaneous debugging information.
 
-@itemx -fdump-rtl-bbro
+@item -fdump-rtl-bbro
 @opindex fdump-rtl-bbro
 Dump after block reordering, to @file{@var{file}.148r.bbro}.
 
-@itemx -fdump-rtl-combine
+@item -fdump-rtl-combine
 @opindex fdump-rtl-combine
 Dump after the RTL instruction combination pass, to the file
 @file{@var{file}.129r.combine}.
 
-@itemx -fdump-rtl-ce1
+@item -fdump-rtl-ce1
 @itemx -fdump-rtl-ce2
 @opindex fdump-rtl-ce1
 @opindex fdump-rtl-ce2
@@ -4469,7 +4477,7 @@ first if conversion, to the file @file{@var{file}.117r.ce1}.
 @option{-fdump-rtl-ce2} enable dumping after the second if
 conversion, to the file @file{@var{file}.130r.ce2}.
 
-@itemx -fdump-rtl-btl
+@item -fdump-rtl-btl
 @itemx -fdump-rtl-dbr
 @opindex fdump-rtl-btl
 @opindex fdump-rtl-dbr
@@ -4483,11 +4491,11 @@ scheduling, to @file{@var{file}.36.dbr}.
 Dump all macro definitions, at the end of preprocessing, in addition to
 normal output.
 
-@itemx -fdump-rtl-ce3
+@item -fdump-rtl-ce3
 @opindex fdump-rtl-ce3
 Dump after the third if conversion, to @file{@var{file}.146r.ce3}.
 
-@itemx -fdump-rtl-cfg
+@item -fdump-rtl-cfg
 @itemx -fdump-rtl-life
 @opindex fdump-rtl-cfg
 @opindex fdump-rtl-life
@@ -4496,11 +4504,11 @@ and data flow analysis, to @file{@var{file}.116r.cfg}.
 @option{-fdump-rtl-cfg} enable dumping dump after life analysis,
 to @file{@var{file}.128r.life1} and @file{@var{file}.135r.life2}.
 
-@itemx -fdump-rtl-greg
+@item -fdump-rtl-greg
 @opindex fdump-rtl-greg
 Dump after global register allocation, to @file{@var{file}.139r.greg}.
 
-@itemx -fdump-rtl-gcse
+@item -fdump-rtl-gcse
 @itemx -fdump-rtl-bypass
 @opindex fdump-rtl-gcse
 @opindex fdump-rtl-bypass
@@ -4509,28 +4517,28 @@ Dump after global register allocation, to @file{@var{file}.139r.greg}.
 enable dumping after jump bypassing and control flow optimizations, to
 @file{@var{file}.115r.bypass}.
 
-@itemx -fdump-rtl-eh
+@item -fdump-rtl-eh
 @opindex fdump-rtl-eh
 Dump after finalization of EH handling code, to @file{@var{file}.02.eh}.
 
-@itemx -fdump-rtl-sibling
+@item -fdump-rtl-sibling
 @opindex fdump-rtl-sibling
 Dump after sibling call optimizations, to @file{@var{file}.106r.sibling}.
 
-@itemx -fdump-rtl-jump
+@item -fdump-rtl-jump
 @opindex fdump-rtl-jump
 Dump after the first jump optimization, to @file{@var{file}.112r.jump}.
 
-@itemx -fdump-rtl-stack
+@item -fdump-rtl-stack
 @opindex fdump-rtl-stack
 Dump after conversion from GCC's "flat register file" registers to the
 x87's stack-like registers, to @file{@var{file}.152r.stack}.
 
-@itemx -fdump-rtl-lreg
+@item -fdump-rtl-lreg
 @opindex fdump-rtl-lreg
 Dump after local register allocation, to @file{@var{file}.138r.lreg}.
 
-@itemx -fdump-rtl-loop2
+@item -fdump-rtl-loop2
 @opindex fdump-rtl-loop2
 @option{-dL} and @option{-fdump-rtl-loop2} enable dumping after the
 loop optimization pass, to @file{@var{file}.119r.loop2},
@@ -4538,54 +4546,54 @@ loop optimization pass, to @file{@var{file}.119r.loop2},
 @file{@var{file}.121r.loop2_invariant}, and
 @file{@var{file}.125r.loop2_done}.
 
-@itemx -fdump-rtl-sms
+@item -fdump-rtl-sms
 @opindex fdump-rtl-sms
 Dump after modulo scheduling, to @file{@var{file}.136r.sms}.
 
-@itemx -fdump-rtl-mach
+@item -fdump-rtl-mach
 @opindex fdump-rtl-mach
 Dump after performing the machine dependent reorganization pass, to
 @file{@var{file}.155r.mach} if that pass exists.
 
-@itemx -fdump-rtl-rnreg
+@item -fdump-rtl-rnreg
 @opindex fdump-rtl-rnreg
 Dump after register renumbering, to @file{@var{file}.147r.rnreg}.
 
-@itemx -fdump-rtl-regmove
+@item -fdump-rtl-regmove
 @opindex fdump-rtl-regmove
 Dump after the register move pass, to @file{@var{file}.132r.regmove}.
 
-@itemx -fdump-rtl-postreload
+@item -fdump-rtl-postreload
 @opindex fdump-rtl-postreload
 Dump after post-reload optimizations, to @file{@var{file}.24.postreload}.
 
-@itemx -fdump-rtl-expand
+@item -fdump-rtl-expand
 @opindex fdump-rtl-expand
 Dump after RTL generation, to @file{@var{file}.104r.expand}.
 
-@itemx -fdump-rtl-sched2
+@item -fdump-rtl-sched2
 @opindex fdump-rtl-sched2
 Dump after the second scheduling pass, to @file{@var{file}.149r.sched2}.
 
-@itemx -fdump-rtl-cse
+@item -fdump-rtl-cse
 @opindex fdump-rtl-cse
 Dump after CSE (including the jump optimization that sometimes follows
 CSE), to @file{@var{file}.113r.cse}.
 
-@itemx -fdump-rtl-sched1
+@item -fdump-rtl-sched1
 @opindex fdump-rtl-sched1
 Dump after the first scheduling pass, to @file{@var{file}.136r.sched1}.
 
-@itemx -fdump-rtl-cse2
+@item -fdump-rtl-cse2
 @opindex fdump-rtl-cse2
 Dump after the second CSE pass (including the jump optimization that
 sometimes follows CSE), to @file{@var{file}.127r.cse2}.
 
-@itemx -fdump-rtl-tracer
+@item -fdump-rtl-tracer
 @opindex fdump-rtl-tracer
 Dump after running tracer, to @file{@var{file}.118r.tracer}.
 
-@itemx -fdump-rtl-vpt
+@item -fdump-rtl-vpt
 @itemx -fdump-rtl-vartrack
 @opindex fdump-rtl-vpt
 @opindex fdump-rtl-vartrack
@@ -4594,19 +4602,19 @@ profile transformations, to @file{@var{file}.10.vpt}.
 @option{-fdump-rtl-vartrack} enable dumping after variable tracking,
 to @file{@var{file}.154r.vartrack}.
 
-@itemx -fdump-rtl-flow2
+@item -fdump-rtl-flow2
 @opindex fdump-rtl-flow2
 Dump after the second flow pass, to @file{@var{file}.142r.flow2}.
 
-@itemx -fdump-rtl-peephole2
+@item -fdump-rtl-peephole2
 @opindex fdump-rtl-peephole2
 Dump after the peephole pass, to @file{@var{file}.145r.peephole2}.
 
-@itemx -fdump-rtl-web
+@item -fdump-rtl-web
 @opindex fdump-rtl-web
 Dump after live range splitting, to @file{@var{file}.126r.web}.
 
-@itemx -fdump-rtl-all
+@item -fdump-rtl-all
 @opindex fdump-rtl-all
 Produce all the dumps listed above.
 
@@ -6156,13 +6164,22 @@ using twos complement arithmetic.  When this option is in effect any
 attempt to determine whether an operation on signed numbers will
 overflow must be written carefully to not actually involve overflow.
 
+This option also allows the compiler to assume strict pointer
+semantics: given a pointer to an object, if adding an offset to that
+pointer does not produce a pointer to the same object, the addition is
+undefined.  This permits the compiler to conclude that @code{p + u >
+p} is always true for a pointer @code{p} and unsigned integer
+@code{u}.  This assumption is only valid because pointer wraparound is
+undefined, as the expression is false if @code{p + u} overflows using
+twos complement arithmetic.
+
 See also the @option{-fwrapv} option.  Using @option{-fwrapv} means
-that signed overflow is fully defined: it wraps.  When
+that integer signed overflow is fully defined: it wraps.  When
 @option{-fwrapv} is used, there is no difference between
-@option{-fstrict-overflow} and @option{-fno-strict-overflow}.  With
-@option{-fwrapv} certain types of overflow are permitted.  For
-example, if the compiler gets an overflow when doing arithmetic on
-constants, the overflowed value can still be used with
+@option{-fstrict-overflow} and @option{-fno-strict-overflow} for
+integers.  With @option{-fwrapv} certain types of overflow are
+permitted.  For example, if the compiler gets an overflow when doing
+arithmetic on constants, the overflowed value can still be used with
 @option{-fwrapv}, but not otherwise.
 
 The @option{-fstrict-overflow} option is enabled at levels
@@ -6314,7 +6331,19 @@ and occasionally eliminate the copy.
 
 Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}.
 
+@item -fprofile-dir=@var{path}
+@opindex fprofile-dir
+
+Set the directory to search the profile data files in to @var{path}.
+This option affects only the profile data generated by
+@option{-fprofile-generate}, @option{-ftest-coverage}, @option{-fprofile-arcs}
+and used by @option{-fprofile-use} and @option{-fbranch-probabilities} 
+and its related options.
+By default, GCC will use the current directory as @var{path}
+thus the profile data file will appear in the same directory as the object file.
+
 @item -fprofile-generate
+@itemx -fprofile-generate=@var{path}
 @opindex fprofile-generate
 
 Enable options usually used for instrumenting application to produce
@@ -6324,7 +6353,11 @@ compiling and when linking your program.
 
 The following options are enabled: @code{-fprofile-arcs}, @code{-fprofile-values}, @code{-fvpt}.
 
+If @var{path} is specified, GCC will look at the @var{path} to find
+the profile feeedback data files. See @option{-fprofile-dir}.
+
 @item -fprofile-use
+@itemx -fprofile-use=@var{path}
 @opindex fprofile-use
 Enable profile feedback directed optimizations, and optimizations
 generally profitable only with profile feedback available.
@@ -6336,6 +6369,9 @@ By default, GCC emits an error message if the feedback profiles do not
 match the source code.  This error can be turned into a warning by using
 @option{-Wcoverage-mismatch}.  Note this may result in poorly optimized
 code.
+
+If @var{path} is specified, GCC will look at the @var{path} to find
+the profile feedback data files. See @option{-fprofile-dir}.
 @end table
 
 The following options control compiler behavior regarding floating
@@ -8542,7 +8578,7 @@ assembly code.  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a8}, @samp{cortex-r4}, @samp{cortex-m3}, @samp{cortex-m1},
 @samp{xscale}, @samp{iwmmxt}, @samp{ep9312}.
 
-@itemx -mtune=@var{name}
+@item -mtune=@var{name}
 @opindex mtune
 This option is very similar to the @option{-mcpu=} option, except that
 instead of specifying the actual target processor type, and hence
@@ -9320,7 +9356,6 @@ one controlled by the @option{-mcpu} or @option{-march} option.
 @itemx -unexported_symbols_list
 @itemx -weak_reference_mismatches
 @itemx -whatsloaded
-
 @opindex allowable_client
 @opindex client_name
 @opindex compatibility_version
@@ -9379,7 +9414,6 @@ one controlled by the @option{-mcpu} or @option{-march} option.
 @opindex unexported_symbols_list
 @opindex weak_reference_mismatches
 @opindex whatsloaded
-
 These options are passed to the Darwin linker.  The Darwin linker man page
 describes them in detail.
 @end table
@@ -10691,29 +10725,33 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 
 @item -mmmx
 @itemx -mno-mmx
-@item -msse
+@itemx -msse
 @itemx -mno-sse
-@item -msse2
+@itemx -msse2
 @itemx -mno-sse2
-@item -msse3
+@itemx -msse3
 @itemx -mno-sse3
-@item -mssse3
+@itemx -mssse3
 @itemx -mno-ssse3
-@item -msse4.1
+@itemx -msse4.1
 @itemx -mno-sse4.1
-@item -msse4.2
+@itemx -msse4.2
 @itemx -mno-sse4.2
-@item -msse4
+@itemx -msse4
 @itemx -mno-sse4
-@item -msse4a
-@item -mno-sse4a
-@item -msse5
+@itemx -maes
+@itemx -mno-aes
+@itemx -mpclmul
+@itemx -mno-pclmul
+@itemx -msse4a
+@itemx -mno-sse4a
+@itemx -msse5
 @itemx -mno-sse5
-@item -m3dnow
+@itemx -m3dnow
 @itemx -mno-3dnow
-@item -mpopcnt
+@itemx -mpopcnt
 @itemx -mno-popcnt
-@item -mabm
+@itemx -mabm
 @itemx -mno-abm
 @opindex mmmx
 @opindex mno-mmx
@@ -10722,8 +10760,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @opindex m3dnow
 @opindex mno-3dnow
 These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4A, SSE5, ABM or 3DNow!@: extended
-instruction sets.
+SSE, SSE2, SSE3, SSSE3, SSE4.1, AES, PCLMUL, SSE4A, SSE5, ABM or
+3DNow!@: extended instruction sets.
 These extensions are also available as built-in functions: see
 @ref{X86 Built-in Functions}, for details of the functions enabled and
 disabled by these switches.
@@ -10770,15 +10808,26 @@ decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
 @item -mveclibabi=@var{type}
 @opindex mveclibabi
 Specifies the ABI type to use for vectorizing intrinsics using an
-external library.  Supported types are @code{acml} for the AMD
-math core library style of interfacing.  GCC will currently emit
-calls to @code{__vrd2_sin}, @code{__vrd2_cos}, @code{__vrd2_exp},
-@code{__vrd2_log}, @code{__vrd2_log2}, @code{__vrd2_log10},
-@code{__vrs4_sinf}, @code{__vrs4_cosf}, @code{__vrs4_expf},
-@code{__vrs4_logf}, @code{__vrs4_log2f}, @code{__vrs4_log10f}
-and @code{__vrs4_powf} when using this type and @option{-ftree-vectorize}
-is enabled.  A ACML ABI compatible library will have to be specified
-at link time.
+external library.  Supported types are @code{svml} for the Intel short
+vector math library and @code{acml} for the AMD math core library style
+of interfacing.  GCC will currently emit calls to @code{vmldExp2},
+@code{vmldLn2}, @code{vmldLog102}, @code{vmldLog102}, @code{vmldPow2},
+@code{vmldTanh2}, @code{vmldTan2}, @code{vmldAtan2}, @code{vmldAtanh2},
+@code{vmldCbrt2}, @code{vmldSinh2}, @code{vmldSin2}, @code{vmldAsinh2},
+@code{vmldAsin2}, @code{vmldCosh2}, @code{vmldCos2}, @code{vmldAcosh2},
+@code{vmldAcos2}, @code{vmlsExp4}, @code{vmlsLn4}, @code{vmlsLog104},
+@code{vmlsLog104}, @code{vmlsPow4}, @code{vmlsTanh4}, @code{vmlsTan4},
+@code{vmlsAtan4}, @code{vmlsAtanh4}, @code{vmlsCbrt4}, @code{vmlsSinh4},
+@code{vmlsSin4}, @code{vmlsAsinh4}, @code{vmlsAsin4}, @code{vmlsCosh4},
+@code{vmlsCos4}, @code{vmlsAcosh4} and @code{vmlsAcos4} for corresponding
+function type when @option{-mveclibabi=svml} is used and @code{__vrd2_sin},
+@code{__vrd2_cos}, @code{__vrd2_exp}, @code{__vrd2_log}, @code{__vrd2_log2},
+@code{__vrd2_log10}, @code{__vrs4_sinf}, @code{__vrs4_cosf},
+@code{__vrs4_expf}, @code{__vrs4_logf}, @code{__vrs4_log2f},
+@code{__vrs4_log10f} and @code{__vrs4_powf} for corresponding function type
+when @option{-mveclibabi=acml} is used. Both @option{-ftree-vectorize} and
+@option{-funsafe-math-optimizations} have to be enabled. A SVML or ACML ABI
+compatible library will have to be specified at link time.
 
 @item -mpush-args
 @itemx -mno-push-args
@@ -12977,7 +13026,7 @@ the AltiVec instruction set.  You may also need to set
 enhancements.
 
 @item -mvrsave
-@item -mno-vrsave
+@itemx -mno-vrsave
 @opindex mvrsave
 @opindex mno-vrsave
 Generate VRSAVE instructions when generating AltiVec code.
@@ -13604,7 +13653,7 @@ to build a linux kernel use @option{-msoft-float}.
 The default is to not maintain the backchain.
 
 @item -mpacked-stack
-@item -mno-packed-stack
+@itemx -mno-packed-stack
 @opindex mpacked-stack
 @opindex mno-packed-stack
 Use (do not use) the packed stack layout.  When @option{-mno-packed-stack} is
@@ -13725,7 +13774,7 @@ Emit a warning if the function calls alloca or uses dynamically
 sized arrays.  This is generally a bad idea with a limited stack size.
 
 @item -mstack-guard=@var{stack-guard}
-@item -mstack-size=@var{stack-size}
+@itemx -mstack-size=@var{stack-size}
 @opindex mstack-guard
 @opindex mstack-size
 If these options are provided the s390 back end emits additional instructions in
@@ -13879,6 +13928,10 @@ linker option @option{-relax}.
 Use 32-bit offsets in @code{switch} tables.  The default is to use
 16-bit offsets.
 
+@item -mbitops
+@opindex mbitops
+Enable the use of bit manipulation instructions on SH2A.
+
 @item -mfmovd
 @opindex mfmovd
 Enable the use of the instruction @code{fmovd}.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index bd4150f35ca..a4117a34efb 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2239,7 +2239,7 @@ range of 1 to 2047.
 
 @end table
 
-@item Blackfin family---@file{config/bfin/bfin.h}
+@item Blackfin family---@file{config/bfin/constraints.md}
 @table @code
 @item a
 P register
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 90c56d909d4..e99b381a9ae 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -1712,82 +1712,176 @@ This virtual register is replaced by the sum of the register given by
 @end table
 
 @findex subreg
-@item (subreg:@var{m} @var{reg} @var{bytenum})
+@item (subreg:@var{m1} @var{reg:m2} @var{bytenum})
+
 @code{subreg} expressions are used to refer to a register in a machine
 mode other than its natural one, or to refer to one register of
 a multi-part @code{reg} that actually refers to several registers.
 
-Each pseudo-register has a natural mode.  If it is necessary to
-operate on it in a different mode---for example, to perform a fullword
-move instruction on a pseudo-register that contains a single
-byte---the pseudo-register must be enclosed in a @code{subreg}.  In
-such a case, @var{bytenum} is zero.
-
-Usually @var{m} is at least as narrow as the mode of @var{reg}, in which
-case it is restricting consideration to only the bits of @var{reg} that
-are in @var{m}.
-
-Sometimes @var{m} is wider than the mode of @var{reg}.  These
-@code{subreg} expressions are often called @dfn{paradoxical}.  They are
-used in cases where we want to refer to an object in a wider mode but do
-not care what value the additional bits have.  The reload pass ensures
-that paradoxical references are only made to hard registers.
-
-The other use of @code{subreg} is to extract the individual registers of
-a multi-register value.  Machine modes such as @code{DImode} and
-@code{TImode} can indicate values longer than a word, values which
-usually require two or more consecutive registers.  To access one of the
-registers, use a @code{subreg} with mode @code{SImode} and a
-@var{bytenum} offset that says which register.
-
-Storing in a non-paradoxical @code{subreg} has undefined results for
-bits belonging to the same word as the @code{subreg}.  This laxity makes
-it easier to generate efficient code for such instructions.  To
-represent an instruction that preserves all the bits outside of those in
-the @code{subreg}, use @code{strict_low_part} around the @code{subreg}.
+Each pseudo register has a natural mode.  If it is necessary to
+operate on it in a different mode, the pseudo register must be
+enclosed in a @code{subreg}.  
+
+It is seldom necessary to wrap hard registers in @code{subreg}s; such
+registers would normally reduce to a single @code{reg} rtx.  This use of
+@code{subregs} is discouraged and may not be supported in the future.
+
+@code{subreg}s come in two distinct flavors, each having its own
+usage and rules:
+
+@table @asis
+@item Paradoxical subregs
+When @var{m1} is strictly wider than @var{m2}, the @code{subreg}
+expression is called @dfn{paradoxical}.  The canonical test for this
+class of @code{subreg} is:
+
+@smallexample
+GET_MODE_SIZE (@var{m1}) > GET_MODE_SIZE (@var{m2})
+@end smallexample
+
+Paradoxical @code{subreg}s can be used as both lvalues and rvalues.
+When used as an rvalue, the low-order bits of the @code{subreg} are
+taken from @var{reg} while the high-order bits are left undefined.
+When used as an lvalue, the low-order bits of the source value are
+stored in @var{reg} and the high-order bits are discarded.
+
+@var{bytenum} is always zero for a paradoxical @code{subreg}, even on
+big-endian targets.
+
+For example, the paradoxical @code{subreg}:
+
+@smallexample
+(set (subreg:SI (reg:HI @var{x}) 0) @var{y})
+@end smallexample
+
+stores the lower 2 bytes of @var{y} in @var{x} and discards the upper
+2 bytes.  A subsequent:
 
+@smallexample
+(set @var{z} (subreg:SI (reg:HI @var{x}) 0))
+@end smallexample
+
+would set the lower two bytes of @var{z} to @var{y} and set the upper two
+bytes to an unknown value.
+
+@item Normal subregs 
+When @var{m1} is at least as narrow as @var{m2} the @code{subreg}
+expression is called @dfn{normal}.
+
+Normal @code{subreg}s restrict consideration to certain bits of @var{reg}.
+There are two cases.  If @var{m1} is smaller than a word, the
+@code{subreg} refers to the least-significant part (or @dfn{lowpart})
+of one word of @var{reg}.  If @var{m1} is word-sized or greater, the
+@code{subreg} refers to one or more complete words.
+
+When used as an lvalue, @code{subreg} is a word-based accessor.
+Storing to a @code{subreg} modifies all the words of @var{reg} that
+overlap the @code{subreg}, but it leaves the other words of @var{reg}
+alone.
+
+When storing to a normal @code{subreg} that is smaller than a word,
+the other bits of the referenced word are usually left in an undefined
+state.  This laxity makes it easier to generate efficient code for
+such instructions.  To represent an instruction that preserves all the
+bits outside of those in the @code{subreg}, use @code{strict_low_part}
+or @code{zero_extract} around the @code{subreg}.
+
+@var{bytenum} must identify the offset of the first byte of the
+@code{subreg} from the start of @var{reg}, assuming that @var{reg} is
+laid out in memory order.  The memory order of bytes is defined by
+two target macros, @code{WORDS_BIG_ENDIAN} and @code{BYTES_BIG_ENDIAN}:
+
+@itemize
+@item
 @cindex @code{WORDS_BIG_ENDIAN}, effect on @code{subreg}
-The compilation parameter @code{WORDS_BIG_ENDIAN}, if set to 1, says
-that byte number zero is part of the most significant word; otherwise,
-it is part of the least significant word.
+@code{WORDS_BIG_ENDIAN}, if set to 1, says that byte number zero is
+part of the most significant word; otherwise, it is part of the least
+significant word.
 
+@item
 @cindex @code{BYTES_BIG_ENDIAN}, effect on @code{subreg}
-The compilation parameter @code{BYTES_BIG_ENDIAN}, if set to 1, says
-that byte number zero is the most significant byte within a word;
-otherwise, it is the least significant byte within a word.
+@code{BYTES_BIG_ENDIAN}, if set to 1, says that byte number zero is
+the most significant byte within a word; otherwise, it is the least
+significant byte within a word.
+@end itemize
 
 @cindex @code{FLOAT_WORDS_BIG_ENDIAN}, (lack of) effect on @code{subreg}
 On a few targets, @code{FLOAT_WORDS_BIG_ENDIAN} disagrees with
-@code{WORDS_BIG_ENDIAN}.
-However, most parts of the compiler treat floating point values as if
-they had the same endianness as integer values.  This works because
-they handle them solely as a collection of integer values, with no
-particular numerical value.  Only real.c and the runtime libraries
-care about @code{FLOAT_WORDS_BIG_ENDIAN}.
-
-@cindex combiner pass
-@cindex reload pass
-@cindex @code{subreg}, special reload handling
-Between the combiner pass and the reload pass, it is possible to have a
-paradoxical @code{subreg} which contains a @code{mem} instead of a
-@code{reg} as its first operand.  After the reload pass, it is also
-possible to have a non-paradoxical @code{subreg} which contains a
-@code{mem}; this usually occurs when the @code{mem} is a stack slot
-which replaced a pseudo register.
-
-Note that it is not valid to access a @code{DFmode} value in @code{SFmode}
-using a @code{subreg}.  On some machines the most significant part of a
-@code{DFmode} value does not have the same format as a single-precision
-floating value.
-
-It is also not valid to access a single word of a multi-word value in a
-hard register when less registers can hold the value than would be
-expected from its size.  For example, some 32-bit machines have
-floating-point registers that can hold an entire @code{DFmode} value.
-If register 10 were such a register @code{(subreg:SI (reg:DF 10) 4)}
-would be invalid because there is no way to convert that reference to
-a single machine register.  The reload pass prevents @code{subreg}
-expressions such as these from being formed.
+@code{WORDS_BIG_ENDIAN}.  However, most parts of the compiler treat
+floating point values as if they had the same endianness as integer
+values.  This works because they handle them solely as a collection of
+integer values, with no particular numerical value.  Only real.c and
+the runtime libraries care about @code{FLOAT_WORDS_BIG_ENDIAN}.
+
+Thus, 
+
+@smallexample
+(subreg:HI (reg:SI @var{x}) 2)
+@end smallexample
+
+on a @code{BYTES_BIG_ENDIAN}, @samp{UNITS_PER_WORD == 4} target is the same as
+
+@smallexample
+(subreg:HI (reg:SI @var{x}) 0)
+@end smallexample
+
+on a little-endian, @samp{UNITS_PER_WORD == 4} target.  Both
+@code{subreg}s access the lower two bytes of register @var{x}.
+
+@end table
+
+A @code{MODE_PARTIAL_INT} mode behaves as if it were as wide as the
+corresponding @code{MODE_INT} mode, except that it has an unknown
+number of undefined bits.  For example:
+
+@smallexample
+(subreg:PSI (reg:SI 0) 0)
+@end smallexample
+
+accesses the whole of @samp{(reg:SI 0)}, but the exact relationship
+between the @code{PSImode} value and the @code{SImode} value is not
+defined.  If we assume @samp{UNITS_PER_WORD <= 4}, then the following
+two @code{subreg}s:
+
+@smallexample
+(subreg:PSI (reg:DI 0) 0)
+(subreg:PSI (reg:DI 0) 4)
+@end smallexample
+
+represent independent 4-byte accesses to the two halves of
+@samp{(reg:DI 0)}.  Both @code{subreg}s have an unknown number
+of undefined bits.
+
+If @samp{UNITS_PER_WORD <= 2} then these two @code{subreg}s:
+
+@smallexample
+(subreg:HI (reg:PSI 0) 0)
+(subreg:HI (reg:PSI 0) 2)
+@end smallexample
+
+represent independent 2-byte accesses that together span the whole
+of @samp{(reg:PSI 0)}.  Storing to the first @code{subreg} does not
+affect the value of the second, and vice versa.  @samp{(reg:PSI 0)}
+has an unknown number of undefined bits, so the assignment:
+
+@smallexample
+(set (subreg:HI (reg:PSI 0) 0) (reg:HI 4))
+@end smallexample
+
+does not guarantee that @samp{(subreg:HI (reg:PSI 0) 0)} has the
+value @samp{(reg:HI 4)}.
+
+@cindex @code{CANNOT_CHANGE_MODE_CLASS} and subreg semantics
+The rules above apply to both pseudo @var{reg}s and hard @var{reg}s.
+If the semantics are not correct for particular combinations of
+@var{m1}, @var{m2} and hard @var{reg}, the target-specific code
+must ensure that those combinations are never used.  For example:
+
+@smallexample
+CANNOT_CHANGE_MODE_CLASS (@var{m2}, @var{m1}, @var{class})
+@end smallexample
+
+must be true for every class @var{class} that includes @var{reg}.
 
 @findex SUBREG_REG
 @findex SUBREG_BYTE
@@ -1795,6 +1889,14 @@ The first operand of a @code{subreg} expression is customarily accessed
 with the @code{SUBREG_REG} macro and the second operand is customarily
 accessed with the @code{SUBREG_BYTE} macro.
 
+@code{subreg}s of @code{subreg}s are not supported.  Using
+@code{simplify_gen_subreg} is the recommended way to avoid this problem.
+
+It has been several years since a platform in which
+@code{BYTES_BIG_ENDIAN} was not equal to @code{WORDS_BIG_ENDIAN} has
+been tested.  Anyone wishing to support such a platform in the future
+may be confronted with code rot.
+
 @findex scratch
 @cindex scratch operands
 @item (scratch:@var{m})
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index d4b77534567..896190cd536 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -340,6 +340,7 @@ The section ``Funding Free Software''.
 @item gcc-common.texi
 Common definitions for manuals.
 @item gpl.texi
+@itemx gpl_v3.texi
 The GNU General Public License.
 @item texinfo.tex
 A copy of @file{texinfo.tex} known to work with the GCC manuals.
@@ -642,6 +643,9 @@ all generated files in the source directory that are not checked into
 CVS, but should not delete anything checked into CVS@.
 @end table
 
+@file{Make-lang.in} must also define a variable @code{@var{lang}_OBJS}
+to a list of host object files that are used by that language.
+
 @item lang.opt
 This file registers the set of switches that the front end accepts on
 the command line, and their @option{--help} text.  @xref{Options}.