diff options
| author | Eric Botcazou <ebotcazou@adacore.com> | 2005-11-07 19:14:02 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@adacore.com> | 2005-11-07 19:14:02 +0000 |
| commit | 40b6af7819c0722b7c51e9377f91bfa30d91b02d (patch) | |
| tree | 001232e238f771969576c56eb45c370bca7b23a8 /gcc/doc | |
| parent | 191f83b7b59aaa565a843906b2749bda2d050838 (diff) | |
* expmed.c (extract_bit_field): Do not use insv/extv/extzv patterns
if the bitsize is zero.
* doc/md.texi (Standard Pattern Names): Document it.
* config/ia64/ia64.c (ia64_pass_by_reference): Delete.
(TARGET_PASS_BY_REFERENCE): Likewise.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@106605 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/md.texi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 36b02739070..4fc8c3b76cc 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3551,7 +3551,7 @@ Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often be valid for @code{word_mode}. The RTL generation pass generates this instruction only with constants -for operands 2 and 3. +for operands 2 and 3 and the constant is never zero for operand 2. The bit-field value is sign-extended to a full word integer before it is stored in operand 0. @@ -3569,7 +3569,7 @@ operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or Operands 1 and 2 must be valid for @code{word_mode}. The RTL generation pass generates this instruction only with constants -for operands 1 and 2. +for operands 1 and 2 and the constant is never zero for operand 1. @cindex @code{mov@var{mode}cc} instruction pattern @item @samp{mov@var{mode}cc} |