2004-09-23 Dorit Naishlos <dorit@il.ibm.com>

        * tree.def (ALIGN_INDIRECT_REF, MISALIGNED_INDIRECT_REF):
        New tree-codes.
        * tree.h (REF_ORIGINAL): Consider ALIGN_INDIRECT_REF and
        MISALIGNED_INDIRECT_REF.
        * alias.c (get_alias_set, nonoverlapping_memrefs_p): Likewise.
        * emit-rtl.c (mem_expr_equal_p, set_mem_attributes_minus_bitpos):
        Likewise.
        * expr.c (safe_from_p, expand_expr_real_1, rewrite_address_base)
        (find_interesting_uses_address): Likewise.
        * fold-const.c (non_lvalue, operand_equal_p): Likewise.
        (build_fold_addr_expr_with_type): Likewise.
        * gimplify.c (gimplify_addr_expr, gimplify_expr): Likewise.
        * print-rtl.c (print_mem_expr): Likewise.
        * tree-dump.c (dequeue_and_dump): Likewise.
        * tree-eh.c (tree_could_trap_p): Likewise.
        * tree-gimple.c (is_gimple_addressable, get_base_address): Likewise.
        * tree-pretty-print.c (op_prio, op_symbol, dump_generic_node): Likewise.
        * tree-ssa-alias.c (find_ptr_dereference, ptr_is_dereferenced_by):
        Likewise.
        * tree-ssa-dce.c (mark_stmt_if_obviously_necessary): Likewise.
        * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
        * tree-ssa-loop-im.c (for_each_index, is_call_clobbered_ref): Likewise.
        * tree-ssa-loop-ivopts.c (find_interesting_uses_address): Likewise.
        (add_address_candidates, rewrite_address_base): Likewise.
        * tree-ssa-operands.c (get_expr_operands, get_indirect_ref_operands):
        Likewise.
        * tree.c (staticp, build1_stat): Likewise.

        * tree.def (REALIGN_LOAD_EXPR, REALIGN_STORE_EXPR): New tree-codes.
        * tree-pretty-print.c (dump_generic_node): Consider REALIGN_LOAD_EXPR.
        * tree-ssa-operands.c (get_expr_operands): Likewise.
        * expr.c (expand_expr_real_1): Likewise.

        * optabs.h (vec_realign_store_optab, vec_realign_load_optab): New
        optabs.
        (OTI_vec_realign_store, OTI_vec_realign_load): New optab_index values
        for the new optabs.
        (expand_ternary_op): New function.
        * genopinit.c (optabs): Handle the new optabs.
        * optabs.c (optab_for_tree_code): Add cases for the new tree-codes.
        (init_optabs): Initialize vec_realign_load_optab.
        (expand_ternary_op): New functions.

        * target-def.h (TARGET_VECTORIZE): New member for struct gcc_target.
        (TARGET_VECTORIZE_MISALIGNED_MEM_OK): New member for targetm.vectorize.
        (TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD): Likewise.
        (TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE): Likewise.
        * target.h (struct vectorize): New member for struct gcc_target.
        (misaligned_mem_ok): New member for targetm.vectorize.
        (builtin_mask_for_load): Likewise.
        (builtin_mask_for_store): Likewise.
        * targethooks.c (default_vect_misaligned_mem_ok): New function.
        * targethooks.h (default_vect_misaligned_mem_ok): New function.

        * config/rs6000/altivec.md (build_vector_mask_for_load): New
        define_expand.
        (vec_realign_load_v4si, vec_realign_load_v4sf, vec_realign_load_v8hi)
        (vec_realign_load_v16qi): New define_insn.
        * config/rs6000/rs6000.h (ALTIVEC_BUILTIN_MASK_FOR_LOAD):
        (ALTIVEC_BUILTIN_MASK_FOR_STORE): New target builtins.
        * config/rs6000/rs6000.c (altivec_builtin_mask_for_load):
        (altivec_builtin_mask_for_store): New variables.
        (rs6000_builtin_mask_for_load): New function. Implements
        TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD.
        (rs6000_builtin_mask_for_store): New function. Implements
        TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE.
        (rs6000_expand_builtin): Expand the target builtins
        builtin_mask_for_load and builtin_mask_for_store.
        (altivec_init_builtins): Initialize the new target builtins.
        * config/i386/i386.c (ix86_misaligned_mem_ok): New function.
        Implements the target hook TARGET_VECTORIZE_MISALIGNED_MEM_OK.

        * tree-vectorizer.c (vect_create_data_ref): Renamed to
        vect_create_data_ref_ptr. Returns a pointer instead of an array-ref.
        (vect_create_addr_base_for_vector_ref): Additional argument (offset).
        (vectorizable_store): Call vect_create_data_ref_ptr with additional
        arguments, and create an indirect_ref with its return value data_ref.
        Check aligned_access_p.
        (vectorizable_load): Handle misaligned loads, using software-pipelined
        scheme with REALIGN_LOAD_EXPR and ALIGN_INDIRECT_REF if
        vec_realign_load_optab is supported, or using a scheme without
        software-pipelining with MISALIGNED_INDIRECT_REF if the target hook
        misaligned_mem_ok is supported.

        (vect_finish_stmt_generation): Typo.
        (vect_enhance_data_refs_alignment): Rename loop_vinfo to loop_info.
        (vect_analyze_data_refs_alignment): Don't fail vectorization in the
        presence of misaligned loads.
        (vect_analyze_data_ref_access): Add check for constant init.
        (vect_get_symbl_and_dr): Remove duplicate line.
        * tree-vectorizer.h (DR_MISALIGNMENT): Add comment.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@87948 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 90 insertions, 0 deletions

diff --git a/gcc/optabs.c b/gcc/optabs.c
index 0b75a81cd7f..abb69700a04 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -286,6 +286,12 @@ optab_for_tree_code (enum tree_code code, tree type)
     case MIN_EXPR:
       return TYPE_UNSIGNED (type) ? umin_optab : smin_optab;
 
+    case REALIGN_STORE_EXPR:
+      return vec_realign_store_optab;
+
+    case REALIGN_LOAD_EXPR:
+      return vec_realign_load_optab;
+
     default:
       break;
     }
@@ -313,6 +319,88 @@ optab_for_tree_code (enum tree_code code, tree type)
     }
 }
 
+
+/* Generate code to perform an operation specified by TERNARY_OPTAB
+   on operands OP0, OP1 and OP2, with result having machine-mode MODE.
+
+   UNSIGNEDP is for the case where we have to widen the operands
+   to perform the operation.  It says to use zero-extension.
+
+   If TARGET is nonzero, the value
+   is generated there, if it is convenient to do so.
+   In all cases an rtx is returned for the locus of the value;
+   this may or may not be TARGET.  */
+
+rtx
+expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, 
+		   rtx op1, rtx op2, rtx target, int unsignedp) 
+{
+  int icode = (int) ternary_optab->handlers[(int) mode].insn_code;
+  enum machine_mode mode0 = insn_data[icode].operand[1].mode;
+  enum machine_mode mode1 = insn_data[icode].operand[2].mode;
+  enum machine_mode mode2 = insn_data[icode].operand[3].mode;
+  rtx temp;
+  rtx pat;
+  rtx xop0 = op0, xop1 = op1, xop2 = op2;
+
+  if (ternary_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
+    abort ();
+
+  if (!target
+      || ! (*insn_data[icode].operand[0].predicate) (target, mode))
+    temp = gen_reg_rtx (mode);
+  else
+    temp = target;
+
+  /* In case the insn wants input operands in modes different from
+     those of the actual operands, convert the operands.  It would
+     seem that we don't need to convert CONST_INTs, but we do, so
+     that they're properly zero-extended, sign-extended or truncated
+     for their mode.  */
+
+  if (GET_MODE (op0) != mode0 && mode0 != VOIDmode)
+    xop0 = convert_modes (mode0,
+                          GET_MODE (op0) != VOIDmode
+                          ? GET_MODE (op0) 
+                          : mode,
+                          xop0, unsignedp);
+
+  if (GET_MODE (op1) != mode1 && mode1 != VOIDmode)
+    xop1 = convert_modes (mode1,
+                          GET_MODE (op1) != VOIDmode
+                          ? GET_MODE (op1)
+                          : mode,
+                          xop1, unsignedp);
+
+  if (GET_MODE (op2) != mode2 && mode2 != VOIDmode)
+    xop2 = convert_modes (mode2,
+                          GET_MODE (op2) != VOIDmode
+                          ? GET_MODE (op2)
+                          : mode,
+                          xop2, unsignedp);
+
+  /* Now, if insn's predicates don't allow our operands, put them into
+     pseudo regs.  */
+  
+  if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)
+      && mode0 != VOIDmode) 
+    xop0 = copy_to_mode_reg (mode0, xop0);
+  
+  if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1)
+      && mode1 != VOIDmode)
+    xop1 = copy_to_mode_reg (mode1, xop1);
+    
+  if (! (*insn_data[icode].operand[3].predicate) (xop2, mode2)
+      && mode2 != VOIDmode)
+    xop2 = copy_to_mode_reg (mode2, xop2);
+    
+  pat = GEN_FCN (icode) (temp, xop0, xop1, xop2);
+    
+  emit_insn (pat);
+  return temp; 
+}
+
+
 /* Like expand_binop, but return a constant rtx if the result can be
    calculated at compile time.  The arguments and return value are
    otherwise the same as for expand_binop.  */
@@ -4657,6 +4745,8 @@ init_optabs (void)
   vec_extract_optab = init_optab (UNKNOWN);
   vec_set_optab = init_optab (UNKNOWN);
   vec_init_optab = init_optab (UNKNOWN);
+  vec_realign_load_optab = init_optab (UNKNOWN);
+
   /* Conversions.  */
   sext_optab = init_convert_optab (SIGN_EXTEND);
   zext_optab = init_convert_optab (ZERO_EXTEND);