diff options
| author | Richard Earnshaw <rearnsha@arm.com> | 2019-10-18 19:01:49 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2019-10-18 19:01:49 +0000 |
| commit | 582d95abcb07059e767e0ee1f7e868122d86de23 (patch) | |
| tree | c5af2c341d3df8179000e0ece11be36b74e123c5 /gcc/testsuite | |
| parent | f95d4f2525d70a7b1f716202dac0e6c1332ba2a2 (diff) | |
[arm] Perform early splitting of adddi3.
This patch causes the expansion of adddi3 to split the operation
immediately for Arm and Thumb-2. This is desirable as it frees up the
register allocator to pick what ever combination of registers suits
best and reduces the number of auxiliary patterns that we need in the
back-end. Three of the testcases that we disabled earlier are already
fixed by this patch. Finally, we add a new pattern to match the
canonicalization of add-with-carry when using an immediate of zero.
gcc:
* config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
* config/arm/arm.c (arm_decompose_di_binop): New function.
* config/arm/arm.md (adddi3): Also accept any const_int for op2.
If not generating Thumb-1 code, decompose the operation into 32-bit
pieces.
* add0si_carryin_<optab>: New pattern.
testsuite:
* gcc.target/arm/pr53447-1.c: Remove XFAIL.
* gcc.target/arm/pr53447-3.c: Remove XFAIL.
* gcc.target/arm/pr53447-4.c: Remove XFAIL.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@277165 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr53447-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr53447-3.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr53447-4.c | 2 |
4 files changed, 9 insertions, 3 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0c5b6e4180d..ae9d216e1e3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2019-10-18 Richard Earnshaw <rearnsha@arm.com> + * gcc.target/arm/pr53447-1.c: Remove XFAIL. + * gcc.target/arm/pr53447-3.c: Remove XFAIL. + * gcc.target/arm/pr53447-4.c: Remove XFAIL. + +2019-10-18 Richard Earnshaw <rearnsha@arm.com> + * gcc.target/arm/negdi-3.c: Add XFAILS. * gcc.target/arm/pr3447-1.c: Likewise. * gcc.target/arm/pr3447-3.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/pr53447-1.c b/gcc/testsuite/gcc.target/arm/pr53447-1.c index 0fd98b791fe..dc094180c85 100644 --- a/gcc/testsuite/gcc.target/arm/pr53447-1.c +++ b/gcc/testsuite/gcc.target/arm/pr53447-1.c @@ -1,6 +1,6 @@ /* { dg-options "-O2" } */ /* { dg-require-effective-target arm32 } */ -/* { dg-final { scan-assembler-not "mov" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "mov" } } */ void t0p(long long * p) { diff --git a/gcc/testsuite/gcc.target/arm/pr53447-3.c b/gcc/testsuite/gcc.target/arm/pr53447-3.c index 79d3691ee14..8e48f119b74 100644 --- a/gcc/testsuite/gcc.target/arm/pr53447-3.c +++ b/gcc/testsuite/gcc.target/arm/pr53447-3.c @@ -1,6 +1,6 @@ /* { dg-options "-O2" } */ /* { dg-require-effective-target arm32 } */ -/* { dg-final { scan-assembler-not "mov" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "mov" } } */ void t0p(long long * p) diff --git a/gcc/testsuite/gcc.target/arm/pr53447-4.c b/gcc/testsuite/gcc.target/arm/pr53447-4.c index bfa20df7ccd..22acb97270e 100644 --- a/gcc/testsuite/gcc.target/arm/pr53447-4.c +++ b/gcc/testsuite/gcc.target/arm/pr53447-4.c @@ -1,6 +1,6 @@ /* { dg-options "-O2" } */ /* { dg-require-effective-target arm32 } */ -/* { dg-final { scan-assembler-not "mov" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "mov" } } */ void t0p(long long * p) |