diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2015-02-12 10:00:42 +0000 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2015-02-12 10:00:42 +0000 |
| commit | 58e81a4d5202c6a2061ecd711ae435cfc84278f1 (patch) | |
| tree | d310bd218bce64871879352a531681bf0ed68bf1 /gcc | |
| parent | 3739b4cb58404fb90282a9112111979e49db0973 (diff) | |
| parent | ccd2bc35525fbf42d01c8c21f7a1e416e3a737f4 (diff) | |
Merge branches/gcc-4_8-branch rev 220524
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@220643 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
128 files changed, 3128 insertions, 415 deletions
diff --git a/gcc/BASE-VER b/gcc/BASE-VER index 57c4b30bba1..bb6ebd31d52 100644 --- a/gcc/BASE-VER +++ b/gcc/BASE-VER @@ -1 +1 @@ -4.8.4 +4.8.5 diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8bc6fc86a51..1b3ced8e2ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,530 @@ +2015-02-05 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/64580 + Backport from mainline + * config.rs6000/rs6000.c (compute_vrsave_mask): Reverse loop order. + (rs6000_stack_info): Add assert. + (rs6000_output_savres_externs): New function, split off from... + (rs6000_output_function_prologue): ... here. Do not call it for + thunks. + +2015-02-04 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2015-01-31 Uros Bizjak <ubizjak@gmail.com> + + PR target/64882 + * config/i386/predicates.md (address_no_seg_operand): Reject + non-CONST_INT_P operands in invalid mode. + + Backport from mainline + 2015-01-31 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/predicates.md (lea_address_operand): Call + address_operand with VOIDmode. + (vsib_address_operand): Ditto. + +2015-02-01 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2015-01-27 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/61058 + * jump.c (cleanup_barriers): Update basic block boundaries + if BLOCK_FOR_INSN is non-NULL on PREV. + + 2013-04-16 Steven Bosscher <steven@gcc.gnu.org> + + PR middle-end/43631 + * jump.c (cleanup_barriers): Use reorder_insns_nobb to avoid making + the moved barrier the tail of the basic block it follows. + + 2015-01-26 Jakub Jelinek <jakub@redhat.com> + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add + OPTION_MASK_QUAD_MEMORY_ATOMIC. + + 2015-01-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/64563 + * tree-vrp.c (vrp_evaluate_conditional): Check for VR_RANGE + instead of != VR_VARYING. + + PR target/64513 + * config/i386/i386.c (ix86_expand_prologue): Add + REG_FRAME_RELATED_EXPR to %rax and %r10 pushes. + +2015-01-29 Ilya Tocar <ilya.tocar@intel.com> + + * config/i386/avx2intrin.h (_mm256_bslli_epi128, + _mm256_bsrli_epi128): New. + * config/i386/emmintrin.h (_mm_bsrli_si128, _mm_bslli_si128): Ditto. + +2015-01-27 Mikael Pettersson <mikpelinux@gmail.com> + + Backport from mainline + + 2013-09-20 Bernd Edlinger <bernd.edlinger@hotmail.de> + + PR middle-end/57748 + * expr.c (expand_assignment): Remove misalignp code path. + + 2014-01-08 Bernd Edlinger <bernd.edlinger@hotmail.de> + + PR middle-end/57748 + * expr.h (expand_expr_real, expand_expr_real_1): Add new parameter + inner_reference_p. + (expand_expr, expand_normal): Adjust. + * expr.c (expand_expr_real, expand_expr_real_1): Add new parameter + inner_reference_p. Use inner_reference_p to expand inner references. + (store_expr): Adjust. + * cfgexpand.c (expand_call_stmt): Adjust. + +2015-01-26 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2015-01-26 Uros Bizjak <ubizjak@gmail.com> + + PR target/64795 + * config/i386/i386.md (*movdi_internal): Also check operand 0 + to determine TYPE_LEA operand. + (*movsi_internal): Ditto. + + Backport from mainline + 2015-01-23 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/sse.md (sse2_loadld): Set attribute isa to sse2 for + alternative 1. + +2015-01-15 Martin Liska <mliska@suse.cz> + + Backport from mainline + 2014-11-27 Richard Biener <rguenther@suse.de> + + PR middle-end/63704 + * alias.c (mems_in_disjoint_alias_sets_p): Remove assert + and instead return false when !fstrict-aliasing. + +2015-01-14 Renlin Li <renlin.li@arm.com> + + Backport form mainline + 2014-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + PR target/61413 + * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Fix definition + of __ARM_SIZEOF_WCHAR_T. + +2015-01-13 Pat Haugen <pthaugen@us.ibm.com> + + Backport from mainline + 2014-12-20 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/64358 + * config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the + input operands if only the second is inverted. + * config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128): + Swap BOOL_REGS_OP1 and BOOL_REGS_OP2. Correct arguments to + rs6000_split_logical. + (*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2]. + +2015-01-13 Oleg Endo <olegendo@gcc.gnu.org> + + Backport form mainline + 2015-01-13 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/64479 + * rtlanal.c (set_reg_p): Handle SEQUENCE constructs. + +2014-12-27 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline: + 2014-12-27 H.J. Lu <hongjiu.lu@intel.com> + + PR target/64409 + * config/i386/i386.c (ix86_function_type_abi): Issue an error + when ms_abi attribute is used with x32. + +2014-12-19 H.J. Lu <hongjiu.lu@intel.com> + + Backported from mainline + 2014-12-14 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-19 Jakub Jelinek <jakub@redhat.com> + + * BASE-VER: Set to 4.8.5. + * DEV-PHASE: Set to prerelease. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-12-18 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + Backport from trunk. + PR fortran/61407 + * config/darwin-c.c (version_as_macro): Added extra 0 for OS X 10.10 + and above. + * config/darwin-driver.c (darwin_find_version_from_kernel): Removed + kernel version check to avoid incrementing it after every major OS X + release. + (darwin_default_min_version): Avoid static memory buffer. + +2014-12-15 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/64265 + * tsan.c (instrument_func_entry): Insert __tsan_func_entry + call on edge from entry block to single succ instead + of after labels of single succ of entry block. + +2014-12-13 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-12-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/64269 + * tree-ssa-forwprop.c (simplify_builtin_call): Bail out if + len2 or diff are too large. + +2014-12-11 Eric Botcazou <ebotcazou@adacore.com> + + * doc/md.texi (Insn Lengths): Fix description of (pc). + +2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2014-09-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE): New + built-in definition. + (XVCVUXDDP_SCALE): Likewise. + (XVCVDPSXDS_SCALE): Likewise. + (XVCVDPUXDS_SCALE): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + entries for VSX_BUILTIN_XVCVSXDDP_SCALE, + VSX_BUILTIN_XVCVUXDDP_SCALE, VSX_BUILTIN_XVCVDPSXDS_SCALE, and + VSX_BUILTIN_XVCVDPUXDS_SCALE. + * config/rs6000/rs6000-protos.h (rs6000_scale_v2df): New + prototype. + * config/rs6000/rs6000.c (real.h): New include. + (rs6000_scale_v2df): New function. + * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSXDDP): New unspec. + (UNSPEC_VSX_XVCVUXDDP): Likewise. + (UNSPEC_VSX_XVCVDPSXDS): Likewise. + (UNSPEC_VSX_XVCVDPUXDS): Likewise. + (vsx_xvcvsxddp_scale): New define_expand. + (vsx_xvcvsxddp): New define_insn. + (vsx_xvcvuxddp_scale): New define_expand. + (vsx_xvcvuxddp): New define_insn. + (vsx_xvcvdpsxds_scale): New define_expand. + (vsx_xvcvdpsxds): New define_insn. + (vsx_xvcvdpuxds_scale): New define_expand. + (vsx_xvcvdpuxds): New define_insn. + * doc/extend.texi (vec_ctf): Add new prototypes. + (vec_cts): Likewise. + (vec_ctu): Likewise. + (vec_splat): Likewise. + (vec_div): Likewise. + (vec_mul): Likewise. + + Backport from mainline + 2014-08-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/altivec.h (vec_xl): New #define. + (vec_xst): Likewise. + * config/rs6000/rs6000-builtin.def (XXSPLTD_V2DF): New built-in. + (XXSPLTD_V2DI): Likewise. + (DIV_V2DI): Likewise. + (UDIV_V2DI): Likewise. + (MUL_V2DI): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + entries for VSX_BUILTIN_XVRDPI, VSX_BUILTIN_DIV_V2DI, + VSX_BUILTIN_UDIV_V2DI, VSX_BUILTIN_MUL_V2DI, + VSX_BUILTIN_XXSPLTD_V2DF, and VSX_BUILTIN_XXSPLTD_V2DI). + * config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): New unspec. + (UNSPEC_VSX_DIVSD): Likewise. + (UNSPEC_VSX_DIVUD): Likewise. + (UNSPEC_VSX_MULSD): Likewise. + (vsx_mul_v2di): New insn-and-split. + (vsx_div_v2di): Likewise. + (vsx_udiv_v2di): Likewise. + (vsx_xxspltd_<mode>): New insn. + + Backport from mainline + 2014-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/altivec.h (vec_cpsgn): New #define. + (vec_mergee): Likewise. + (vec_mergeo): Likewise. + (vec_cntlz): Likewise. + * config/rs600/rs6000-c.c (altivec_overloaded_builtins): Add new + entries for VEC_AND, VEC_ANDC, VEC_MERGEH, VEC_MERGEL, VEC_NOR, + VEC_OR, VEC_PACKSU, VEC_XOR, VEC_PERM, VEC_SEL, VEC_VCMPGT_P, + VMRGEW, and VMRGOW. + * doc/extend.texi: Document various forms of vec_cpsgn, + vec_splats, vec_and, vec_andc, vec_mergeh, vec_mergel, vec_nor, + vec_or, vec_perm, vec_sel, vec_sub, vec_xor, vec_all_eq, + vec_all_ge, vec_all_gt, vec_all_le, vec_all_lt, vec_all_ne, + vec_any_eq, vec_any_ge, vec_any_gt, vec_any_le, vec_any_lt, + vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz. + + Backport from mainline + 2014-07-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/altivec.md (unspec enum): Fix typo in UNSPEC_VSLDOI. + (altivec_vsldoi_<mode>): Likewise. + +2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline: + 2014-12-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR middle-end/64225 + * tree-ssa-reassoc.c (acceptable_pow_call): Disable transformation + for BUILT_IN_POW when flag_errno_math is present. + +2014-12-10 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-12-10 Marek Polacek <polacek@redhat.com> + + PR tree-optimization/61686 + * tree-ssa-reassoc.c (range_entry_cmp): Use q->high instead of + p->high. + +2014-12-09 David Edelsohn <dje.gcc@gmail.com> + + Backport from mainline + 2014-12-05 David Edelsohn <dje.gcc@gmail.com> + + * config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_LOCAL): Append + alignment to section name. Increase default alignment to + word. + +2014-12-09 Uros Bizjak <ubizjak@gmail.com> + + PR bootstrap/64213 + Revert: + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-08 Richard Biener <rguenther@suse.de> + + Backport from 4.9 branch + * configure.ac + (ac_has_isl_schedule_constraints_compute_schedule): + New check. + * graphite-clast-to-gimple.c: For ISL 0.14, include deprecate headers. + * graphite-interchange.c: Ditto. + * graphite-poly.c: Ditto. + * graphite-sese-to-poly.c: Ditto. + * graphite-optimize-isl.c (getScheduleForBandList): Ditto. + Conditionally use ISL 0.13+ functions. + * config.in: Regenerate. + * configure: Regenerate. + +2014-12-07 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-12-07 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/50751 + * config/sh/sh.md (extendqihi2): Allow only for TARGET_SH1. + +2014-12-05 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-04 Shanyao Chen <chenshanyao@huawei.com> + + Backport from mainline + 2014-11-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + PR target/59593 + * config/arm/arm.md (*movhi_insn): Use right formatting + for immediate. + + 2014-11-19 Felix Yang <felix.yang@huawei.com> + Shanyao Chen <chenshanyao@huawei.com> + + PR target/59593 + * config/arm/arm.md (define_attr "arch"): Add v6t2. + (define_attr "arch_enabled"): Add test for the above. + (*movhi_insn_arch4): Add new alternative. + +2014-12-04 Jakub Jelinek <jakub@redhat.com> + + PR c++/56493 + * convert.c (convert_to_real, convert_to_expr, convert_to_complex): + Handle COMPOUND_EXPR. + +2014-12-02 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + PR target/64115 + * config/rs6000/rs6000.c (rs6000_delegitimize_address): Remove + invalid UNSPEC_TOCREL sanity check under ENABLE_CHECKING. + +2014-12-01 Richard Biener <rguenther@suse.de> + + PR middle-end/64111 + * tree.c (int_cst_hash_hash): Use TYPE_UID instead of + htab_hash_pointer to not break PCH. + +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-27 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/64067 + * expr.c (expand_expr_addr_expr_1) <case COMPOUND_LITERAL_EXPR>: + Handle it by returning address of COMPOUND_LITERAL_EXPR_DECL + not only if modifier is EXPAND_INITIALIZER, but whenever + COMPOUND_LITERAL_EXPR_DECL is non-NULL and TREE_STATIC. + + 2014-10-31 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/63659 + * ree.c (update_reg_equal_equiv_notes): New function. + (combine_set_extension, transform_ifelse): Use it. + + 2014-10-03 Jakub Jelinek <jakub@redhat.com> + + PR libgomp/61200 + * omp-low.c (taskreg_contexts): New variable. + (scan_omp_parallel): Push newly created context into taskreg_contexts + vector and move record layout code to finish_taskreg_scan. + (scan_omp_task): Likewise. + (finish_taskreg_scan): New function. + (execute_lower_omp): Call finish_taskreg_scan on all taskreg_contexts + vector elements and release it. + +2014-11-26 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-10-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61969 + * tree-nrv.c (pass_nrv::execute): Properly test for automatic + variables. + + 2014-08-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62031 + * tree-data-ref.c (dr_analyze_indices): Do not set + DR_UNCONSTRAINED_BASE. + (dr_may_alias_p): All indirect accesses have to go the + formerly DR_UNCONSTRAINED_BASE path. + * tree-data-ref.h (struct indices): Remove + unconstrained_base member. + (DR_UNCONSTRAINED_BASE): Remove. + + 2014-10-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63379 + * tree-vect-slp.c (vect_get_constant_vectors): Do not compute + a neutral operand for min/max when it is not a reduction chain. + + 2014-11-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63605 + * fold-const.c (fold_binary_loc): Properly use element_precision + for types that may not be scalar. + + 2014-10-28 Richard Biener <rguenther@suse.de> + + PR middle-end/63665 + * fold-const.c (fold_comparison): Properly guard simplifying + against INT_MAX/INT_MIN with !TYPE_OVERFLOW_WRAPS. + +2014-11-22 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-11-20 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/60111 + * config/sh/sh.c: Use signed char for signed field. + +2014-11-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/63673 + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Allow + the base pointer of vec_vsx_ld and vec_vsx_st to take a pointer to + double. + +2014-11-19 Uros Bizjak <ubizjak@gmail.com> + + PR target/63947 + * config/i386/i386.c (put_condition_code) <case LTU, case GEU>: + Output "b" and "nb" suffix for FP mode. + +2014-11-19 Tom de Vries <tom@codesourcery.com> + + Backport from mainline + PR tree-optimization/62167 + * tree-ssa-tail-merge.c (stmt_local_def): Handle statements with vuse + conservatively. + (gimple_equal_p): Don't use vn_valueize to compare for lhs equality of + assigns. + +2014-11-18 Teresa Johnson <tejohnson@google.com> + + Backport from mainline and gcc-4_9 branch. + 2014-11-13 Teresa Johnson <tejohnson@google.com> + + PR tree-optimization/63841 + * tree-ssa-strlen.c (strlen_optimize_stmt): Ignore clobbers. + +2014-11-16 Eric Botcazou <ebotcazou@adacore.com> + + * doc/tm.texi.in (TARGET_FLAGS_REGNUM): Move around. + * doc/tm.texi: Regenerate. + + Backport from mainline + 2013-09-16 Andreas Schwab <schwab@linux-m68k.org> + + * doc/tm.texi.in (Cond Exec Macros): Remove node. + (Condition Code): Don't reference it. + * doc/tm.texi: Regenerate. + +2014-11-13 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from mainline + 2014-11-02 Michael Collison <michael.collison@linaro.org> + + * config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update + to support vector modes. + (CTZ_DEFINED_VALUE_AT_ZERO): Ditto. + +2014-11-13 Eric Botcazou <ebotcazou@adacore.com> + + * doc/tm.texi.in (SELECT_CC_MODE): Update example. + (REVERSIBLE_CC_MODE): Fix example. + (REVERSE_CONDITION): Fix typo. + * doc/tm.texi: Regenerate. + +2014-11-12 Jakub Jelinek <jakub@redhat.com> + + PR ipa/63838 + * ipa-pure-const.c (propagate_nothrow): Walk w->indirect_calls + chain instead of node->indirect_calls. + +2014-11-10 Daniel Hellstrom <daniel@gaisler.com> + + Backport from mainline + * config.gcc (sparc-*-rtems*): Clean away unused t-elf. + * config/sparc/t-rtems: Add leon3v7 and muser-mode multilibs. + 2014-11-07 Daniel Hellstrom <daniel@gaisler.com> * config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor. @@ -15,7 +542,7 @@ * config/pa/pa.md (trap): New insn. Add "trap" to attribute type. Don't allow trap insn in in_branch_delay, in_nullified_branch_delay or in_call_delay. - + 2014-11-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64-elf-raw.h (CA53_ERR_835769_SPEC): Define. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f638984061a..badd154f9f4 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20141110 +20150209 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 2f39ad5dbe1..0050ae5f636 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,16 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-11-22 Eric Botcazou <ebotcazou@adacore.com> + + Backport from mainline + 2014-11-20 Vincent Celier <celier@adacore.com> + + PR ada/47500 + * back_end.adb (Scan_Back_End_Switches): Skip switch -G and + its argument. + 2014-10-13 Eric Botcazou <ebotcazou@adacore.com> Alan Modra <amodra@gmail.com> diff --git a/gcc/ada/back_end.adb b/gcc/ada/back_end.adb index f23230ecf9d..4313ca4500c 100644 --- a/gcc/ada/back_end.adb +++ b/gcc/ada/back_end.adb @@ -209,9 +209,10 @@ package body Back_End is Last : constant Natural := Switch_Last (Switch_Chars); begin - -- Skip -o or internal GCC switches together with their argument + -- Skip -o, -G or internal GCC switches together with their argument. if Switch_Chars (First .. Last) = "o" + or else Switch_Chars (First .. Last) = "G" or else Is_Internal_GCC_Switch (Switch_Chars) then Next_Arg := Next_Arg + 1; diff --git a/gcc/alias.c b/gcc/alias.c index 381222c3487..5240982795c 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -380,17 +380,9 @@ get_alias_set_entry (alias_set_type alias_set) static inline int mems_in_disjoint_alias_sets_p (const_rtx mem1, const_rtx mem2) { -/* Perform a basic sanity check. Namely, that there are no alias sets - if we're not using strict aliasing. This helps to catch bugs - whereby someone uses PUT_CODE, but doesn't clear MEM_ALIAS_SET, or - where a MEM is allocated in some way other than by the use of - gen_rtx_MEM, and the MEM_ALIAS_SET is not cleared. If we begin to - use alias sets to indicate that spilled registers cannot alias each - other, we might need to remove this check. */ - gcc_assert (flag_strict_aliasing - || (!MEM_ALIAS_SET (mem1) && !MEM_ALIAS_SET (mem2))); - - return ! alias_sets_conflict_p (MEM_ALIAS_SET (mem1), MEM_ALIAS_SET (mem2)); + return (flag_strict_aliasing + && ! alias_sets_conflict_p (MEM_ALIAS_SET (mem1), + MEM_ALIAS_SET (mem2))); } /* Insert the NODE into the splay tree given by DATA. Used by diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 8100afca2d6..b230bc4a303 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,16 @@ +2015-01-20 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-06-23 Marek Polacek <polacek@redhat.com> + + PR c/61553 + * c-common.c (get_atomic_generic_size): Don't segfault if the + type doesn't have a size. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index 86f64ec60e8..f41ec9ca889 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -10143,7 +10143,8 @@ get_atomic_generic_size (location_t loc, tree function, function); return 0; } - size = tree_low_cst (TYPE_SIZE_UNIT (TREE_TYPE (type)), 1); + tree type_size = TYPE_SIZE_UNIT (TREE_TYPE (type)); + size = type_size ? tree_low_cst (type_size, 1) : 0; if (size != size_0) { error_at (loc, "size mismatch in argument %d of %qE", x + 1, diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 22d0e032a04..04b33a3cf16 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,16 @@ +2015-02-01 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2015-01-27 Jakub Jelinek <jakub@redhat.com> + + PR c/64766 + * c-typeck.c (store_init_value): Don't overwrite DECL_INITIAL + of FUNCTION_DECLs with error_mark_node. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index e47c2e5a453..a608fb6ddc6 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -5788,7 +5788,8 @@ store_init_value (location_t init_loc, tree decl, tree init, tree origtype) warning (OPT_Wtraditional, "traditional C rejects automatic " "aggregate initialization"); - DECL_INITIAL (decl) = value; + if (value != error_mark_node || TREE_CODE (decl) != FUNCTION_DECL) + DECL_INITIAL (decl) = value; /* ANSI wants warnings about out-of-range constant initializers. */ STRIP_TYPE_NOPS (value); diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index 1321c214d92..3edfeeea3d0 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -2111,7 +2111,7 @@ expand_call_stmt (gimple stmt) if (lhs) expand_assignment (lhs, exp, false); else - expand_expr_real_1 (exp, const0_rtx, VOIDmode, EXPAND_NORMAL, NULL); + expand_expr (exp, const0_rtx, VOIDmode, EXPAND_NORMAL); mark_transaction_restart_calls (stmt); } diff --git a/gcc/combine.c b/gcc/combine.c index a0e881fb2d6..94a9a06b1cb 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -1527,8 +1527,8 @@ setup_incoming_promotions (rtx first) uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); /* The mode and signedness of the argument as it is actually passed, - after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */ - mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3, + see assign_parm_setup_reg in function.c. */ + mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3, TREE_TYPE (cfun->decl), 0); /* The mode of the register in which the argument is being passed. */ diff --git a/gcc/config.gcc b/gcc/config.gcc index 3039cf04e94..7b698ca9be6 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2463,7 +2463,7 @@ sparc-*-elf*) ;; sparc-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h" - tmake_file="sparc/t-sparc sparc/t-elf sparc/t-rtems t-rtems" + tmake_file="sparc/t-sparc sparc/t-rtems t-rtems" ;; sparc-*-linux*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h" diff --git a/gcc/config.in b/gcc/config.in index 27497d4194b..8e8976265c4 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -1175,6 +1175,12 @@ #endif +/* Define if isl_schedule_constraints_compute_schedule exists. */ +#ifndef USED_FOR_TARGET +#undef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#endif + + /* Define to 1 if you have the `kill' function. */ #ifndef USED_FOR_TARGET #undef HAVE_KILL diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8927b4e2a9c..88a99a9461f 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -69,8 +69,8 @@ extern char arm_arch_name[]; builtin_define_with_int_value ( \ "__ARM_SIZEOF_MINIMAL_ENUM", \ flag_short_enums ? 1 : 4); \ - builtin_define_with_int_value ( \ - "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \ + builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ + wchar_type_node); \ if (TARGET_ARM_ARCH_PROFILE) \ builtin_define_with_int_value ( \ "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ @@ -2113,9 +2113,10 @@ extern int making_const_table; ? reverse_condition_maybe_unordered (code) \ : reverse_condition (code)) -/* The arm5 clz instruction returns 32. */ -#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) -#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) #define CC_STATUS_INIT \ do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index aff783833a0..8fbd4a9c44b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -104,8 +104,10 @@ ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6" ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without ; arm_arch6. This attribute is used to compute attribute "enabled", -; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" +; arm_arch6. "v6t2" for Thumb-2 with arm_arch6. This attribute is +; used to compute attribute "enabled", use type "any" to enable an +; alternative in all cases. +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" (const_string "any")) (define_attr "arch_enabled" "no,yes" @@ -145,6 +147,10 @@ (not (match_test "TARGET_PREFER_NEON_64BITS"))) (const_string "yes") + (and (eq_attr "arch" "v6t2") + (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2")) + (const_string "yes") + (and (eq_attr "arch" "neon_for_64bits") (match_test "TARGET_NEON") (match_test "TARGET_PREFER_NEON_64BITS")) @@ -6874,8 +6880,8 @@ ;; Pattern to recognize insn generated default case above (define_insn "*movhi_insn_arch4" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") - (match_operand:HI 1 "general_operand" "rI,K,r,mi"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r") + (match_operand:HI 1 "general_operand" "rI,K,n,r,mi"))] "TARGET_ARM && arm_arch4 && (register_operand (operands[0], HImode) @@ -6883,16 +6889,19 @@ "@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi + movw%?\\t%0, %L1\\t%@ movhi str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,*,256") - (set_attr "neg_pool_range" "*,*,*,244") + (set_attr "pool_range" "*,*,*,*,256") + (set_attr "neg_pool_range" "*,*,*,*,244") + (set_attr "arch" "*,*,v6t2,*,*") (set_attr_alternative "type" [(if_then_else (match_operand 1 "const_int_operand" "") (const_string "mov_imm" ) (const_string "mov_reg")) (const_string "mvn_imm") + (const_string "mov_imm") (const_string "store1") (const_string "load1")])] ) diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c index ed547b27468..88ba752656e 100644 --- a/gcc/config/darwin-c.c +++ b/gcc/config/darwin-c.c @@ -571,21 +571,34 @@ find_subframework_header (cpp_reader *pfile, const char *header, cpp_dir **dirp) } /* Return the value of darwin_macosx_version_min suitable for the - __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ macro, - so '10.4.2' becomes 1040. The lowest digit is always zero. + __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ macro, so '10.4.2' + becomes 1040 and '10.10.0' becomes 101000. The lowest digit is + always zero, as is the second lowest for '10.10.x' and above. Print a warning if the version number can't be understood. */ static const char * version_as_macro (void) { - static char result[] = "1000"; + static char result[7] = "1000"; + int minorDigitIdx; if (strncmp (darwin_macosx_version_min, "10.", 3) != 0) goto fail; if (! ISDIGIT (darwin_macosx_version_min[3])) goto fail; - result[2] = darwin_macosx_version_min[3]; - if (darwin_macosx_version_min[4] != '\0' - && darwin_macosx_version_min[4] != '.') + + minorDigitIdx = 3; + result[2] = darwin_macosx_version_min[minorDigitIdx++]; + if (ISDIGIT (darwin_macosx_version_min[minorDigitIdx])) + { + /* Starting with OS X 10.10, the macro ends '00' rather than '0', + i.e. 10.10.x becomes 101000 rather than 10100. */ + result[3] = darwin_macosx_version_min[minorDigitIdx++]; + result[4] = '0'; + result[5] = '0'; + result[6] = '\0'; + } + if (darwin_macosx_version_min[minorDigitIdx] != '\0' + && darwin_macosx_version_min[minorDigitIdx] != '.') goto fail; return result; diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c index 41076002308..33fccb6746f 100644 --- a/gcc/config/darwin-driver.c +++ b/gcc/config/darwin-driver.c @@ -29,8 +29,8 @@ along with GCC; see the file COPYING3. If not see #include <sys/sysctl.h> #include "xregex.h" -static bool -darwin_find_version_from_kernel (char *new_flag) +static char * +darwin_find_version_from_kernel (void) { char osversion[32]; size_t osversion_len = sizeof (osversion) - 1; @@ -39,6 +39,7 @@ darwin_find_version_from_kernel (char *new_flag) char minor_vers[6]; char * version_p; char * version_pend; + char * new_flag; /* Determine the version of the running OS. If we can't, warn user, and do nothing. */ @@ -46,7 +47,7 @@ darwin_find_version_from_kernel (char *new_flag) &osversion_len, NULL, 0) == -1) { warning (0, "sysctl for kern.osversion failed: %m"); - return false; + return NULL; } /* Try to parse the first two parts of the OS version number. Warn @@ -57,8 +58,6 @@ darwin_find_version_from_kernel (char *new_flag) version_p = osversion + 1; if (ISDIGIT (*version_p)) major_vers = major_vers * 10 + (*version_p++ - '0'); - if (major_vers > 4 + 9) - goto parse_failed; if (*version_p++ != '.') goto parse_failed; version_pend = strchr(version_p, '.'); @@ -74,17 +73,16 @@ darwin_find_version_from_kernel (char *new_flag) if (major_vers - 4 <= 4) /* On 10.4 and earlier, the old linker is used which does not support three-component system versions. */ - sprintf (new_flag, "10.%d", major_vers - 4); + asprintf (&new_flag, "10.%d", major_vers - 4); else - sprintf (new_flag, "10.%d.%s", major_vers - 4, - minor_vers); + asprintf (&new_flag, "10.%d.%s", major_vers - 4, minor_vers); - return true; + return new_flag; parse_failed: warning (0, "couldn%'t understand kern.osversion %q.*s", (int) osversion_len, osversion); - return false; + return NULL; } #endif @@ -105,7 +103,7 @@ darwin_default_min_version (unsigned int *decoded_options_count, const unsigned int argc = *decoded_options_count; struct cl_decoded_option *const argv = *decoded_options; unsigned int i; - static char new_flag[sizeof ("10.0.0") + 6]; + const char *new_flag; /* If the command-line is empty, just return. */ if (argc <= 1) @@ -142,16 +140,16 @@ darwin_default_min_version (unsigned int *decoded_options_count, #ifndef CROSS_DIRECTORY_STRUCTURE - /* Try to find the version from the kernel, if we fail - we print a message - and give up. */ - if (!darwin_find_version_from_kernel (new_flag)) - return; + /* Try to find the version from the kernel, if we fail - we print a message + and give up. */ + new_flag = darwin_find_version_from_kernel (); + if (!new_flag) + return; #else - /* For cross-compilers, default to the target OS version. */ - - strncpy (new_flag, DEF_MIN_OSX_VERSION, sizeof (new_flag)); + /* For cross-compilers, default to the target OS version. */ + new_flag = DEF_MIN_OSX_VERSION; #endif /* CROSS_DIRECTORY_STRUCTURE */ @@ -165,7 +163,6 @@ darwin_default_min_version (unsigned int *decoded_options_count, memcpy (*decoded_options + 2, argv + 1, (argc - 1) * sizeof (struct cl_decoded_option)); return; - } /* Translate -filelist and -framework options in *DECODED_OPTIONS diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h index 1537bf5add0..006c6240785 100644 --- a/gcc/config/i386/avx2intrin.h +++ b/gcc/config/i386/avx2intrin.h @@ -639,11 +639,20 @@ _mm256_sign_epi32 (__m256i __X, __m256i __Y) #ifdef __OPTIMIZE__ extern __inline __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_bslli_epi128 (__m256i __A, const int __N) +{ + return (__m256i)__builtin_ia32_pslldqi256 (__A, __N * 8); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_slli_si256 (__m256i __A, const int __N) { return (__m256i)__builtin_ia32_pslldqi256 (__A, __N * 8); } #else +#define _mm256_bslli_epi128(A, N) \ + ((__m256i)__builtin_ia32_pslldqi256 ((__m256i)(A), (int)(N) * 8)) #define _mm256_slli_si256(A, N) \ ((__m256i)__builtin_ia32_pslldqi256 ((__m256i)(A), (int)(N) * 8)) #endif @@ -721,11 +730,20 @@ _mm256_sra_epi32 (__m256i __A, __m128i __B) #ifdef __OPTIMIZE__ extern __inline __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_bsrli_epi128 (__m256i __A, const int __N) +{ + return (__m256i)__builtin_ia32_psrldqi256 (__A, __N * 8); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_srli_si256 (__m256i __A, const int __N) { return (__m256i)__builtin_ia32_psrldqi256 (__A, __N * 8); } #else +#define _mm256_bsrli_epi128(A, N) \ + ((__m256i)__builtin_ia32_psrldqi256 ((__m256i)(A), (int)(N) * 8)) #define _mm256_srli_si256(A, N) \ ((__m256i)__builtin_ia32_psrldqi256 ((__m256i)(A), (int)(N) * 8)) #endif diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h index cf404a13536..3aa88a7c9a5 100644 --- a/gcc/config/i386/emmintrin.h +++ b/gcc/config/i386/emmintrin.h @@ -1143,6 +1143,18 @@ _mm_srai_epi32 (__m128i __A, int __B) #ifdef __OPTIMIZE__ extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_bsrli_si128 (__m128i __A, const int __N) +{ + return (__m128i)__builtin_ia32_psrldqi128 (__A, __N * 8); +} + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_bslli_si128 (__m128i __A, const int __N) +{ + return (__m128i)__builtin_ia32_pslldqi128 (__A, __N * 8); +} + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_srli_si128 (__m128i __A, const int __N) { return (__m128i)__builtin_ia32_psrldqi128 (__A, __N * 8); @@ -1154,6 +1166,10 @@ _mm_slli_si128 (__m128i __A, const int __N) return (__m128i)__builtin_ia32_pslldqi128 (__A, __N * 8); } #else +#define _mm_bsrli_si128(A, N) \ + ((__m128i)__builtin_ia32_psrldqi128 ((__m128i)(A), (int)(N) * 8)) +#define _mm_bslli_si128(A, N) \ + ((__m128i)__builtin_ia32_pslldqi128 ((__m128i)(A), (int)(N) * 8)) #define _mm_srli_si128(A, N) \ ((__m128i)__builtin_ia32_psrldqi128 ((__m128i)(A), (int)(N) * 8)) #define _mm_slli_si128(A, N) \ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 73f8a44a209..f0dadb7226d 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5539,7 +5539,18 @@ ix86_function_type_abi (const_tree fntype) if (abi == SYSV_ABI) { if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype))) - abi = MS_ABI; + { + if (TARGET_X32) + { + static bool warned = false; + if (!warned) + { + error ("X32 does not support ms_abi attribute"); + warned = true; + } + } + abi = MS_ABI; + } } else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype))) abi = SYSV_ABI; @@ -10483,6 +10494,10 @@ ix86_expand_prologue (void) if (sp_is_cfa_reg) m->fs.cfa_offset += UNITS_PER_WORD; RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_rtx_SET (VOIDmode, stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, + -UNITS_PER_WORD))); } } @@ -10496,6 +10511,10 @@ ix86_expand_prologue (void) if (sp_is_cfa_reg) m->fs.cfa_offset += UNITS_PER_WORD; RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_rtx_SET (VOIDmode, stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, + -UNITS_PER_WORD))); } } @@ -13800,7 +13819,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, if (mode == CCmode) suffix = "b"; else if (mode == CCCmode) - suffix = "c"; + suffix = fp ? "b" : "c"; else gcc_unreachable (); break; @@ -13823,9 +13842,9 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, break; case GEU: if (mode == CCmode) - suffix = fp ? "nb" : "ae"; + suffix = "nb"; else if (mode == CCCmode) - suffix = "nc"; + suffix = fp ? "nb" : "nc"; else gcc_unreachable (); break; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 24e93f9f41a..372ae63f03d 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1945,7 +1945,8 @@ (const_string "ssemov") (eq_attr "alternative" "15,16") (const_string "ssecvt") - (match_operand 1 "pic_32bit_operand") + (and (match_operand 0 "register_operand") + (match_operand 1 "pic_32bit_operand")) (const_string "lea") ] (const_string "imov"))) @@ -2171,7 +2172,8 @@ (const_string "sselog1") (eq_attr "alternative" "7,8,9,10,11") (const_string "ssemov") - (match_operand 1 "pic_32bit_operand") + (and (match_operand 0 "register_operand") + (match_operand 1 "pic_32bit_operand")) (const_string "lea") ] (const_string "imov"))) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 0e52c85184e..61614e11246 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -806,11 +806,16 @@ ;; a segment override. Defined as a special predicate to allow ;; mode-less const_int operands pass to address_operand. (define_special_predicate "lea_address_operand" - (match_operand 0 "address_operand") + (match_test "address_operand (op, VOIDmode)") { struct ix86_address parts; int ok; + if (!CONST_INT_P (op) + && mode != VOIDmode + && GET_MODE (op) != mode) + return false; + ok = ix86_decompose_address (op, &parts); gcc_assert (ok); return parts.seg == SEG_DEFAULT; @@ -823,7 +828,7 @@ ;; Return true if op if a valid base register, displacement or ;; sum of base register and displacement for VSIB addressing. (define_predicate "vsib_address_operand" - (match_operand 0 "address_operand") + (match_test "address_operand (op, VOIDmode)") { struct ix86_address parts; int ok; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index cba540107c5..bc47bb4067a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7369,7 +7369,7 @@ movss\t{%2, %0|%0, %2} movss\t{%2, %0|%0, %2} vmovss\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "sse2,*,noavx,noavx,avx") + [(set_attr "isa" "sse2,sse2,noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex") (set_attr "mode" "TI,TI,V4SF,SF,SF")]) diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index f101751f6ab..ad485d6eb78 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -124,6 +124,7 @@ #define vec_vcfux __builtin_vec_vcfux #define vec_cts __builtin_vec_cts #define vec_ctu __builtin_vec_ctu +#define vec_cpsgn __builtin_vec_copysign #define vec_expte __builtin_vec_expte #define vec_floor __builtin_vec_floor #define vec_loge __builtin_vec_loge @@ -214,8 +215,10 @@ #define vec_lvsl __builtin_vec_lvsl #define vec_lvsr __builtin_vec_lvsr #define vec_max __builtin_vec_max +#define vec_mergee __builtin_vec_vmrgew #define vec_mergeh __builtin_vec_mergeh #define vec_mergel __builtin_vec_mergel +#define vec_mergeo __builtin_vec_vmrgow #define vec_min __builtin_vec_min #define vec_mladd __builtin_vec_mladd #define vec_msum __builtin_vec_msum @@ -319,6 +322,8 @@ #define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st +#define vec_xl __builtin_vec_vsx_ld +#define vec_xst __builtin_vec_vsx_st /* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions instead of __builtin_vec_<xxx> */ @@ -336,6 +341,7 @@ #define vec_vadduqm __builtin_vec_vadduqm #define vec_vbpermq __builtin_vec_vbpermq #define vec_vclz __builtin_vec_vclz +#define vec_cntlz __builtin_vec_vclz #define vec_vclzb __builtin_vec_vclzb #define vec_vclzd __builtin_vec_vclzd #define vec_vclzh __builtin_vec_vclzh diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 47a4610b78a..697057f73f1 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -67,7 +67,7 @@ UNSPEC_VCTSXS UNSPEC_VLOGEFP UNSPEC_VEXPTEFP - UNSPEC_VLSDOI + UNSPEC_VSLDOI UNSPEC_VUNPACK_HI_SIGN UNSPEC_VUNPACK_LO_SIGN UNSPEC_VUNPACK_HI_SIGN_DIRECT @@ -2077,7 +2077,7 @@ (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") (match_operand:QI 3 "immediate_operand" "i")] - UNSPEC_VLSDOI))] + UNSPEC_VSLDOI))] "TARGET_ALTIVEC" "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index f7eb2714ff6..3d7ee36a6a2 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1258,6 +1258,16 @@ BU_VSX_2 (VEC_MERGEL_V2DF, "mergel_2df", CONST, vsx_mergel_v2df) BU_VSX_2 (VEC_MERGEL_V2DI, "mergel_2di", CONST, vsx_mergel_v2di) BU_VSX_2 (VEC_MERGEH_V2DF, "mergeh_2df", CONST, vsx_mergeh_v2df) BU_VSX_2 (VEC_MERGEH_V2DI, "mergeh_2di", CONST, vsx_mergeh_v2di) +BU_VSX_2 (XXSPLTD_V2DF, "xxspltd_2df", CONST, vsx_xxspltd_v2df) +BU_VSX_2 (XXSPLTD_V2DI, "xxspltd_2di", CONST, vsx_xxspltd_v2di) +BU_VSX_2 (DIV_V2DI, "div_2di", CONST, vsx_div_v2di) +BU_VSX_2 (UDIV_V2DI, "udiv_2di", CONST, vsx_udiv_v2di) +BU_VSX_2 (MUL_V2DI, "mul_2di", CONST, vsx_mul_v2di) + +BU_VSX_2 (XVCVSXDDP_SCALE, "xvcvsxddp_scale", CONST, vsx_xvcvsxddp_scale) +BU_VSX_2 (XVCVUXDDP_SCALE, "xvcvuxddp_scale", CONST, vsx_xvcvuxddp_scale) +BU_VSX_2 (XVCVDPSXDS_SCALE, "xvcvdpsxds_scale", CONST, vsx_xvcvdpsxds_scale) +BU_VSX_2 (XVCVDPUXDS_SCALE, "xvcvdpuxds_scale", CONST, vsx_xvcvdpuxds_scale) /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 3009f1ea80e..94f799cb3b8 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -595,6 +595,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, @@ -875,6 +877,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -929,6 +943,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -1116,18 +1142,30 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, + RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, @@ -1593,6 +1631,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, @@ -1641,6 +1689,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, @@ -1769,6 +1827,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_XVMULDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, @@ -1810,6 +1872,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, @@ -1840,6 +1914,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -1943,6 +2029,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, @@ -2125,6 +2213,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, @@ -2517,6 +2613,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -2776,6 +2884,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, + { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, @@ -2816,6 +2926,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, @@ -3265,6 +3381,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, @@ -3319,6 +3437,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, @@ -3429,6 +3549,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, @@ -3887,12 +4019,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 089c98d723c..cbb305e1c4a 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -91,6 +91,7 @@ | OPTION_MASK_PPC_GFXOPT \ | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_QUAD_MEMORY \ + | OPTION_MASK_QUAD_MEMORY_ATOMIC \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 5db8b28fec5..d4b93d9970d 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -65,6 +65,7 @@ extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned); extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); +extern void rs6000_scale_v2df (rtx, rtx, int); extern void build_mask64_2_operands (rtx, rtx *); extern int expand_block_clear (rtx[]); extern int expand_block_move (rtx[]); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9589d411136..2f9a1789f57 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -60,6 +60,7 @@ #include "opts.h" #include "tree-vectorizer.h" #include "dumpfile.h" +#include "real.h" #if TARGET_XCOFF #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ #endif @@ -6877,24 +6878,6 @@ rs6000_delegitimize_address (rtx orig_x) if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL) { -#ifdef ENABLE_CHECKING - if (REG_P (XVECEXP (y, 0, 1)) - && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER) - { - /* All good. */ - } - else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR) - { - /* Weirdness alert. df_note_compute can replace r2 with a - debug_expr when this unspec is in a debug_insn. - Seen in gcc.dg/pr51957-1.c */ - } - else - { - debug_rtx (orig_x); - abort (); - } -#endif y = XVECEXP (y, 0, 0); #ifdef HAVE_AS_TLS @@ -20765,7 +20748,7 @@ compute_vrsave_mask (void) them in again. More importantly, the mask we compute here is used to generate CLOBBERs in the set_vrsave insn, and we do not wish the argument registers to die. */ - for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) + for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++) mask &= ~ALTIVEC_REG_BIT (i); /* Similarly, remove the return value from the set. */ @@ -21175,6 +21158,9 @@ rs6000_savres_strategy (rs6000_stack_t *info, static rs6000_stack_t * rs6000_stack_info (void) { + /* We should never be called for thunks, we are not set up for that. */ + gcc_assert (!cfun->is_thunk); + rs6000_stack_t *info_ptr = &stack_info; int reg_size = TARGET_32BIT ? 4 : 8; int ehrd_size; @@ -23903,11 +23889,10 @@ rs6000_emit_prologue (void) } } -/* Write function prologue. */ +/* Output .extern statements for the save/restore routines we use. */ static void -rs6000_output_function_prologue (FILE *file, - HOST_WIDE_INT size ATTRIBUTE_UNUSED) +rs6000_output_savres_externs (FILE *file) { rs6000_stack_t *info = rs6000_stack_info (); @@ -23939,6 +23924,16 @@ rs6000_output_function_prologue (FILE *file, fprintf (file, "\t.extern %s\n", name); } } +} + +/* Write function prologue. */ + +static void +rs6000_output_function_prologue (FILE *file, + HOST_WIDE_INT size ATTRIBUTE_UNUSED) +{ + if (!cfun->is_thunk) + rs6000_output_savres_externs (file); /* ELFv2 ABI r2 setup code and local entry point. This must follow immediately after the global entry point label. */ @@ -31033,6 +31028,23 @@ rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp) rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); } +/* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */ +void +rs6000_scale_v2df (rtx tgt, rtx src, int scale) +{ + HOST_WIDE_INT hwi_scale (scale); + REAL_VALUE_TYPE r_pow; + rtvec v = rtvec_alloc (2); + rtx elt; + rtx scale_vec = gen_reg_rtx (V2DFmode); + (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale); + elt = CONST_DOUBLE_FROM_REAL_VALUE (r_pow, DFmode); + RTVEC_ELT (v, 0) = elt; + RTVEC_ELT (v, 1) = elt; + rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v)); + emit_insn (gen_mulv2df3 (tgt, src, scale_vec)); +} + /* Return an RTX representing where to find the function value of a function returning MODE. */ static rtx @@ -32628,6 +32640,14 @@ rs6000_split_logical_inner (rtx dest, if (complement_op2_p) op2 = gen_rtx_NOT (mode, op2); + /* For canonical RTL, if only one arm is inverted it is the first. */ + if (!complement_op1_p && complement_op2_p) + { + rtx temp = op1; + op1 = op2; + op2 = temp; + } + bool_rtx = ((code == NOT) ? gen_rtx_NOT (mode, op1) : gen_rtx_fmt_ee (code, mode, op1, op2)); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d31ae4c377f..e8a09601b59 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8622,8 +8622,8 @@ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") (match_operator:BOOL_128 3 "boolean_operator" [(not:BOOL_128 - (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>")) - (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))] + (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")) + (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))] "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)" { if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) @@ -8638,7 +8638,7 @@ && reload_completed && int_reg_operand (operands[0], <MODE>mode)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false, + rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true, NULL_RTX); DONE; } @@ -8660,14 +8660,14 @@ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") (match_operator:TI2 3 "boolean_operator" [(not:TI2 - (match_operand:TI2 1 "int_reg_operand" "r,0,r")) - (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))] + (match_operand:TI2 2 "int_reg_operand" "r,0,r")) + (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))] "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" "#" "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false, + rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true, NULL_RTX); DONE; } diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 432dfe14f43..8f171946d86 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -260,6 +260,14 @@ UNSPEC_VSX_ROUND_IC UNSPEC_VSX_SLDWI UNSPEC_VSX_XXSPLTW + UNSPEC_VSX_XXSPLTD + UNSPEC_VSX_DIVSD + UNSPEC_VSX_DIVUD + UNSPEC_VSX_MULSD + UNSPEC_VSX_XVCVSXDDP + UNSPEC_VSX_XVCVUXDDP + UNSPEC_VSX_XVCVDPSXDS + UNSPEC_VSX_XVCVDPUXDS ]) ;; VSX moves @@ -746,6 +754,34 @@ [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_mul>")]) +; Emulate vector with scalar for vec_mul in V2DImode +(define_insn_and_split "vsx_mul_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa")] + UNSPEC_VSX_MULSD))] + "VECTOR_MEM_VSX_P (V2DImode)" + "#" + "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress" + [(const_int 0)] + " +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + emit_insn (gen_muldi3 (op5, op3, op4)); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + emit_insn (gen_muldi3 (op3, op3, op4)); + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); +}" + [(set_attr "type" "vecdouble")]) + (define_insn "*vsx_div<mode>3" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") @@ -755,6 +791,61 @@ [(set_attr "type" "<VStype_div>") (set_attr "fp_type" "<VSfptype_div>")]) +; Emulate vector with scalar for vec_div in V2DImode +(define_insn_and_split "vsx_div_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa")] + UNSPEC_VSX_DIVSD))] + "VECTOR_MEM_VSX_P (V2DImode)" + "#" + "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress" + [(const_int 0)] + " +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + emit_insn (gen_divdi3 (op5, op3, op4)); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + emit_insn (gen_divdi3 (op3, op3, op4)); + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); +}" + [(set_attr "type" "vecdiv")]) + +(define_insn_and_split "vsx_udiv_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa")] + UNSPEC_VSX_DIVUD))] + "VECTOR_MEM_VSX_P (V2DImode)" + "#" + "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress" + [(const_int 0)] + " +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + emit_insn (gen_udivdi3 (op5, op3, op4)); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + emit_insn (gen_udivdi3 (op3, op3, op4)); + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); +}" + [(set_attr "type" "vecdiv")]) + ;; *tdiv* instruction returning the FG flag (define_expand "vsx_tdiv<mode>3_fg" [(set (match_dup 3) @@ -1268,6 +1359,102 @@ "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) +;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long) + +(define_expand "vsx_xvcvsxddp_scale" + [(match_operand:V2DF 0 "vsx_register_operand" "") + (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int scale = INTVAL(operands[2]); + emit_insn (gen_vsx_xvcvsxddp (op0, op1)); + if (scale != 0) + rs6000_scale_v2df (op0, op0, -scale); + DONE; +}) + +(define_insn "vsx_xvcvsxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVSXDDP))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvsxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvuxddp_scale" + [(match_operand:V2DF 0 "vsx_register_operand" "") + (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int scale = INTVAL(operands[2]); + emit_insn (gen_vsx_xvcvuxddp (op0, op1)); + if (scale != 0) + rs6000_scale_v2df (op0, op0, -scale); + DONE; +}) + +(define_insn "vsx_xvcvuxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVUXDDP))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvuxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpsxds_scale" + [(match_operand:V2DI 0 "vsx_register_operand" "") + (match_operand:V2DF 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = gen_reg_rtx (V2DFmode); + int scale = INTVAL(operands[2]); + if (scale != 0) + rs6000_scale_v2df (tmp, op1, scale); + emit_insn (gen_vsx_xvcvdpsxds (op0, tmp)); + DONE; +}) + +(define_insn "vsx_xvcvdpsxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVDPSXDS))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpsxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpuxds_scale" + [(match_operand:V2DI 0 "vsx_register_operand" "") + (match_operand:V2DF 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = gen_reg_rtx (V2DFmode); + int scale = INTVAL(operands[2]); + if (scale != 0) + rs6000_scale_v2df (tmp, op1, scale); + emit_insn (gen_vsx_xvcvdpuxds (op0, tmp)); + DONE; +}) + +(define_insn "vsx_xvcvdpuxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVDPUXDS))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpuxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + ;; Convert from 64-bit to 32-bit types ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. @@ -1844,6 +2031,22 @@ "xxspltw %x0,%x1,%2" [(set_attr "type" "vecperm")]) +;; V2DF/V2DI splat for use by vec_splat builtin +(define_insn "vsx_xxspltd_<mode>" + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") + (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wa") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSX_XXSPLTD))] + "VECTOR_MEM_VSX_P (<MODE>mode)" +{ + if ((VECTOR_ELT_ORDER_BIG && INTVAL (operands[2]) == 0) + || (!VECTOR_ELT_ORDER_BIG && INTVAL (operands[2]) == 1)) + return "xxpermdi %x0,%x1,%x1,0"; + else + return "xxpermdi %x0,%x1,%x1,3"; +} + [(set_attr "type" "vecperm")]) + ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_<mode>" [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h index 512bcb5472e..10123313f99 100644 --- a/gcc/config/rs6000/xcoff.h +++ b/gcc/config/rs6000/xcoff.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for some generic XCOFF file format - Copyright (C) 2001-2013 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. This file is part of GCC. @@ -304,14 +304,15 @@ do { fputs (LOCAL_COMMON_ASM_OP, (FILE)); \ RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ if ((ALIGN) > 32) \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,%u\n", \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s%u_,%u\n", \ (SIZE), xcoff_bss_section_name, \ + floor_log2 ((ALIGN) / BITS_PER_UNIT), \ floor_log2 ((ALIGN) / BITS_PER_UNIT)); \ else if ((SIZE) > 4) \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,3\n", \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s3_,3\n", \ (SIZE), xcoff_bss_section_name); \ else \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s\n", \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,2\n", \ (SIZE), xcoff_bss_section_name); \ } while (0) #endif diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index e818a799b4d..4289a978974 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -3042,7 +3042,7 @@ enum struct ashl_lshr_sequence { char insn_count; - char amount[6]; + signed char amount[6]; char clobbers_t; }; diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 4390bacddf5..f86ae3d3e1e 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -6133,10 +6133,9 @@ label: }) (define_expand "extendqihi2" - [(set (match_operand:HI 0 "arith_reg_dest" "") - (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))] - "" - "") + [(set (match_operand:HI 0 "arith_reg_dest") + (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))] + "TARGET_SH1") (define_insn "*extendqihi2_compact_reg" [(set (match_operand:HI 0 "arith_reg_dest" "=r") diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index f1a3d845e32..5b4d4143f67 100644 --- a/gcc/config/sparc/t-rtems +++ b/gcc/config/sparc/t-rtems @@ -17,6 +17,15 @@ # <http://www.gnu.org/licenses/>. # -MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3 -MULTILIB_DIRNAMES = soft v8 leon3 +MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3/mcpu=leon3v7 muser-mode +MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 user-mode MULTILIB_MATCHES = msoft-float=mno-fpu + +MULTILIB_EXCEPTIONS = muser-mode +MULTILIB_EXCEPTIONS += mcpu=leon3 +MULTILIB_EXCEPTIONS += mcpu=leon3v7 +MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3 +MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3v7 +MULTILIB_EXCEPTIONS += msoft-float/muser-mode +MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/muser-mode +MULTILIB_EXCEPTIONS += mcpu=v8/muser-mode diff --git a/gcc/configure b/gcc/configure index 01767dca0f1..513ea922ec6 100755 --- a/gcc/configure +++ b/gcc/configure @@ -27314,7 +27314,47 @@ if test "x${CLOOGLIBS}" != "x" ; then $as_echo "#define HAVE_cloog 1" >>confdefs.h + + # Check whether isl_schedule_constraints_compute_schedule is available; + # it's new in ISL-0.13. + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $ISLINC" + saved_LIBS="$LIBS" + LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking Checking for isl_schedule_constraints_compute_schedule" >&5 +$as_echo_n "checking Checking for isl_schedule_constraints_compute_schedule... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <isl/schedule.h> +int +main () +{ +isl_schedule_constraints_compute_schedule (NULL); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_has_isl_schedule_constraints_compute_schedule=yes +else + ac_has_isl_schedule_constraints_compute_schedule=no fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_has_isl_schedule_constraints_compute_schedule" >&5 +$as_echo "$ac_has_isl_schedule_constraints_compute_schedule" >&6; } + + LIBS="$saved_LIBS" + CFLAGS="$saved_CFLAGS" + + if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then + +$as_echo "#define HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE 1" >>confdefs.h + + fi +fi + # Check for plugin support # Check whether --enable-plugin was given. diff --git a/gcc/configure.ac b/gcc/configure.ac index ef349a4a688..069ab972806 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5212,8 +5212,31 @@ AC_ARG_VAR(CLOOGLIBS,[How to link CLOOG]) AC_ARG_VAR(CLOOGINC,[How to find CLOOG include files]) if test "x${CLOOGLIBS}" != "x" ; then AC_DEFINE(HAVE_cloog, 1, [Define if cloog is in use.]) + + # Check whether isl_schedule_constraints_compute_schedule is available; + # it's new in ISL-0.13. + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $ISLINC" + saved_LIBS="$LIBS" + LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS" + + AC_MSG_CHECKING([Checking for isl_schedule_constraints_compute_schedule]) + AC_TRY_LINK([#include <isl/schedule.h>], + [isl_schedule_constraints_compute_schedule (NULL);], + [ac_has_isl_schedule_constraints_compute_schedule=yes], + [ac_has_isl_schedule_constraints_compute_schedule=no]) + AC_MSG_RESULT($ac_has_isl_schedule_constraints_compute_schedule) + + LIBS="$saved_LIBS" + CFLAGS="$saved_CFLAGS" + + if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then + AC_DEFINE(HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE, 1, + [Define if isl_schedule_constraints_compute_schedule exists.]) + fi fi + # Check for plugin support AC_ARG_ENABLE(plugin, [AS_HELP_STRING([--enable-plugin], [enable plugin support])], diff --git a/gcc/convert.c b/gcc/convert.c index e124e7a7d47..2b93437e5ea 100644 --- a/gcc/convert.c +++ b/gcc/convert.c @@ -95,6 +95,15 @@ convert_to_real (tree type, tree expr) enum built_in_function fcode = builtin_mathfn_code (expr); tree itype = TREE_TYPE (expr); + if (TREE_CODE (expr) == COMPOUND_EXPR) + { + tree t = convert_to_real (type, TREE_OPERAND (expr, 1)); + if (t == TREE_OPERAND (expr, 1)) + return expr; + return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t), + TREE_OPERAND (expr, 0), t); + } + /* Disable until we figure out how to decide whether the functions are present in runtime. */ /* Convert (float)sqrt((double)x) where x is float into sqrtf(x) */ @@ -366,6 +375,15 @@ convert_to_integer (tree type, tree expr) return error_mark_node; } + if (ex_form == COMPOUND_EXPR) + { + tree t = convert_to_integer (type, TREE_OPERAND (expr, 1)); + if (t == TREE_OPERAND (expr, 1)) + return expr; + return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t), + TREE_OPERAND (expr, 0), t); + } + /* Convert e.g. (long)round(d) -> lround(d). */ /* If we're converting to char, we may encounter differing behavior between converting from double->char vs double->long->char. @@ -854,6 +872,14 @@ convert_to_complex (tree type, tree expr) if (TYPE_MAIN_VARIANT (elt_type) == TYPE_MAIN_VARIANT (subtype)) return expr; + else if (TREE_CODE (expr) == COMPOUND_EXPR) + { + tree t = convert_to_complex (type, TREE_OPERAND (expr, 1)); + if (t == TREE_OPERAND (expr, 1)) + return expr; + return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, + TREE_TYPE (t), TREE_OPERAND (expr, 0), t); + } else if (TREE_CODE (expr) == COMPLEX_EXPR) return fold_build2 (COMPLEX_EXPR, type, convert (subtype, TREE_OPERAND (expr, 0)), diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 917e5cfdd20..9239750e472 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,19 @@ +2015-01-13 Jason Merrill <jason@redhat.com> + + PR c++/64487 + * semantics.c (finish_offsetof): Handle templates here. + * parser.c (cp_parser_builtin_offsetof): Not here. + + PR c++/64251 + * decl2.c (mark_used): Don't mark if in_template_function. + + PR c++/64297 + * typeck.c (apply_memfn_quals): Correct wrong TYPE_CANONICAL. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-10-15 Jason Merrill <jason@redhat.com> PR c++/63455 diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index 7dd98c07e0e..1a604a459b1 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -4606,7 +4606,7 @@ mark_used (tree decl) --function_depth; } - if (processing_template_decl) + if (processing_template_decl || in_template_function ()) return true; /* Check this too in case we're within fold_non_dependent_expr. */ diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index a84bc59cef2..6d8bef43027 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -8024,12 +8024,7 @@ cp_parser_builtin_offsetof (cp_parser *parser) } success: - /* If we're processing a template, we can't finish the semantics yet. - Otherwise we can fold the entire expression now. */ - if (processing_template_decl) - expr = build1 (OFFSETOF_EXPR, size_type_node, expr); - else - expr = finish_offsetof (expr); + expr = finish_offsetof (expr); failure: parser->integral_constant_expression_p = save_ice_p; diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index 30ec7fcf565..329f12f0900 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -3651,6 +3651,14 @@ finish_bases (tree type, bool direct) tree finish_offsetof (tree expr) { + /* If we're processing a template, we can't finish the semantics yet. + Otherwise we can fold the entire expression now. */ + if (processing_template_decl) + { + expr = build1 (OFFSETOF_EXPR, size_type_node, expr); + return expr; + } + if (TREE_CODE (expr) == PSEUDO_DTOR_EXPR) { error ("cannot apply %<offsetof%> to destructor %<~%T%>", diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index 2fa47025b7d..6da2f3b197d 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -8639,6 +8639,12 @@ apply_memfn_quals (tree type, cp_cv_quals memfn_quals, cp_ref_qualifier rqual) /* This should really have a different TYPE_MAIN_VARIANT, but that gets complex. */ tree result = build_qualified_type (type, memfn_quals); + if (tree canon = TYPE_CANONICAL (result)) + if (canon != result) + /* check_qualified_type doesn't check the ref-qualifier, so make sure + TYPE_CANONICAL is correct. */ + TYPE_CANONICAL (result) + = build_ref_qualified_type (canon, type_memfn_rqual (result)); result = build_exception_variant (result, TYPE_RAISES_EXCEPTIONS (type)); return build_ref_qualified_type (result, rqual); } diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index a0b30294434..dc3e0bcba46 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -12310,16 +12310,22 @@ vector bool int vec_cmplt (vector unsigned int, vector unsigned int); vector bool int vec_cmplt (vector signed int, vector signed int); vector bool int vec_cmplt (vector float, vector float); +vector float vec_cpsgn (vector float, vector float); + vector float vec_ctf (vector unsigned int, const int); vector float vec_ctf (vector signed int, const int); +vector double vec_ctf (vector unsigned long, const int); +vector double vec_ctf (vector signed long, const int); vector float vec_vcfsx (vector signed int, const int); vector float vec_vcfux (vector unsigned int, const int); vector signed int vec_cts (vector float, const int); +vector signed long vec_cts (vector double, const int); vector unsigned int vec_ctu (vector float, const int); +vector unsigned long vec_ctu (vector double, const int); void vec_dss (const int); @@ -13155,6 +13161,16 @@ vector float vec_splat (vector float, const int); vector signed int vec_splat (vector signed int, const int); vector unsigned int vec_splat (vector unsigned int, const int); vector bool int vec_splat (vector bool int, const int); +vector signed long vec_splat (vector signed long, const int); +vector unsigned long vec_splat (vector unsigned long, const int); + +vector signed char vec_splats (signed char); +vector unsigned char vec_splats (unsigned char); +vector signed short vec_splats (signed short); +vector unsigned short vec_splats (unsigned short); +vector signed int vec_splats (signed int); +vector unsigned int vec_splats (unsigned int); +vector float vec_splats (float); vector float vec_vspltw (vector float, const int); vector signed int vec_vspltw (vector signed int, const int); @@ -13859,17 +13875,32 @@ vector double vec_add (vector double, vector double); vector double vec_and (vector double, vector double); vector double vec_and (vector double, vector bool long); vector double vec_and (vector bool long, vector double); +vector long vec_and (vector long, vector long); +vector long vec_and (vector long, vector bool long); +vector long vec_and (vector bool long, vector long); +vector unsigned long vec_and (vector unsigned long, vector unsigned long); +vector unsigned long vec_and (vector unsigned long, vector bool long); +vector unsigned long vec_and (vector bool long, vector unsigned long); vector double vec_andc (vector double, vector double); vector double vec_andc (vector double, vector bool long); vector double vec_andc (vector bool long, vector double); +vector long vec_andc (vector long, vector long); +vector long vec_andc (vector long, vector bool long); +vector long vec_andc (vector bool long, vector long); +vector unsigned long vec_andc (vector unsigned long, vector unsigned long); +vector unsigned long vec_andc (vector unsigned long, vector bool long); +vector unsigned long vec_andc (vector bool long, vector unsigned long); vector double vec_ceil (vector double); vector bool long vec_cmpeq (vector double, vector double); vector bool long vec_cmpge (vector double, vector double); vector bool long vec_cmpgt (vector double, vector double); vector bool long vec_cmple (vector double, vector double); vector bool long vec_cmplt (vector double, vector double); +vector double vec_cpsgn (vector double, vector double); vector float vec_div (vector float, vector float); vector double vec_div (vector double, vector double); +vector long vec_div (vector long, vector long); +vector unsigned long vec_div (vector unsigned long, vector unsigned long); vector double vec_floor (vector double); vector double vec_ld (int, const vector double *); vector double vec_ld (int, const double *); @@ -13879,38 +13910,83 @@ vector unsigned char vec_lvsl (int, const volatile double *); vector unsigned char vec_lvsr (int, const volatile double *); vector double vec_madd (vector double, vector double, vector double); vector double vec_max (vector double, vector double); +vector signed long vec_mergeh (vector signed long, vector signed long); +vector signed long vec_mergeh (vector signed long, vector bool long); +vector signed long vec_mergeh (vector bool long, vector signed long); +vector unsigned long vec_mergeh (vector unsigned long, vector unsigned long); +vector unsigned long vec_mergeh (vector unsigned long, vector bool long); +vector unsigned long vec_mergeh (vector bool long, vector unsigned long); +vector signed long vec_mergel (vector signed long, vector signed long); +vector signed long vec_mergel (vector signed long, vector bool long); +vector signed long vec_mergel (vector bool long, vector signed long); +vector unsigned long vec_mergel (vector unsigned long, vector unsigned long); +vector unsigned long vec_mergel (vector unsigned long, vector bool long); +vector unsigned long vec_mergel (vector bool long, vector unsigned long); vector double vec_min (vector double, vector double); vector float vec_msub (vector float, vector float, vector float); vector double vec_msub (vector double, vector double, vector double); vector float vec_mul (vector float, vector float); vector double vec_mul (vector double, vector double); +vector long vec_mul (vector long, vector long); +vector unsigned long vec_mul (vector unsigned long, vector unsigned long); vector float vec_nearbyint (vector float); vector double vec_nearbyint (vector double); vector float vec_nmadd (vector float, vector float, vector float); vector double vec_nmadd (vector double, vector double, vector double); vector double vec_nmsub (vector double, vector double, vector double); vector double vec_nor (vector double, vector double); +vector long vec_nor (vector long, vector long); +vector long vec_nor (vector long, vector bool long); +vector long vec_nor (vector bool long, vector long); +vector unsigned long vec_nor (vector unsigned long, vector unsigned long); +vector unsigned long vec_nor (vector unsigned long, vector bool long); +vector unsigned long vec_nor (vector bool long, vector unsigned long); vector double vec_or (vector double, vector double); vector double vec_or (vector double, vector bool long); vector double vec_or (vector bool long, vector double); -vector double vec_perm (vector double, - vector double, - vector unsigned char); +vector long vec_or (vector long, vector long); +vector long vec_or (vector long, vector bool long); +vector long vec_or (vector bool long, vector long); +vector unsigned long vec_or (vector unsigned long, vector unsigned long); +vector unsigned long vec_or (vector unsigned long, vector bool long); +vector unsigned long vec_or (vector bool long, vector unsigned long); +vector double vec_perm (vector double, vector double, vector unsigned char); +vector long vec_perm (vector long, vector long, vector unsigned char); +vector unsigned long vec_perm (vector unsigned long, vector unsigned long, + vector unsigned char); vector double vec_rint (vector double); vector double vec_recip (vector double, vector double); vector double vec_rsqrt (vector double); vector double vec_rsqrte (vector double); vector double vec_sel (vector double, vector double, vector bool long); vector double vec_sel (vector double, vector double, vector unsigned long); -vector double vec_sub (vector double, vector double); +vector long vec_sel (vector long, vector long, vector long); +vector long vec_sel (vector long, vector long, vector unsigned long); +vector long vec_sel (vector long, vector long, vector bool long); +vector unsigned long vec_sel (vector unsigned long, vector unsigned long, + vector long); +vector unsigned long vec_sel (vector unsigned long, vector unsigned long, + vector unsigned long); +vector unsigned long vec_sel (vector unsigned long, vector unsigned long, + vector bool long); +vector double vec_splats (double); +vector signed long vec_splats (signed long); +vector unsigned long vec_splats (unsigned long); vector float vec_sqrt (vector float); vector double vec_sqrt (vector double); void vec_st (vector double, int, vector double *); void vec_st (vector double, int, double *); +vector double vec_sub (vector double, vector double); vector double vec_trunc (vector double); vector double vec_xor (vector double, vector double); vector double vec_xor (vector double, vector bool long); vector double vec_xor (vector bool long, vector double); +vector long vec_xor (vector long, vector long); +vector long vec_xor (vector long, vector bool long); +vector long vec_xor (vector bool long, vector long); +vector unsigned long vec_xor (vector unsigned long, vector unsigned long); +vector unsigned long vec_xor (vector unsigned long, vector bool long); +vector unsigned long vec_xor (vector bool long, vector unsigned long); int vec_all_eq (vector double, vector double); int vec_all_ge (vector double, vector double); int vec_all_gt (vector double, vector double); @@ -14039,17 +14115,30 @@ vector unsigned long long vec_add (vector unsigned long long, vector unsigned long long); int vec_all_eq (vector long long, vector long long); +int vec_all_eq (vector unsigned long long, vector unsigned long long); int vec_all_ge (vector long long, vector long long); +int vec_all_ge (vector unsigned long long, vector unsigned long long); int vec_all_gt (vector long long, vector long long); +int vec_all_gt (vector unsigned long long, vector unsigned long long); int vec_all_le (vector long long, vector long long); +int vec_all_le (vector unsigned long long, vector unsigned long long); int vec_all_lt (vector long long, vector long long); +int vec_all_lt (vector unsigned long long, vector unsigned long long); int vec_all_ne (vector long long, vector long long); +int vec_all_ne (vector unsigned long long, vector unsigned long long); + int vec_any_eq (vector long long, vector long long); +int vec_any_eq (vector unsigned long long, vector unsigned long long); int vec_any_ge (vector long long, vector long long); +int vec_any_ge (vector unsigned long long, vector unsigned long long); int vec_any_gt (vector long long, vector long long); +int vec_any_gt (vector unsigned long long, vector unsigned long long); int vec_any_le (vector long long, vector long long); +int vec_any_le (vector unsigned long long, vector unsigned long long); int vec_any_lt (vector long long, vector long long); +int vec_any_lt (vector unsigned long long, vector unsigned long long); int vec_any_ne (vector long long, vector long long); +int vec_any_ne (vector unsigned long long, vector unsigned long long); vector long long vec_eqv (vector long long, vector long long); vector long long vec_eqv (vector bool long long, vector long long); @@ -14087,6 +14176,14 @@ vector long long vec_max (vector long long, vector long long); vector unsigned long long vec_max (vector unsigned long long, vector unsigned long long); +vector signed int vec_mergee (vector signed int, vector signed int); +vector unsigned int vec_mergee (vector unsigned int, vector unsigned int); +vector bool int vec_mergee (vector bool int, vector bool int); + +vector signed int vec_mergeo (vector signed int, vector signed int); +vector unsigned int vec_mergeo (vector unsigned int, vector unsigned int); +vector bool int vec_mergeo (vector bool int, vector bool int); + vector long long vec_min (vector long long, vector long long); vector unsigned long long vec_min (vector unsigned long long, vector unsigned long long); @@ -14165,6 +14262,8 @@ vector unsigned int vec_packs (vector unsigned long long, vector unsigned long long); vector unsigned int vec_packsu (vector long long, vector long long); +vector unsigned int vec_packsu (vector unsigned long long, + vector unsigned long long); vector long long vec_rl (vector long long, vector unsigned long long); @@ -14206,6 +14305,15 @@ vector unsigned long long vec_vaddudm (vector unsigned long long, vector long long vec_vbpermq (vector signed char, vector signed char); vector long long vec_vbpermq (vector unsigned char, vector unsigned char); +vector long long vec_cntlz (vector long long); +vector unsigned long long vec_cntlz (vector unsigned long long); +vector int vec_cntlz (vector int); +vector unsigned int vec_cntlz (vector int); +vector short vec_cntlz (vector short); +vector unsigned short vec_cntlz (vector unsigned short); +vector signed char vec_cntlz (vector signed char); +vector unsigned char vec_cntlz (vector unsigned char); + vector long long vec_vclz (vector long long); vector unsigned long long vec_vclz (vector unsigned long long); vector int vec_vclz (vector int); diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 8254ff5e1be..d260c49e5d4 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -8169,9 +8169,9 @@ must be a @code{label_ref}. @cindex @code{pc} and attributes @item (pc) -This refers to the address of the @emph{current} insn. It might have -been more consistent with other usage to make this the address of the -@emph{next} insn but this would be confusing because the length of the +For non-branch instructions and backward branch instructions, this refers +to the address of the current insn. But for forward branch instructions, +this refers to the address of the next insn, because the length of the current insn is to be computed. @end table diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index dbe3d1278f9..327e05d66e7 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -4424,10 +4424,6 @@ to return a nonzero value when it is required, the compiler will run out of spill registers and print a fatal error message. @end deftypefn -@deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM -If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately. -@end deftypevr - @node Scalar Return @subsection How Scalar Function Values Are Returned @cindex return values in registers @@ -5901,7 +5897,6 @@ interested in most macros in this section. @menu * CC0 Condition Codes:: Old style representation of condition codes. * MODE_CC Condition Codes:: Modern representation of condition codes. -* Cond Exec Macros:: Macros to control conditional execution. @end menu @node CC0 Condition Codes @@ -6014,10 +6009,11 @@ for comparisons whose argument is a @code{plus}: @smallexample #define SELECT_CC_MODE(OP,X,Y) \ - (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ - ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ - : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ - || GET_CODE (X) == NEG) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + ? ((OP == LT || OP == LE || OP == GT || OP == GE) \ + ? CCFPEmode : CCFPmode) \ + : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ + || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \ ? CC_NOOVmode : CCmode)) @end smallexample @@ -6060,10 +6056,11 @@ then @code{REVERSIBLE_CC_MODE (@var{mode})} must be zero. You need not define this macro if it would always returns zero or if the floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}. For example, here is the definition used on the SPARC, where floating-point -inequality comparisons are always given @code{CCFPEmode}: +inequality comparisons are given either @code{CCFPEmode} or @code{CCFPmode}: @smallexample -#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) +#define REVERSIBLE_CC_MODE(MODE) \ + ((MODE) != CCFPEmode && (MODE) != CCFPmode) @end smallexample @end defmac @@ -6073,7 +6070,7 @@ comparison done in CC_MODE @var{mode}. The macro is used only in case @code{REVERSIBLE_CC_MODE (@var{mode})} is nonzero. Define this macro in case machine has some non-standard way how to reverse certain conditionals. For instance in case all floating point conditions are non-trapping, compiler may -freely convert unordered compares to ordered one. Then definition may look +freely convert unordered compares to ordered ones. Then definition may look like: @smallexample @@ -6111,14 +6108,9 @@ same. If they are, it returns that mode. If they are different, it returns @code{VOIDmode}. @end deftypefn -@node Cond Exec Macros -@subsection Macros to control conditional execution -@findex conditional execution -@findex predication - -There is one macro that may need to be defined for targets -supporting conditional execution, independent of how they -represent conditional branches. +@deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM +If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately. +@end deftypevr @node Costs @section Describing Relative Costs of Operations diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 5bd515a5d5c..1038fb1d50a 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -4359,8 +4359,6 @@ to return a nonzero value when it is required, the compiler will run out of spill registers and print a fatal error message. @end deftypefn -@hook TARGET_FLAGS_REGNUM - @node Scalar Return @subsection How Scalar Function Values Are Returned @cindex return values in registers @@ -5805,7 +5803,6 @@ interested in most macros in this section. @menu * CC0 Condition Codes:: Old style representation of condition codes. * MODE_CC Condition Codes:: Modern representation of condition codes. -* Cond Exec Macros:: Macros to control conditional execution. @end menu @node CC0 Condition Codes @@ -5918,10 +5915,11 @@ for comparisons whose argument is a @code{plus}: @smallexample #define SELECT_CC_MODE(OP,X,Y) \ - (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ - ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ - : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ - || GET_CODE (X) == NEG) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + ? ((OP == LT || OP == LE || OP == GT || OP == GE) \ + ? CCFPEmode : CCFPmode) \ + : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ + || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \ ? CC_NOOVmode : CCmode)) @end smallexample @@ -5964,10 +5962,11 @@ then @code{REVERSIBLE_CC_MODE (@var{mode})} must be zero. You need not define this macro if it would always returns zero or if the floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}. For example, here is the definition used on the SPARC, where floating-point -inequality comparisons are always given @code{CCFPEmode}: +inequality comparisons are given either @code{CCFPEmode} or @code{CCFPmode}: @smallexample -#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) +#define REVERSIBLE_CC_MODE(MODE) \ + ((MODE) != CCFPEmode && (MODE) != CCFPmode) @end smallexample @end defmac @@ -5977,7 +5976,7 @@ comparison done in CC_MODE @var{mode}. The macro is used only in case @code{REVERSIBLE_CC_MODE (@var{mode})} is nonzero. Define this macro in case machine has some non-standard way how to reverse certain conditionals. For instance in case all floating point conditions are non-trapping, compiler may -freely convert unordered compares to ordered one. Then definition may look +freely convert unordered compares to ordered ones. Then definition may look like: @smallexample @@ -6015,14 +6014,7 @@ same. If they are, it returns that mode. If they are different, it returns @code{VOIDmode}. @end deftypefn -@node Cond Exec Macros -@subsection Macros to control conditional execution -@findex conditional execution -@findex predication - -There is one macro that may need to be defined for targets -supporting conditional execution, independent of how they -represent conditional branches. +@hook TARGET_FLAGS_REGNUM @node Costs @section Describing Relative Costs of Operations diff --git a/gcc/expr.c b/gcc/expr.c index f83a7d0d448..8ec37336989 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -4708,8 +4708,6 @@ expand_assignment (tree to, tree from, bool nontemporal) int unsignedp; int volatilep = 0; tree tem; - bool misalignp; - rtx mem = NULL_RTX; push_temp_slots (); tem = get_inner_reference (to, &bitsize, &bitpos, &offset, &mode1, @@ -4728,40 +4726,7 @@ expand_assignment (tree to, tree from, bool nontemporal) && DECL_BIT_FIELD_TYPE (TREE_OPERAND (to, 1))) get_bit_range (&bitregion_start, &bitregion_end, to, &bitpos, &offset); - /* If we are going to use store_bit_field and extract_bit_field, - make sure to_rtx will be safe for multiple use. */ - mode = TYPE_MODE (TREE_TYPE (tem)); - if (TREE_CODE (tem) == MEM_REF - && mode != BLKmode - && ((align = get_object_alignment (tem)) - < GET_MODE_ALIGNMENT (mode)) - && ((icode = optab_handler (movmisalign_optab, mode)) - != CODE_FOR_nothing)) - { - struct expand_operand ops[2]; - - misalignp = true; - to_rtx = gen_reg_rtx (mode); - mem = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_WRITE); - - /* If the misaligned store doesn't overwrite all bits, perform - rmw cycle on MEM. */ - if (bitsize != GET_MODE_BITSIZE (mode)) - { - create_input_operand (&ops[0], to_rtx, mode); - create_fixed_operand (&ops[1], mem); - /* The movmisalign<mode> pattern cannot fail, else the assignment - would silently be omitted. */ - expand_insn (icode, 2, ops); - - mem = copy_rtx (mem); - } - } - else - { - misalignp = false; - to_rtx = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_WRITE); - } + to_rtx = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_WRITE); /* If the bitfield is volatile, we want to access it in the field's mode, not the computed mode. @@ -4900,17 +4865,6 @@ expand_assignment (tree to, tree from, bool nontemporal) get_alias_set (to), nontemporal); } - if (misalignp) - { - struct expand_operand ops[2]; - - create_fixed_operand (&ops[0], mem); - create_input_operand (&ops[1], to_rtx, mode); - /* The movmisalign<mode> pattern cannot fail, else the assignment - would silently be omitted. */ - expand_insn (icode, 2, ops); - } - if (result) preserve_temp_slots (result); pop_temp_slots (); @@ -5262,7 +5216,7 @@ store_expr (tree exp, rtx target, int call_param_p, bool nontemporal) temp = expand_expr_real (exp, tmp_target, GET_MODE (target), (call_param_p ? EXPAND_STACK_PARM : EXPAND_NORMAL), - &alt_rtl); + &alt_rtl, false); } /* If TEMP is a VOIDmode constant and the mode of the type of EXP is not @@ -7590,11 +7544,13 @@ expand_expr_addr_expr_1 (tree exp, rtx target, enum machine_mode tmode, break; case COMPOUND_LITERAL_EXPR: - /* Allow COMPOUND_LITERAL_EXPR in initializers, if e.g. - rtl_for_decl_init is called on DECL_INITIAL with - COMPOUNT_LITERAL_EXPRs in it, they aren't gimplified. */ - if (modifier == EXPAND_INITIALIZER - && COMPOUND_LITERAL_EXPR_DECL (exp)) + /* Allow COMPOUND_LITERAL_EXPR in initializers or coming from + initializers, if e.g. rtl_for_decl_init is called on DECL_INITIAL + with COMPOUND_LITERAL_EXPRs in it, or ARRAY_REF on a const static + array with address of COMPOUND_LITERAL_EXPR in DECL_INITIAL; + the initializers aren't gimplified. */ + if (COMPOUND_LITERAL_EXPR_DECL (exp) + && TREE_STATIC (COMPOUND_LITERAL_EXPR_DECL (exp))) return expand_expr_addr_expr_1 (COMPOUND_LITERAL_EXPR_DECL (exp), target, tmode, modifier, as); /* FALLTHRU */ @@ -7879,11 +7835,21 @@ expand_constructor (tree exp, rtx target, enum expand_modifier modifier, address, and ALT_RTL is non-NULL, then *ALT_RTL is set to the DECL_RTL of the VAR_DECL. *ALT_RTL is also set if EXP is a COMPOUND_EXPR whose second argument is such a VAR_DECL, and so on - recursively. */ + recursively. + + If INNER_REFERENCE_P is true, we are expanding an inner reference. + In this case, we don't adjust a returned MEM rtx that wouldn't be + sufficiently aligned for its mode; instead, it's up to the caller + to deal with it afterwards. This is used to make sure that unaligned + base objects for which out-of-bounds accesses are supported, for + example record types with trailing arrays, aren't realigned behind + the back of the caller. + The normal operating mode is to pass FALSE for this parameter. */ rtx expand_expr_real (tree exp, rtx target, enum machine_mode tmode, - enum expand_modifier modifier, rtx *alt_rtl) + enum expand_modifier modifier, rtx *alt_rtl, + bool inner_reference_p) { rtx ret; @@ -7895,7 +7861,8 @@ expand_expr_real (tree exp, rtx target, enum machine_mode tmode, return ret ? ret : const0_rtx; } - ret = expand_expr_real_1 (exp, target, tmode, modifier, alt_rtl); + ret = expand_expr_real_1 (exp, target, tmode, modifier, alt_rtl, + inner_reference_p); return ret; } @@ -9188,7 +9155,8 @@ expand_expr_real_2 (sepops ops, rtx target, enum machine_mode tmode, rtx expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, - enum expand_modifier modifier, rtx *alt_rtl) + enum expand_modifier modifier, rtx *alt_rtl, + bool inner_reference_p) { rtx op0, op1, temp, decl_rtl; tree type; @@ -9334,7 +9302,7 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, set_curr_insn_location (gimple_location (g)); r = expand_expr_real (gimple_assign_rhs_to_tree (g), target, - tmode, modifier, NULL); + tmode, modifier, NULL, inner_reference_p); set_curr_insn_location (saved_loc); if (REG_P (r) && !REG_EXPR (r)) set_reg_attrs_for_decl_rtl (SSA_NAME_VAR (exp), r); @@ -9555,7 +9523,8 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, case SAVE_EXPR: { tree val = treeop0; - rtx ret = expand_expr_real_1 (val, target, tmode, modifier, alt_rtl); + rtx ret = expand_expr_real_1 (val, target, tmode, modifier, alt_rtl, + inner_reference_p); if (!SAVE_EXPR_RESOLVED_P (exp)) { @@ -9704,6 +9673,7 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, MEM_VOLATILE_P (temp) = 1; if (modifier != EXPAND_WRITE && modifier != EXPAND_MEMORY + && !inner_reference_p && mode != BLKmode && align < GET_MODE_ALIGNMENT (mode)) { @@ -9938,18 +9908,19 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, computation, since it will need a temporary and TARGET is known to have to do. This occurs in unchecked conversion in Ada. */ orig_op0 = op0 - = expand_expr (tem, - (TREE_CODE (TREE_TYPE (tem)) == UNION_TYPE - && COMPLETE_TYPE_P (TREE_TYPE (tem)) - && (TREE_CODE (TYPE_SIZE (TREE_TYPE (tem))) - != INTEGER_CST) - && modifier != EXPAND_STACK_PARM - ? target : NULL_RTX), - VOIDmode, - (modifier == EXPAND_INITIALIZER - || modifier == EXPAND_CONST_ADDRESS - || modifier == EXPAND_STACK_PARM) - ? modifier : EXPAND_NORMAL); + = expand_expr_real (tem, + (TREE_CODE (TREE_TYPE (tem)) == UNION_TYPE + && COMPLETE_TYPE_P (TREE_TYPE (tem)) + && (TREE_CODE (TYPE_SIZE (TREE_TYPE (tem))) + != INTEGER_CST) + && modifier != EXPAND_STACK_PARM + ? target : NULL_RTX), + VOIDmode, + (modifier == EXPAND_INITIALIZER + || modifier == EXPAND_CONST_ADDRESS + || modifier == EXPAND_STACK_PARM) + ? modifier : EXPAND_NORMAL, + NULL, true); /* If the bitfield is volatile, we want to access it in the @@ -10300,17 +10271,18 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, { /* See the normal_inner_ref case for the rationale. */ orig_op0 - = expand_expr (tem, - (TREE_CODE (TREE_TYPE (tem)) == UNION_TYPE - && (TREE_CODE (TYPE_SIZE (TREE_TYPE (tem))) - != INTEGER_CST) - && modifier != EXPAND_STACK_PARM - ? target : NULL_RTX), - VOIDmode, - (modifier == EXPAND_INITIALIZER - || modifier == EXPAND_CONST_ADDRESS - || modifier == EXPAND_STACK_PARM) - ? modifier : EXPAND_NORMAL); + = expand_expr_real (tem, + (TREE_CODE (TREE_TYPE (tem)) == UNION_TYPE + && (TREE_CODE (TYPE_SIZE (TREE_TYPE (tem))) + != INTEGER_CST) + && modifier != EXPAND_STACK_PARM + ? target : NULL_RTX), + VOIDmode, + (modifier == EXPAND_INITIALIZER + || modifier == EXPAND_CONST_ADDRESS + || modifier == EXPAND_STACK_PARM) + ? modifier : EXPAND_NORMAL, + NULL, true); if (MEM_P (orig_op0)) { @@ -10337,8 +10309,8 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, } if (!op0) - op0 = expand_expr (treeop0, - NULL_RTX, VOIDmode, modifier); + op0 = expand_expr_real (treeop0, NULL_RTX, VOIDmode, modifier, + NULL, inner_reference_p); /* If the input and output modes are both the same, we are done. */ if (mode == GET_MODE (op0)) @@ -10405,50 +10377,53 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, op0 = copy_rtx (op0); set_mem_align (op0, MAX (MEM_ALIGN (op0), TYPE_ALIGN (type))); } - else if (mode != BLKmode - && MEM_ALIGN (op0) < GET_MODE_ALIGNMENT (mode) - /* If the target does have special handling for unaligned - loads of mode then use them. */ - && ((icode = optab_handler (movmisalign_optab, mode)) - != CODE_FOR_nothing)) - { - rtx reg, insn; - - op0 = adjust_address (op0, mode, 0); - /* We've already validated the memory, and we're creating a - new pseudo destination. The predicates really can't - fail. */ - reg = gen_reg_rtx (mode); - - /* Nor can the insn generator. */ - insn = GEN_FCN (icode) (reg, op0); - emit_insn (insn); - return reg; - } - else if (STRICT_ALIGNMENT + else if (modifier != EXPAND_WRITE + && modifier != EXPAND_MEMORY + && !inner_reference_p && mode != BLKmode && MEM_ALIGN (op0) < GET_MODE_ALIGNMENT (mode)) { - tree inner_type = TREE_TYPE (treeop0); - HOST_WIDE_INT temp_size - = MAX (int_size_in_bytes (inner_type), - (HOST_WIDE_INT) GET_MODE_SIZE (mode)); - rtx new_rtx - = assign_stack_temp_for_type (mode, temp_size, type); - rtx new_with_op0_mode - = adjust_address (new_rtx, GET_MODE (op0), 0); - - gcc_assert (!TREE_ADDRESSABLE (exp)); - - if (GET_MODE (op0) == BLKmode) - emit_block_move (new_with_op0_mode, op0, - GEN_INT (GET_MODE_SIZE (mode)), - (modifier == EXPAND_STACK_PARM - ? BLOCK_OP_CALL_PARM : BLOCK_OP_NORMAL)); - else - emit_move_insn (new_with_op0_mode, op0); + /* If the target does have special handling for unaligned + loads of mode then use them. */ + if ((icode = optab_handler (movmisalign_optab, mode)) + != CODE_FOR_nothing) + { + rtx reg, insn; + + op0 = adjust_address (op0, mode, 0); + /* We've already validated the memory, and we're creating a + new pseudo destination. The predicates really can't + fail. */ + reg = gen_reg_rtx (mode); + + /* Nor can the insn generator. */ + insn = GEN_FCN (icode) (reg, op0); + emit_insn (insn); + return reg; + } + else if (STRICT_ALIGNMENT) + { + tree inner_type = TREE_TYPE (treeop0); + HOST_WIDE_INT temp_size + = MAX (int_size_in_bytes (inner_type), + (HOST_WIDE_INT) GET_MODE_SIZE (mode)); + rtx new_rtx + = assign_stack_temp_for_type (mode, temp_size, type); + rtx new_with_op0_mode + = adjust_address (new_rtx, GET_MODE (op0), 0); + + gcc_assert (!TREE_ADDRESSABLE (exp)); + + if (GET_MODE (op0) == BLKmode) + emit_block_move (new_with_op0_mode, op0, + GEN_INT (GET_MODE_SIZE (mode)), + (modifier == EXPAND_STACK_PARM + ? BLOCK_OP_CALL_PARM : BLOCK_OP_NORMAL)); + else + emit_move_insn (new_with_op0_mode, op0); - op0 = new_rtx; + op0 = new_rtx; + } } op0 = adjust_address (op0, mode, 0); @@ -10548,7 +10523,7 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, /* WITH_SIZE_EXPR expands to its first argument. The caller should have pulled out the size to use in whatever context it needed. */ return expand_expr_real (treeop0, original_target, tmode, - modifier, alt_rtl); + modifier, alt_rtl, inner_reference_p); default: return expand_expr_real_2 (&ops, target, tmode, modifier); diff --git a/gcc/expr.h b/gcc/expr.h index 98c9daeda9c..4adebe43044 100644 --- a/gcc/expr.h +++ b/gcc/expr.h @@ -41,7 +41,8 @@ along with GCC; see the file COPYING3. If not see is a constant that is not a legitimate address. EXPAND_WRITE means we are only going to write to the resulting rtx. EXPAND_MEMORY means we are interested in a memory result, even if - the memory is constant and we could have propagated a constant value. */ + the memory is constant and we could have propagated a constant value, + or the memory is unaligned on a STRICT_ALIGNMENT target. */ enum expand_modifier {EXPAND_NORMAL = 0, EXPAND_STACK_PARM, EXPAND_SUM, EXPAND_CONST_ADDRESS, EXPAND_INITIALIZER, EXPAND_WRITE, EXPAND_MEMORY}; @@ -428,9 +429,9 @@ extern rtx force_operand (rtx, rtx); /* Work horses for expand_expr. */ extern rtx expand_expr_real (tree, rtx, enum machine_mode, - enum expand_modifier, rtx *); + enum expand_modifier, rtx *, bool); extern rtx expand_expr_real_1 (tree, rtx, enum machine_mode, - enum expand_modifier, rtx *); + enum expand_modifier, rtx *, bool); extern rtx expand_expr_real_2 (sepops, rtx, enum machine_mode, enum expand_modifier); @@ -441,13 +442,13 @@ static inline rtx expand_expr (tree exp, rtx target, enum machine_mode mode, enum expand_modifier modifier) { - return expand_expr_real (exp, target, mode, modifier, NULL); + return expand_expr_real (exp, target, mode, modifier, NULL, false); } static inline rtx expand_normal (tree exp) { - return expand_expr_real (exp, NULL_RTX, VOIDmode, EXPAND_NORMAL, NULL); + return expand_expr_real (exp, NULL_RTX, VOIDmode, EXPAND_NORMAL, NULL, false); } /* At the start of a function, record that we have no previously-pushed diff --git a/gcc/fold-const.c b/gcc/fold-const.c index a775f2713c1..2feaa4eba46 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -8933,7 +8933,8 @@ fold_comparison (location_t loc, enum tree_code code, tree type, /* If the constant operation overflowed this can be simplified as a comparison against INT_MAX/INT_MIN. */ if (TREE_CODE (lhs) == INTEGER_CST - && TREE_OVERFLOW (lhs)) + && TREE_OVERFLOW (lhs) + && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0))) { int const1_sgn = tree_int_cst_sgn (const1); enum tree_code code2 = code; @@ -13085,6 +13086,8 @@ fold_binary_loc (location_t loc, tree arg01 = TREE_OPERAND (arg0, 1); tree itype = TREE_TYPE (arg00); if (TREE_INT_CST_HIGH (arg01) == 0 + && !(TREE_CODE (itype) == COMPLEX_TYPE + || TREE_CODE (itype) == VECTOR_TYPE) && TREE_INT_CST_LOW (arg01) == (unsigned HOST_WIDE_INT) (TYPE_PRECISION (itype) - 1)) { diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index b5dfcf1fa47..81c4c1d860e 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,55 @@ +2015-02-01 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2015-01-13 Jakub Jelinek <jakub@redhat.com> + + PR fortran/64528 + * trans-decl.c (create_function_arglist): Don't set TREE_READONLY + on dummy args with VALUE attribute. + +2015-01-24 Thomas Koenig <tkoenig@gcc.gnu.org> + + PR fortran/56867 + * trans-array.c (gfc_conv_resolve_dependencies): Also check + dependencies when there may be substrings of character arrays. + +2015-01-24 Thomas Koenig <tkoenig@netcologne.de> + + Backport from trunk + PR fortran/57023 + * dependency.c (callback_dummy_intent_not_int): New function. + (dummy_intent_not_in): New function. + (gfc_full_array_ref_p): Use dummy_intent_not_in. + +2015-01-12 Janus Weil <janus@gcc.gnu.org> + + Backport from mainline + PR fortran/63733 + * interface.c (gfc_extend_expr): Look for type-bound operators before + non-typebound ones. + +2014-12-23 Janus Weil <janus@gcc.gnu.org> + + Backport from mainline + PR fortran/64244 + * resolve.c (resolve_typebound_call): New argument to pass out the + non-overridable attribute of the specific procedure. + (resolve_typebound_subroutine): Get overridable flag from + resolve_typebound_call. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-24 Jakub Jelinek <jakub@redhat.com> + + PR fortran/63938 + * trans-openmp.c (gfc_trans_omp_atomic): Make sure lhsaddr is + simple enough for goa_lhs_expr_p. + 2014-10-10 Jakub Jelinek <jakub@redhat.com> PR fortran/59488 diff --git a/gcc/fortran/dependency.c b/gcc/fortran/dependency.c index 3924905f0ef..a40b891ffdf 100644 --- a/gcc/fortran/dependency.c +++ b/gcc/fortran/dependency.c @@ -1604,11 +1604,40 @@ gfc_check_element_vs_element (gfc_ref *lref, gfc_ref *rref, int n) return GFC_DEP_EQUAL; } +/* Callback function for checking if an expression depends on a + dummy variable which is any other than INTENT(IN). */ + +static int +callback_dummy_intent_not_in (gfc_expr **ep, + int *walk_subtrees ATTRIBUTE_UNUSED, + void *data ATTRIBUTE_UNUSED) +{ + gfc_expr *e = *ep; + + if (e->expr_type == EXPR_VARIABLE && e->symtree + && e->symtree->n.sym->attr.dummy) + return e->symtree->n.sym->attr.intent != INTENT_IN; + else + return 0; +} + +/* Auxiliary function to check if subexpressions have dummy variables which + are not intent(in). +*/ + +static bool +dummy_intent_not_in (gfc_expr **ep) +{ + return gfc_expr_walker (ep, callback_dummy_intent_not_in, NULL); +} /* Determine if an array ref, usually an array section specifies the entire array. In addition, if the second, pointer argument is provided, the function will return true if the reference is - contiguous; eg. (:, 1) gives true but (1,:) gives false. */ + contiguous; eg. (:, 1) gives true but (1,:) gives false. + If one of the bounds depends on a dummy variable which is + not INTENT(IN), also return false, because the user may + have changed the variable. */ bool gfc_full_array_ref_p (gfc_ref *ref, bool *contiguous) @@ -1672,14 +1701,16 @@ gfc_full_array_ref_p (gfc_ref *ref, bool *contiguous) && (!ref->u.ar.as || !ref->u.ar.as->lower[i] || gfc_dep_compare_expr (ref->u.ar.start[i], - ref->u.ar.as->lower[i]))) + ref->u.ar.as->lower[i]) + || dummy_intent_not_in (&ref->u.ar.start[i]))) lbound_OK = false; /* Check the upper bound. */ if (ref->u.ar.end[i] && (!ref->u.ar.as || !ref->u.ar.as->upper[i] || gfc_dep_compare_expr (ref->u.ar.end[i], - ref->u.ar.as->upper[i]))) + ref->u.ar.as->upper[i]) + || dummy_intent_not_in (&ref->u.ar.end[i]))) ubound_OK = false; /* Check the stride. */ if (ref->u.ar.stride[i] diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c index e38bb1f5d0b..2d739426e22 100644 --- a/gcc/fortran/interface.c +++ b/gcc/fortran/interface.c @@ -3557,6 +3557,8 @@ gfc_extend_expr (gfc_expr *e) gfc_user_op *uop; gfc_intrinsic_op i; const char *gname; + gfc_typebound_proc* tbo; + gfc_expr* tb_base; sym = NULL; @@ -3573,6 +3575,48 @@ gfc_extend_expr (gfc_expr *e) i = fold_unary_intrinsic (e->value.op.op); + /* See if we find a matching type-bound operator. */ + if (i == INTRINSIC_USER) + tbo = matching_typebound_op (&tb_base, actual, + i, e->value.op.uop->name, &gname); + else + switch (i) + { +#define CHECK_OS_COMPARISON(comp) \ + case INTRINSIC_##comp: \ + case INTRINSIC_##comp##_OS: \ + tbo = matching_typebound_op (&tb_base, actual, \ + INTRINSIC_##comp, NULL, &gname); \ + if (!tbo) \ + tbo = matching_typebound_op (&tb_base, actual, \ + INTRINSIC_##comp##_OS, NULL, &gname); \ + break; + CHECK_OS_COMPARISON(EQ) + CHECK_OS_COMPARISON(NE) + CHECK_OS_COMPARISON(GT) + CHECK_OS_COMPARISON(GE) + CHECK_OS_COMPARISON(LT) + CHECK_OS_COMPARISON(LE) +#undef CHECK_OS_COMPARISON + + default: + tbo = matching_typebound_op (&tb_base, actual, i, NULL, &gname); + break; + } + + /* If there is a matching typebound-operator, replace the expression with + a call to it and succeed. */ + if (tbo) + { + gcc_assert (tb_base); + build_compcall_for_operator (e, actual, tb_base, tbo, gname); + + if (gfc_resolve_expr (e) == FAILURE) + return MATCH_ERROR; + else + return MATCH_YES; + } + if (i == INTRINSIC_USER) { for (ns = gfc_current_ns; ns; ns = ns->parent) @@ -3623,54 +3667,6 @@ gfc_extend_expr (gfc_expr *e) if (sym == NULL) { - gfc_typebound_proc* tbo; - gfc_expr* tb_base; - - /* See if we find a matching type-bound operator. */ - if (i == INTRINSIC_USER) - tbo = matching_typebound_op (&tb_base, actual, - i, e->value.op.uop->name, &gname); - else - switch (i) - { -#define CHECK_OS_COMPARISON(comp) \ - case INTRINSIC_##comp: \ - case INTRINSIC_##comp##_OS: \ - tbo = matching_typebound_op (&tb_base, actual, \ - INTRINSIC_##comp, NULL, &gname); \ - if (!tbo) \ - tbo = matching_typebound_op (&tb_base, actual, \ - INTRINSIC_##comp##_OS, NULL, &gname); \ - break; - CHECK_OS_COMPARISON(EQ) - CHECK_OS_COMPARISON(NE) - CHECK_OS_COMPARISON(GT) - CHECK_OS_COMPARISON(GE) - CHECK_OS_COMPARISON(LT) - CHECK_OS_COMPARISON(LE) -#undef CHECK_OS_COMPARISON - - default: - tbo = matching_typebound_op (&tb_base, actual, i, NULL, &gname); - break; - } - - /* If there is a matching typebound-operator, replace the expression with - a call to it and succeed. */ - if (tbo) - { - gfc_try result; - - gcc_assert (tb_base); - build_compcall_for_operator (e, actual, tb_base, tbo, gname); - - result = gfc_resolve_expr (e); - if (result == FAILURE) - return MATCH_ERROR; - - return MATCH_YES; - } - /* Don't use gfc_free_actual_arglist(). */ free (actual->next); free (actual); diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c index 43eb240245e..bfb17cdf43e 100644 --- a/gcc/fortran/resolve.c +++ b/gcc/fortran/resolve.c @@ -6048,7 +6048,7 @@ success: /* Resolve a call to a type-bound subroutine. */ static gfc_try -resolve_typebound_call (gfc_code* c, const char **name) +resolve_typebound_call (gfc_code* c, const char **name, bool *overridable) { gfc_actual_arglist* newactual; gfc_symtree* target; @@ -6072,6 +6072,10 @@ resolve_typebound_call (gfc_code* c, const char **name) if (resolve_typebound_generic_call (c->expr1, name) == FAILURE) return FAILURE; + /* Pass along the NON_OVERRIDABLE attribute of the specific TBP. */ + if (overridable) + *overridable = !c->expr1->value.compcall.tbp->non_overridable; + /* Transform into an ordinary EXEC_CALL for now. */ if (resolve_typebound_static (c->expr1, &target, &newactual) == FAILURE) @@ -6324,7 +6328,7 @@ resolve_typebound_subroutine (gfc_code *code) if (c->ts.u.derived == NULL) c->ts.u.derived = gfc_find_derived_vtab (declared); - if (resolve_typebound_call (code, &name) == FAILURE) + if (resolve_typebound_call (code, &name, NULL) == FAILURE) return FAILURE; /* Use the generic name if it is there. */ @@ -6356,7 +6360,7 @@ resolve_typebound_subroutine (gfc_code *code) } if (st == NULL) - return resolve_typebound_call (code, NULL); + return resolve_typebound_call (code, NULL, NULL); if (resolve_ref (code->expr1) == FAILURE) return FAILURE; @@ -6369,10 +6373,10 @@ resolve_typebound_subroutine (gfc_code *code) || (!class_ref && st->n.sym->ts.type != BT_CLASS)) { gfc_free_ref_list (new_ref); - return resolve_typebound_call (code, NULL); + return resolve_typebound_call (code, NULL, NULL); } - if (resolve_typebound_call (code, &name) == FAILURE) + if (resolve_typebound_call (code, &name, &overridable) == FAILURE) { gfc_free_ref_list (new_ref); return FAILURE; diff --git a/gcc/fortran/trans-array.c b/gcc/fortran/trans-array.c index 8da24a2578f..00b1c36e747 100644 --- a/gcc/fortran/trans-array.c +++ b/gcc/fortran/trans-array.c @@ -4299,11 +4299,20 @@ gfc_conv_resolve_dependencies (gfc_loopinfo * loop, gfc_ss * dest, for (ss = rss; ss != gfc_ss_terminator; ss = ss->next) { - if (ss->info->type != GFC_SS_SECTION) - continue; ss_expr = ss->info->expr; + if (ss->info->type != GFC_SS_SECTION) + { + /* Check for cases like c(:)(1:2) = c(2)(2:3) */ + if (!nDepend && dest_expr->rank > 0 + && dest_expr->ts.type == BT_CHARACTER + && ss_expr->expr_type == EXPR_VARIABLE) + + nDepend = gfc_check_dependency (dest_expr, ss_expr, false); + continue; + } + if (dest_expr->symtree->n.sym != ss_expr->symtree->n.sym) { if (gfc_could_be_alias (dest, ss) diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c index b4b0fc536b0..b473d660e73 100644 --- a/gcc/fortran/trans-decl.c +++ b/gcc/fortran/trans-decl.c @@ -2186,8 +2186,9 @@ create_function_arglist (gfc_symbol * sym) /* Fill in arg stuff. */ DECL_CONTEXT (parm) = fndecl; DECL_ARG_TYPE (parm) = TREE_VALUE (typelist); - /* All implementation args are read-only. */ - TREE_READONLY (parm) = 1; + /* All implementation args except for VALUE are read-only. */ + if (!f->sym->attr.value) + TREE_READONLY (parm) = 1; if (POINTER_TYPE_P (type) && (!f->sym->attr.proc_pointer && f->sym->attr.flavor != FL_PROCEDURE)) diff --git a/gcc/fortran/trans-openmp.c b/gcc/fortran/trans-openmp.c index 53a78f08875..7076e3bef15 100644 --- a/gcc/fortran/trans-openmp.c +++ b/gcc/fortran/trans-openmp.c @@ -1227,6 +1227,18 @@ gfc_trans_omp_atomic (gfc_code *code) } lhsaddr = save_expr (lhsaddr); + if (TREE_CODE (lhsaddr) != SAVE_EXPR + && (TREE_CODE (lhsaddr) != ADDR_EXPR + || TREE_CODE (TREE_OPERAND (lhsaddr, 0)) != VAR_DECL)) + { + /* Make sure LHS is simple enough so that goa_lhs_expr_p can recognize + it even after unsharing function body. */ + tree var = create_tmp_var_raw (TREE_TYPE (lhsaddr), NULL); + DECL_CONTEXT (var) = current_function_decl; + lhsaddr = build4 (TARGET_EXPR, TREE_TYPE (lhsaddr), var, lhsaddr, + NULL_TREE, NULL_TREE); + } + rhs = gfc_evaluate_now (rse.expr, &block); if (atomic_code->ext.omp_atomic == GFC_OMP_ATOMIC_WRITE) diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog index e5860d7ffca..cca8539e4b8 100644 --- a/gcc/go/ChangeLog +++ b/gcc/go/ChangeLog @@ -1,3 +1,7 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/graphite-clast-to-gimple.c b/gcc/graphite-clast-to-gimple.c index 58a69ed0b4b..30d42c4b70d 100644 --- a/gcc/graphite-clast-to-gimple.c +++ b/gcc/graphite-clast-to-gimple.c @@ -30,6 +30,11 @@ along with GCC; see the file COPYING3. If not see #include <isl/aff.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/lp.h> +#include <isl/deprecated/ilp_int.h> +#endif #endif #include "system.h" diff --git a/gcc/graphite-interchange.c b/gcc/graphite-interchange.c index 05147e18ab5..3ec4069b9da 100644 --- a/gcc/graphite-interchange.c +++ b/gcc/graphite-interchange.c @@ -31,6 +31,12 @@ along with GCC; see the file COPYING3. If not see #include <isl/ilp.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/aff_int.h> +#include <isl/deprecated/ilp_int.h> +#include <isl/deprecated/constraint_int.h> +#endif #endif #include "system.h" diff --git a/gcc/graphite-optimize-isl.c b/gcc/graphite-optimize-isl.c index b6e31c7ed59..6a94cbdf88c 100644 --- a/gcc/graphite-optimize-isl.c +++ b/gcc/graphite-optimize-isl.c @@ -28,6 +28,10 @@ along with GCC; see the file COPYING3. If not see #include <isl/band.h> #include <isl/aff.h> #include <isl/options.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/aff_int.h> +#endif #endif #include "system.h" @@ -365,7 +369,11 @@ getScheduleForBandList(isl_band_list *BandList) { for (i = ScheduleDimensions - 1 ; i >= 0 ; i--) { +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE + if (isl_band_member_is_coincident (Band, i)) +#else if (isl_band_member_is_zero_distance(Band, i)) +#endif { isl_map *TileMap; isl_union_map *TileUMap; diff --git a/gcc/graphite-poly.c b/gcc/graphite-poly.c index c44791ca592..7e95255e87b 100644 --- a/gcc/graphite-poly.c +++ b/gcc/graphite-poly.c @@ -30,6 +30,10 @@ along with GCC; see the file COPYING3. If not see #include <isl/aff.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/ilp_int.h> +#endif #endif #include "system.h" diff --git a/gcc/graphite-sese-to-poly.c b/gcc/graphite-sese-to-poly.c index 34057e948da..f0a17208749 100644 --- a/gcc/graphite-sese-to-poly.c +++ b/gcc/graphite-sese-to-poly.c @@ -29,6 +29,11 @@ along with GCC; see the file COPYING3. If not see #include <cloog/cloog.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/aff_int.h> +#include <isl/deprecated/constraint_int.h> +#endif #endif #include "system.h" diff --git a/gcc/ipa-pure-const.c b/gcc/ipa-pure-const.c index bedc28a8c39..e3c4b6aee32 100644 --- a/gcc/ipa-pure-const.c +++ b/gcc/ipa-pure-const.c @@ -1429,7 +1429,7 @@ propagate_nothrow (void) else if (e->can_throw_external && !TREE_NOTHROW (y->symbol.decl)) can_throw = true; } - for (ie = node->indirect_calls; ie; ie = ie->next_callee) + for (ie = w->indirect_calls; ie; ie = ie->next_callee) if (ie->can_throw_external) can_throw = true; w_info = (struct ipa_dfs_info *) w->symbol.aux; diff --git a/gcc/java/ChangeLog b/gcc/java/ChangeLog index aa2b556f142..3f9949299fa 100644 --- a/gcc/java/ChangeLog +++ b/gcc/java/ChangeLog @@ -1,3 +1,7 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/jump.c b/gcc/jump.c index 54d98605dfc..8a0b5811b5c 100644 --- a/gcc/jump.c +++ b/gcc/jump.c @@ -133,7 +133,30 @@ cleanup_barriers (void) if (BARRIER_P (prev)) delete_insn (insn); else if (prev != PREV_INSN (insn)) - reorder_insns (insn, insn, prev); + { + basic_block bb = BLOCK_FOR_INSN (prev); + rtx end = PREV_INSN (insn); + reorder_insns_nobb (insn, insn, prev); + if (bb) + { + /* If the backend called in machine reorg compute_bb_for_insn + and didn't free_bb_for_insn again, preserve basic block + boundaries. Move the end of basic block to PREV since + it is followed by a barrier now, and clear BLOCK_FOR_INSN + on the following notes. + ??? Maybe the proper solution for the targets that have + cfg around after machine reorg is not to run cleanup_barriers + pass at all. */ + BB_END (bb) = prev; + do + { + prev = NEXT_INSN (prev); + if (prev != insn && BLOCK_FOR_INSN (prev) == bb) + BLOCK_FOR_INSN (prev) = NULL; + } + while (prev != end); + } + } } } return 0; diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog index c5d55780e85..b3cb2f505bf 100644 --- a/gcc/lto/ChangeLog +++ b/gcc/lto/ChangeLog @@ -1,3 +1,7 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/objc/ChangeLog b/gcc/objc/ChangeLog index c30ff747919..befc2a16eaf 100644 --- a/gcc/objc/ChangeLog +++ b/gcc/objc/ChangeLog @@ -1,3 +1,7 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/objcp/ChangeLog b/gcc/objcp/ChangeLog index bc73f613129..835702b9aed 100644 --- a/gcc/objcp/ChangeLog +++ b/gcc/objcp/ChangeLog @@ -1,3 +1,7 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/omp-low.c b/gcc/omp-low.c index 49fadc3a699..fc7c9910168 100644 --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -128,6 +128,7 @@ static splay_tree all_contexts; static int taskreg_nesting_level; struct omp_region *root_omp_region; static bitmap task_shared_vars; +static vec<omp_context *> taskreg_contexts; static void scan_omp (gimple_seq *, omp_context *); static tree scan_omp_1_op (tree *, int *, void *); @@ -1655,6 +1656,7 @@ scan_omp_parallel (gimple_stmt_iterator *gsi, omp_context *outer_ctx) } ctx = new_omp_context (stmt, outer_ctx); + taskreg_contexts.safe_push (ctx); if (taskreg_nesting_level > 1) ctx->is_nested = true; ctx->field_map = splay_tree_new (splay_tree_compare_pointers, 0, 0); @@ -1674,11 +1676,6 @@ scan_omp_parallel (gimple_stmt_iterator *gsi, omp_context *outer_ctx) if (TYPE_FIELDS (ctx->record_type) == NULL) ctx->record_type = ctx->receiver_decl = NULL; - else - { - layout_type (ctx->record_type); - fixup_child_record_type (ctx); - } } /* Scan an OpenMP task directive. */ @@ -1689,7 +1686,6 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) omp_context *ctx; tree name, t; gimple stmt = gsi_stmt (*gsi); - location_t loc = gimple_location (stmt); /* Ignore task directives with empty bodies. */ if (optimize > 0 @@ -1700,6 +1696,7 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) } ctx = new_omp_context (stmt, outer_ctx); + taskreg_contexts.safe_push (ctx); if (taskreg_nesting_level > 1) ctx->is_nested = true; ctx->field_map = splay_tree_new (splay_tree_compare_pointers, 0, 0); @@ -1737,8 +1734,71 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) t = build_int_cst (long_integer_type_node, 1); gimple_omp_task_set_arg_align (stmt, t); } +} + + +/* If any decls have been made addressable during scan_omp, + adjust their fields if needed, and layout record types + of parallel/task constructs. */ + +static void +finish_taskreg_scan (omp_context *ctx) +{ + if (ctx->record_type == NULL_TREE) + return; + + /* If any task_shared_vars were needed, verify all + OMP_CLAUSE_SHARED clauses on GIMPLE_OMP_{PARALLEL,TASK} + statements if use_pointer_for_field hasn't changed + because of that. If it did, update field types now. */ + if (task_shared_vars) + { + tree c; + + for (c = gimple_omp_taskreg_clauses (ctx->stmt); + c; c = OMP_CLAUSE_CHAIN (c)) + if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_SHARED) + { + tree decl = OMP_CLAUSE_DECL (c); + + /* Global variables don't need to be copied, + the receiver side will use them directly. */ + if (is_global_var (maybe_lookup_decl_in_outer_ctx (decl, ctx))) + continue; + if (!bitmap_bit_p (task_shared_vars, DECL_UID (decl)) + || !use_pointer_for_field (decl, ctx)) + continue; + tree field = lookup_field (decl, ctx); + if (TREE_CODE (TREE_TYPE (field)) == POINTER_TYPE + && TREE_TYPE (TREE_TYPE (field)) == TREE_TYPE (decl)) + continue; + TREE_TYPE (field) = build_pointer_type (TREE_TYPE (decl)); + TREE_THIS_VOLATILE (field) = 0; + DECL_USER_ALIGN (field) = 0; + DECL_ALIGN (field) = TYPE_ALIGN (TREE_TYPE (field)); + if (TYPE_ALIGN (ctx->record_type) < DECL_ALIGN (field)) + TYPE_ALIGN (ctx->record_type) = DECL_ALIGN (field); + if (ctx->srecord_type) + { + tree sfield = lookup_sfield (decl, ctx); + TREE_TYPE (sfield) = TREE_TYPE (field); + TREE_THIS_VOLATILE (sfield) = 0; + DECL_USER_ALIGN (sfield) = 0; + DECL_ALIGN (sfield) = DECL_ALIGN (field); + if (TYPE_ALIGN (ctx->srecord_type) < DECL_ALIGN (sfield)) + TYPE_ALIGN (ctx->srecord_type) = DECL_ALIGN (sfield); + } + } + } + + if (gimple_code (ctx->stmt) == GIMPLE_OMP_PARALLEL) + { + layout_type (ctx->record_type); + fixup_child_record_type (ctx); + } else { + location_t loc = gimple_location (ctx->stmt); tree *p, vla_fields = NULL_TREE, *q = &vla_fields; /* Move VLA fields to the end. */ p = &TYPE_FIELDS (ctx->record_type); @@ -1758,12 +1818,12 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) fixup_child_record_type (ctx); if (ctx->srecord_type) layout_type (ctx->srecord_type); - t = fold_convert_loc (loc, long_integer_type_node, - TYPE_SIZE_UNIT (ctx->record_type)); - gimple_omp_task_set_arg_size (stmt, t); + tree t = fold_convert_loc (loc, long_integer_type_node, + TYPE_SIZE_UNIT (ctx->record_type)); + gimple_omp_task_set_arg_size (ctx->stmt, t); t = build_int_cst (long_integer_type_node, TYPE_ALIGN_UNIT (ctx->record_type)); - gimple_omp_task_set_arg_align (stmt, t); + gimple_omp_task_set_arg_align (ctx->stmt, t); } } @@ -7112,6 +7172,8 @@ static unsigned int execute_lower_omp (void) { gimple_seq body; + int i; + omp_context *ctx; /* This pass always runs, to provide PROP_gimple_lomp. But there is nothing to do unless -fopenmp is given. */ @@ -7124,6 +7186,9 @@ execute_lower_omp (void) body = gimple_body (current_function_decl); scan_omp (&body, NULL); gcc_assert (taskreg_nesting_level == 0); + FOR_EACH_VEC_ELT (taskreg_contexts, i, ctx) + finish_taskreg_scan (ctx); + taskreg_contexts.release (); if (all_contexts->root) { diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index 951c15d2f3a..d0ff21dc958 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2014-12-19 Release Manager + + * GCC 4.8.4 released. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/ree.c b/gcc/ree.c index ff96df8a016..c7e106f9626 100644 --- a/gcc/ree.c +++ b/gcc/ree.c @@ -261,6 +261,50 @@ typedef struct ext_cand static int max_insn_uid; +/* Update or remove REG_EQUAL or REG_EQUIV notes for INSN. */ + +static bool +update_reg_equal_equiv_notes (rtx insn, enum machine_mode new_mode, + enum machine_mode old_mode, enum rtx_code code) +{ + rtx *loc = ®_NOTES (insn); + while (*loc) + { + enum reg_note kind = REG_NOTE_KIND (*loc); + if (kind == REG_EQUAL || kind == REG_EQUIV) + { + rtx orig_src = XEXP (*loc, 0); + /* Update equivalency constants. Recall that RTL constants are + sign-extended. */ + if (GET_CODE (orig_src) == CONST_INT + && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (new_mode)) + { + if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND) + /* Nothing needed. */; + else + { + /* Zero-extend the negative constant by masking out the + bits outside the source mode. */ + rtx new_const_int + = gen_int_mode (INTVAL (orig_src) + & GET_MODE_MASK (old_mode), + new_mode); + if (!validate_change (insn, &XEXP (*loc, 0), + new_const_int, true)) + return false; + } + loc = &XEXP (*loc, 1); + } + /* Drop all other notes, they assume a wrong mode. */ + else if (!validate_change (insn, loc, XEXP (*loc, 1), true)) + return false; + } + else + loc = &XEXP (*loc, 1); + } + return true; +} + /* Given a insn (CURR_INSN), an extension candidate for removal (CAND) and a pointer to the SET rtx (ORIG_SET) that needs to be modified, this code modifies the SET rtx to a new SET rtx that extends the @@ -282,6 +326,7 @@ static bool combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) { rtx orig_src = SET_SRC (*orig_set); + enum machine_mode orig_mode = GET_MODE (SET_DEST (*orig_set)); rtx new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (*orig_set))); rtx new_set; @@ -296,9 +341,8 @@ combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) { /* Zero-extend the negative constant by masking out the bits outside the source mode. */ - enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set)); rtx new_const_int - = GEN_INT (INTVAL (orig_src) & GET_MODE_MASK (src_mode)); + = GEN_INT (INTVAL (orig_src) & GET_MODE_MASK (orig_mode)); new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int); } } @@ -336,7 +380,9 @@ combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) /* This change is a part of a group of changes. Hence, validate_change will not try to commit the change. */ - if (validate_change (curr_insn, orig_set, new_set, true)) + if (validate_change (curr_insn, orig_set, new_set, true) + && update_reg_equal_equiv_notes (curr_insn, cand->mode, orig_mode, + cand->code)) { if (dump_file) { @@ -385,7 +431,9 @@ transform_ifelse (ext_cand *cand, rtx def_insn) ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2); new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr); - if (validate_change (def_insn, &PATTERN (def_insn), new_set, true)) + if (validate_change (def_insn, &PATTERN (def_insn), new_set, true) + && update_reg_equal_equiv_notes (def_insn, cand->mode, GET_MODE (dstreg), + cand->code)) { if (dump_file) { diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index b37df5b6618..395392706ef 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -873,6 +873,17 @@ reg_set_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn) int reg_set_p (const_rtx reg, const_rtx insn) { + /* After delay slot handling, call and branch insns might be in a + sequence. Check all the elements there. */ + if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) + { + for (int i = 0; i < XVECLEN (PATTERN (insn), 0); ++i) + if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i))) + return true; + + return false; + } + /* We can be passed an insn or part of one. If we are passed an insn, check if a side-effect of the insn clobbers REG. */ if (INSN_P (insn) @@ -884,7 +895,7 @@ reg_set_p (const_rtx reg, const_rtx insn) GET_MODE (reg), REGNO (reg))) || MEM_P (reg) || find_reg_fusage (insn, CLOBBER, reg))))) - return 1; + return true; return set_of (reg, insn) != NULL_RTX; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3b05295c12b..a3d4b249ddd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,250 @@ +2015-02-04 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2015-01-31 Uros Bizjak <ubizjak@gmail.com> + + PR target/64882 + * gcc.dg/torture/pr64882.c: New test. + +2015-02-01 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2015-01-27 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/61058 + * gcc.dg/pr61058.c: New test. + + PR c/64766 + * gcc.dg/pr64766.c: New test. + + 2015-01-13 Jakub Jelinek <jakub@redhat.com> + + PR fortran/64528 + * gfortran.dg/pr64528.f90: New test. + + 2015-01-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/64563 + * gcc.dg/pr64563.c: New test. + + PR target/64513 + * gcc.target/i386/pr64513.c: New test. + +2015-01-29 Ilya Tocar <ilya.tocar@intel.com> + + * gcc.target/i386/sse-14.c: Test new intrinsic. + * gcc.target/i386/sse-22.c: Ditto. + +2015-01-27 Mikael Pettersson <mikpelinux@gmail.com> + + Backport from mainline + + 2013-09-20 Bernd Edlinger <bernd.edlinger@hotmail.de> + + PR middle-end/57748 + * gcc.dg/torture/pr57748-1.c: New test. + * gcc.dg/torture/pr57748-2.c: New test. + + 2014-01-08 Bernd Edlinger <bernd.edlinger@hotmail.de> + + PR middle-end/57748 + * gcc.dg/torture/pr57748-3.c: New test. + * gcc.dg/torture/pr57748-4.c: New test. + +2015-01-24 Thomas Koenig <tkoenig@gcc.gnu.org> + + PR fortran/56867 + * gfortran.dg/dependency_45.f90: New test. + +2015-01-24 Thomas Koenig <tkoenig@netcologne.de> + + Backport from trunk + PR fortran/57023 + * gfortran.dg/internal_pack_15.f90: New test. + +2015-01-20 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-06-23 Marek Polacek <polacek@redhat.com> + + PR c/61553 + * c-c++-common/pr61553.c: New test. + +2015-01-12 Janus Weil <janus@gcc.gnu.org> + + Backport from mainline + PR fortran/63733 + * gfortran.dg/typebound_operator_20.f90: New. + +2014-12-28 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline: + 2014-12-28 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr57003.c: Skip on x32. + * gcc.target/i386/pr60516.c: Likewise. + +2014-12-27 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline: + 2014-12-26 H.J. Lu <hongjiu.lu@intel.com> + + PR target/64409 + * gcc.target/i386/pr64409.c: New test. + +2014-12-23 Janus Weil <janus@gcc.gnu.org> + + Backport from mainline + PR fortran/64244 + * gfortran.dg/typebound_call_26.f90: New. + +2014-12-19 H.J. Lu <hongjiu.lu@intel.com> + + Backported from mainline + 2014-12-14 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * g++.dg/pr64037.C: New test. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-12-18 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + Backport from trunk. + PR fortran/61407 + * gcc.dg/darwin-minversion-1.c: Fixed formatting + * gcc.dg/darwin-minversion-2.c: Fixed formatting + * gcc.dg/darwin-minversion-3.c: Fixed formatting + * gcc.dg/darwin-minversion-4.c: Added test for OS X 10.10 + +2014-12-15 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/58624 + Backported from mainline + 2014-03-07 Jason Merrill <jason@redhat.com> + + * g++.dg/plugin/plugin.exp (DEFAULT_CXXFLAGS): Remove -ansi. + +2014-12-13 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-12-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/64269 + * gcc.c-torture/compile/pr64269.c: New test. + +2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2014-09-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/builtins-1.c: Add tests for vec_ctf, + vec_cts, and vec_ctu. + * gcc.target/powerpc/builtins-2.c: Likewise. + + Backport from mainline + 2014-08-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/builtins-1.c: Add tests for vec_xl, vec_xst, + vec_round, vec_splat, vec_div, and vec_mul. + * gcc.target/powerpc/builtins-2.c: New test. + + Backport from mainline + 2014-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * testsuite/gcc.target/powerpc/builtins-1.c: New test. + +2014-12-09 Uros Bizjak <ubizjak@gmail.com> + + PR bootstrap/64213 + Revert: + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * g++.dg/pr64037.C: New test. + +2014-12-05 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * g++.dg/pr64037.C: New test. + +2014-12-04 Jakub Jelinek <jakub@redhat.com> + + PR c++/56493 + * c-c++-common/pr56493.c: New test. + +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-27 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/64067 + * gcc.c-torture/compile/pr64067.c: New test. + + 2014-10-31 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/63659 + * gcc.c-torture/execute/pr63659.c: New test. + + 2014-10-03 Jakub Jelinek <jakub@redhat.com> + + PR libgomp/61200 + * c-c++-common/gomp/pr61200.c: New test. + +2014-11-26 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-08-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62031 + * gcc.dg/torture/pr62031.c: New testcase. + + 2014-10-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63379 + * gcc.dg/vect/pr63379.c: New testcase. + + 2014-11-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63605 + * gcc.dg/vect/pr63605.c: New testcase. + + 2014-10-28 Richard Biener <rguenther@suse.de> + + PR middle-end/63665 + * gcc.dg/pr63665.c: New testcase. + +2014-11-19 Uros Bizjak <ubizjak@gmail.com> + + PR target/63947 + * gcc.target/i386/pr63947.c: New test. + +2014-11-19 Tom de Vries <tom@codesourcery.com> + + Backport from mainline + PR tree-optimization/62167 + * gcc.dg/pr51879-12.c: Add xfails. + * gcc.dg/pr62167-run.c: New test. + * gcc.dg/pr62167.c: New test. + +2014-11-18 Teresa Johnson <tejohnson@google.com> + + Backport from mainline and gcc-4_9 branch. + 2014-11-13 Teresa Johnson <tejohnson@google.com> + + PR tree-optimization/63841 + * g++.dg/tree-ssa/pr63841.C: New test. + +2014-11-12 Jakub Jelinek <jakub@redhat.com> + + PR ipa/63838 + * g++.dg/ipa/pr63838.C: New test. + 2014-11-03 Marek Polacek <polacek@redhat.com> PR c/52769 diff --git a/gcc/testsuite/c-c++-common/gomp/pr61200.c b/gcc/testsuite/c-c++-common/gomp/pr61200.c new file mode 100644 index 00000000000..d0d699dfa0b --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/pr61200.c @@ -0,0 +1,13 @@ +/* PR libgomp/61200 */ + +int +main () +{ + int var = 1; + #pragma omp parallel + if (var != 1) + __builtin_abort (); + #pragma omp task shared(var) + var = 2; + return 0; +} diff --git a/gcc/testsuite/c-c++-common/pr56493.c b/gcc/testsuite/c-c++-common/pr56493.c new file mode 100644 index 00000000000..4181260430f --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr56493.c @@ -0,0 +1,16 @@ +/* PR c++/56493 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple" } */ + +unsigned long long bar (void); +int x; + +void +foo (void) +{ + x += bar (); +} + +/* Verify we narrow the addition from unsigned long long to unsigned int type. */ +/* { dg-final { scan-tree-dump " (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* = \\1 \\+ \\2;" "gimple" { target { ilp32 || lp64 } } } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/c-c++-common/pr61553.c b/gcc/testsuite/c-c++-common/pr61553.c new file mode 100644 index 00000000000..8a3b699ee70 --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr61553.c @@ -0,0 +1,8 @@ +/* PR c/61553 */ +/* { dg-do compile } */ + +void +foo (char *s) +{ + __atomic_store (s, (void *) 0, __ATOMIC_SEQ_CST); /* { dg-error "size mismatch" } */ +} diff --git a/gcc/testsuite/g++.dg/cpp0x/ref-qual16.C b/gcc/testsuite/g++.dg/cpp0x/ref-qual16.C new file mode 100644 index 00000000000..1d7650bb61b --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/ref-qual16.C @@ -0,0 +1,12 @@ +// PR c++/64297 +// { dg-do compile { target c++11 } } + +struct A { + typedef int X; + template <int> X m_fn1() const; +}; +template <typename> struct is_function {}; +is_function<int() const &> i; +struct D { + template <typename Y, typename = is_function<Y>> D(Y); +} b(&A::m_fn1<0>); diff --git a/gcc/testsuite/g++.dg/ipa/pr63838.C b/gcc/testsuite/g++.dg/ipa/pr63838.C new file mode 100644 index 00000000000..d6736490080 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr63838.C @@ -0,0 +1,56 @@ +// PR ipa/63838 +// { dg-do run } +// { dg-options "-O2 -fdump-ipa-pure-const" } +// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void foo" "pure-const" } } +// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void bar" "pure-const" } } +// { dg-final { cleanup-ipa-dump "pure-const" } } + +__attribute__((noinline, noclone)) static void bar (int); +volatile int v; +void (*fn) (); +struct S { S () { v++; } ~S () { v++; } }; + +__attribute__((noinline, noclone)) static void +foo (int x) +{ + v++; + if (x == 5) + bar (x); +} + +__attribute__((noinline, noclone)) static void +bar (int x) +{ + v++; + if (x == 6) + foo (x); + else if (x == 5) + fn (); +} + +__attribute__((noinline, noclone)) int +baz (int x) +{ + S s; + foo (x); +} + +void +throw0 () +{ + throw 0; +} + +int +main () +{ + fn = throw0; + asm volatile ("" : : : "memory"); + try + { + baz (5); + } + catch (int) + { + } +} diff --git a/gcc/testsuite/g++.dg/plugin/plugin.exp b/gcc/testsuite/g++.dg/plugin/plugin.exp index c26b8794e10..8068e49176b 100644 --- a/gcc/testsuite/g++.dg/plugin/plugin.exp +++ b/gcc/testsuite/g++.dg/plugin/plugin.exp @@ -31,7 +31,7 @@ if { ![info exists TESTING_IN_BUILD_TREE] || ![info exists ENABLE_PLUGIN] } { # If a testcase doesn't have special options, use these. global DEFAULT_CXXFLAGS if ![info exists DEFAULT_CXXFLAGS] then { - set DEFAULT_CXXFLAGS " -ansi -pedantic-errors -Wno-long-long" + set DEFAULT_CXXFLAGS " -pedantic-errors -Wno-long-long" } # The procedures in plugin-support.exp need these parameters. diff --git a/gcc/testsuite/g++.dg/pr64037.C b/gcc/testsuite/g++.dg/pr64037.C new file mode 100644 index 00000000000..e5cd0e2ee17 --- /dev/null +++ b/gcc/testsuite/g++.dg/pr64037.C @@ -0,0 +1,27 @@ +// { dg-do run { target i?86-*-* x86_64-*-* } } +// { dg-options "-std=c++11 -Os" } + +enum class X : unsigned char { + V = 2, +}; + +static void +__attribute__((noinline,noclone)) +foo(unsigned &out, unsigned a, X b) +{ + out = static_cast<unsigned>(b); +} + +int main() +{ + unsigned deadbeef = 0xDEADBEEF; + asm volatile ("" : "+d" (deadbeef), "+c" (deadbeef)); + + unsigned out; + foo(out, 2, X::V); + + if (out != 2) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/g++.dg/template/non-dependent14.C b/gcc/testsuite/g++.dg/template/non-dependent14.C new file mode 100644 index 00000000000..b257d9baf1a --- /dev/null +++ b/gcc/testsuite/g++.dg/template/non-dependent14.C @@ -0,0 +1,7 @@ +// PR c++/64251 + +class DictionaryValue {}; +template <typename T> void CreateValue(T) { + DictionaryValue(0); + CreateValue(0); +} diff --git a/gcc/testsuite/g++.dg/template/offsetof3.C b/gcc/testsuite/g++.dg/template/offsetof3.C new file mode 100644 index 00000000000..b17374645b2 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/offsetof3.C @@ -0,0 +1,18 @@ +// PR c++/64487 + +struct foo { + int member; +}; + +template < int N> +struct bar {}; + +template <int N> +struct qux { + static bar<N+__builtin_offsetof(foo,member)> static_member; +}; + +template <int N> +bar<N+__builtin_offsetof(foo,member)> qux<N>::static_member; + +int main() { } diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr63841.C b/gcc/testsuite/g++.dg/tree-ssa/pr63841.C new file mode 100644 index 00000000000..2a2c78f9fb2 --- /dev/null +++ b/gcc/testsuite/g++.dg/tree-ssa/pr63841.C @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include <string> + +std::string __attribute__ ((noinline)) comp_test_write() { + std::string data; + + for (int i = 0; i < 2; ++i) { + char b = 1 >> (i * 8); + data.append(&b, 1); + } + + return data; +} + +std::string __attribute__ ((noinline)) comp_test_write_good() { + std::string data; + + char b; + for (int i = 0; i < 2; ++i) { + b = 1 >> (i * 8); + data.append(&b, 1); + } + + return data; +} + +int main() { + std::string good = comp_test_write_good(); + std::string bad = comp_test_write(); + + if (good != bad) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr64067.c b/gcc/testsuite/gcc.c-torture/compile/pr64067.c new file mode 100644 index 00000000000..24ad996efdb --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr64067.c @@ -0,0 +1,10 @@ +/* PR middle-end/64067 */ + +struct S { int s; }; +int *const v[1] = { &((struct S) { .s = 42 }).s }; + +int * +foo (void) +{ + return v[0]; +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr64269.c b/gcc/testsuite/gcc.c-torture/compile/pr64269.c new file mode 100644 index 00000000000..640758d3fef --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr64269.c @@ -0,0 +1,9 @@ +/* PR tree-optimization/64269 */ + +void +foo (char *p) +{ + __SIZE_TYPE__ s = ~(__SIZE_TYPE__)0; + *p = 0; + __builtin_memset (p + 1, 0, s); +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr63659.c b/gcc/testsuite/gcc.c-torture/execute/pr63659.c new file mode 100644 index 00000000000..780dc8a7e21 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr63659.c @@ -0,0 +1,29 @@ +/* PR rtl-optimization/63659 */ + +int a, b, c, *d = &b, g, h, i; +unsigned char e; +char f; + +int +main () +{ + while (a) + { + for (a = 0; a; a++) + for (; c; c++) + ; + if (i) + break; + } + + char j = c, k = -1, l; + l = g = j >> h; + f = l == 0 ? k : k % l; + e = 0 ? 0 : f; + *d = e; + + if (b != 255) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-1.c b/gcc/testsuite/gcc.dg/darwin-minversion-1.c index d8a3243bb55..6221d617b2e 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-1.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-1.c @@ -2,7 +2,8 @@ /* { dg-options "-mmacosx-version-min=10.1" } */ /* { dg-do run { target *-*-darwin* } } */ -int main(void) +int +main () { #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 1010 fail me; diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-2.c b/gcc/testsuite/gcc.dg/darwin-minversion-2.c index fd4975a5292..8e18d5273a6 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-2.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-2.c @@ -2,7 +2,8 @@ /* { dg-options "-mmacosx-version-min=10.1 -mmacosx-version-min=10.3" } */ /* { dg-do run { target *-*-darwin* } } */ -int main(void) +int +main () { #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 1030 fail me; diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-3.c b/gcc/testsuite/gcc.dg/darwin-minversion-3.c index d0c5934b449..4fcb9693cd4 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-3.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-3.c @@ -2,7 +2,8 @@ /* { dg-options "-mmacosx-version-min=10.4.10" } */ /* { dg-do compile { target *-*-darwin* } } */ -int main(void) +int +main () { #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 1040 fail me; diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-4.c b/gcc/testsuite/gcc.dg/darwin-minversion-4.c new file mode 100644 index 00000000000..1cb42ebe3e9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/darwin-minversion-4.c @@ -0,0 +1,12 @@ +/* Test that major versions greater than 9 work and have the additional 0. */ +/* { dg-options "-mmacosx-version-min=10.10.0" } */ +/* { dg-do compile { target *-*-darwin* } } */ + +int +main () +{ +#if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 101000 + fail me; +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr51879-12.c b/gcc/testsuite/gcc.dg/pr51879-12.c index 1b25e296fbf..7490e33f055 100644 --- a/gcc/testsuite/gcc.dg/pr51879-12.c +++ b/gcc/testsuite/gcc.dg/pr51879-12.c @@ -24,6 +24,6 @@ foo (int y) baz (a); } -/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre"} } */ -/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre"} } */ +/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre" { xfail *-*-* } } } */ +/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre" { xfail *-*-* } } } */ /* { dg-final { cleanup-tree-dump "pre" } } */ diff --git a/gcc/testsuite/gcc.dg/pr61058.c b/gcc/testsuite/gcc.dg/pr61058.c new file mode 100644 index 00000000000..6f840f418fe --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr61058.c @@ -0,0 +1,10 @@ +/* PR rtl-optimization/61058 */ +/* { dg-do compile } */ +/* { dg-options "" } */ +/* { dg-additional-options "-fno-asynchronous-unwind-tables -mtune=atom" { target i?86-*-* x86_64-*-* } } */ + +void +foo (void) +{ + __builtin_unreachable (); +} diff --git a/gcc/testsuite/gcc.dg/pr62167-run.c b/gcc/testsuite/gcc.dg/pr62167-run.c new file mode 100644 index 00000000000..37214a3ecee --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr62167-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-tail-merge" } */ + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +int +main () +{ + struct node *p; + + node.next = (void*)0; + + node.prev = (void *)head; + + head->first = &node; + + struct node *n = head->first; + + struct head *h = &heads[k]; + + heads[2].first = n->next; + + if ((void*)n->prev == (void *)h) + p = h->first; + else + /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */ + p = n->prev->next; + + return !(p == (void*)0); +} diff --git a/gcc/testsuite/gcc.dg/pr62167.c b/gcc/testsuite/gcc.dg/pr62167.c new file mode 100644 index 00000000000..f8c31a0792f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr62167.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */ + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +int +main () +{ + struct node *p; + + node.next = (void*)0; + + node.prev = (void *)head; + + head->first = &node; + + struct node *n = head->first; + + struct head *h = &heads[k]; + + heads[2].first = n->next; + + if ((void*)n->prev == (void *)h) + p = h->first; + else + /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */ + p = n->prev->next; + + return !(p == (void*)0); +} + +/* { dg-final { scan-tree-dump-not "Removing basic block" "pre"} } */ +/* { dg-final { cleanup-tree-dump "pre" } } */ diff --git a/gcc/testsuite/gcc.dg/pr63665.c b/gcc/testsuite/gcc.dg/pr63665.c new file mode 100644 index 00000000000..046ecae7c1d --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63665.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target int32plus } */ +/* { dg-options "-O -fno-tree-ccp -fno-tree-fre -fno-tree-copy-prop -fwrapv" } */ + +static inline int +test5 (int x) +{ + int y = 0x80000000; + return x + y; +} + +int +main () +{ + if (test5 (0x80000000) != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr64563.c b/gcc/testsuite/gcc.dg/pr64563.c new file mode 100644 index 00000000000..7223349c41f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr64563.c @@ -0,0 +1,14 @@ +/* PR tree-optimization/64563 */ +/* { dg-do compile } */ +/* { dg-options "-Os -Wtype-limits" } */ + +int a, b, c, d, f; +unsigned int e; + +void +foo (void) +{ + d = b = (a != (e | 4294967288UL)); + if (!d) + c = f || b; +} diff --git a/gcc/testsuite/gcc.dg/pr64766.c b/gcc/testsuite/gcc.dg/pr64766.c new file mode 100644 index 00000000000..bf6fb2d5905 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr64766.c @@ -0,0 +1,9 @@ +/* PR c/64766 */ +/* { dg-do compile } */ + +void +foo () +{ +} + +void foo () = 0; /* { dg-error "is initialized like a variable|invalid initializer" } */ diff --git a/gcc/testsuite/gcc.dg/torture/pr62031.c b/gcc/testsuite/gcc.dg/torture/pr62031.c new file mode 100644 index 00000000000..f0dcef44b1d --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr62031.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ + +#include <stdlib.h> + +#define NUM_OF_STATES 4 +typedef unsigned int entry_t[2]; +typedef struct entries_item { entry_t metricEntries_[0]; } entries_item_t; + +void __attribute__((noinline,noclone)) +test_00(size_t numOfStates, entries_item_t* p_bm, + const unsigned int* polyArray, + size_t polyArraySize) +{ + size_t idx; + unsigned int hlp0, hlp1; + for (idx = 0; idx < numOfStates; ++idx) + { + size_t idy; + + hlp0 = (idx << 1) | 0x00; + hlp1 = (idx << 1) | 0x01; + p_bm->metricEntries_[idx][0] = 0; + p_bm->metricEntries_[idx][1] = 0; + for (idy = 0; idy < polyArraySize; ++idy) + { + p_bm->metricEntries_[idx][0] + |= __builtin_parity(hlp0 & polyArray[idy]) << idy; + p_bm->metricEntries_[idx][1] + |= __builtin_parity(hlp1 & polyArray[idy]) << idy; + } + } +} + +int main() +{ + unsigned int polyArray[] = { 0x07, 0x05 }; + entries_item_t* pBranchMetrics; + pBranchMetrics = malloc(sizeof(entry_t) * NUM_OF_STATES); + test_00(NUM_OF_STATES, pBranchMetrics, polyArray, + sizeof(polyArray) / sizeof(polyArray[0])); + if (pBranchMetrics->metricEntries_[0][0] != 0 + || pBranchMetrics->metricEntries_[0][1] != 3 + || pBranchMetrics->metricEntries_[1][0] != 1 + || pBranchMetrics->metricEntries_[1][1] != 2 + || pBranchMetrics->metricEntries_[2][0] != 3 + || pBranchMetrics->metricEntries_[2][1] != 0 + || pBranchMetrics->metricEntries_[3][0] != 2 + || pBranchMetrics->metricEntries_[3][1] != 1) + abort (); + free(pBranchMetrics); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr64882.c b/gcc/testsuite/gcc.dg/torture/pr64882.c new file mode 100644 index 00000000000..462edace1b9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr64882.c @@ -0,0 +1,33 @@ +/* PR target/64882 */ +/* { dg-do compile } */ + +int a, d, e; +long long b; +static long long *c = &b; + +void +fn1 (short p) +{ +} + +long long +fn2 (long long p1, long long p2) +{ + return (p1 && p1 > 26854775807LL - p2) || p1 < -p2 ? p1 : p1 + p2; +} + +void +fn3 () +{ + long long f; + int g = 3; + int *h = &a; + for (e = 0; e < 2; e++) + { + int *i = &g; + if (!fn2 (*c, 7 < d % (*i)--)) + f = fn2 ((*h <= 0) | b, 5278350700LL); + *h = f; + fn1 (*h); + } +} diff --git a/gcc/testsuite/gcc.dg/vect/pr63379.c b/gcc/testsuite/gcc.dg/vect/pr63379.c new file mode 100644 index 00000000000..f6e8fc6a4ce --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63379.c @@ -0,0 +1,43 @@ +/* PR tree-optimization/63379 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +extern void abort (void); + +typedef struct { + int x; + int y; +} Point; + +Point pt_array[25]; + +void __attribute__((noinline,noclone)) +generate_array(void) +{ + unsigned int i; + for (i = 0; i<25; i++) + { + pt_array[i].x = i; + pt_array[i].y = 1000+i; + } +} + +int main() +{ + check_vect (); + generate_array (); + Point min_pt = pt_array[0]; + Point *ptr, *ptr_end; + for (ptr = pt_array+1, ptr_end = pt_array+25; ptr != ptr_end; ++ptr) + { + min_pt.x = (min_pt.x < ptr->x) ? min_pt.x : ptr->x; + min_pt.y = (min_pt.y < ptr->y) ? min_pt.y : ptr->y; + } + + if (min_pt.x != 0 || min_pt.y != 1000) + abort (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63605.c b/gcc/testsuite/gcc.dg/vect/pr63605.c new file mode 100644 index 00000000000..5096c7239d8 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63605.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ + +#include "tree-vect.h" + +extern void abort (void); + +int a, b[8] = { 2, 0, 0, 0, 0, 0, 0, 0 }, c[8]; + +int +main () +{ + int d; + check_vect (); + for (; a < 8; a++) + { + d = b[a] >> 1; + c[a] = d != 0; + } + if (c[0] != 1) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr57003.c b/gcc/testsuite/gcc.target/i386/pr57003.c index 91b4f5402e6..132d18d1139 100644 --- a/gcc/testsuite/gcc.target/i386/pr57003.c +++ b/gcc/testsuite/gcc.target/i386/pr57003.c @@ -1,5 +1,5 @@ /* PR rtl-optimization/57003 */ -/* { dg-do run } */ +/* { dg-do run { target { ! x32 } } } */ /* { dg-options "-O2 -maccumulate-outgoing-args" } */ #define N 2001 diff --git a/gcc/testsuite/gcc.target/i386/pr60516.c b/gcc/testsuite/gcc.target/i386/pr60516.c index 575c8b61d1e..d7e11161c49 100644 --- a/gcc/testsuite/gcc.target/i386/pr60516.c +++ b/gcc/testsuite/gcc.target/i386/pr60516.c @@ -1,5 +1,5 @@ /* PR target/60516 */ -/* { dg-do compile } */ +/* { dg-do compile { target { ! x32 } } } */ /* { dg-options "-O2" } */ struct S { char c[65536]; }; diff --git a/gcc/testsuite/gcc.target/i386/pr63947.c b/gcc/testsuite/gcc.target/i386/pr63947.c new file mode 100644 index 00000000000..3c0a67a73ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr63947.c @@ -0,0 +1,9 @@ +/* PR target/63947 */ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-additional-options "-march=i686" { target ia32 } } */ + +long double foo (unsigned a, unsigned b) +{ + return a + b < a; +} diff --git a/gcc/testsuite/gcc.target/i386/pr64409.c b/gcc/testsuite/gcc.target/i386/pr64409.c new file mode 100644 index 00000000000..6a64b5961de --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr64409.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O0 -mx32" } */ + +int a; +int* __attribute__ ((ms_abi)) fn1 () { return &a; } /* { dg-error "X32 does not support ms_abi attribute" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr64513.c b/gcc/testsuite/gcc.target/i386/pr64513.c new file mode 100644 index 00000000000..02364960999 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr64513.c @@ -0,0 +1,17 @@ +/* PR target/64513 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mstack-arg-probe" } */ + +struct A {}; +struct B { struct A y; }; +int foo (struct A); + +int +bar (int x) +{ + struct B b; + int c; + while (x--) + c = foo (b.y); + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 331be0e1987..dc8bc9126e2 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -150,6 +150,8 @@ test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1) /* emmintrin.h */ test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1) +test_1 (_mm_bsrli_si128, __m128i, __m128i, 1) +test_1 (_mm_bslli_si128, __m128i, __m128i, 1) test_1 (_mm_srli_si128, __m128i, __m128i, 1) test_1 (_mm_slli_si128, __m128i, __m128i, 1) test_1 (_mm_extract_epi16, int, __m128i, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 8e4c4bd3ebd..f928d485c06 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -88,6 +88,8 @@ test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA) #endif #include <emmintrin.h> test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1) +test_1 (_mm_bsrli_si128, __m128i, __m128i, 1) +test_1 (_mm_bslli_si128, __m128i, __m128i, 1) test_1 (_mm_srli_si128, __m128i, __m128i, 1) test_1 (_mm_slli_si128, __m128i, __m128i, 1) test_1 (_mm_extract_epi16, int, __m128i, 1) @@ -219,6 +221,8 @@ test_2 ( _mm256_blend_epi16, __m256i, __m256i, __m256i, 1) test_1 ( _mm256_shuffle_epi32, __m256i, __m256i, 1) test_1 ( _mm256_shufflehi_epi16, __m256i, __m256i, 1) test_1 ( _mm256_shufflelo_epi16, __m256i, __m256i, 1) +test_1 ( _mm256_bslli_epi128, __m256i, __m256i, 8) +test_1 ( _mm256_bsrli_epi128, __m256i, __m256i, 8) test_1 ( _mm256_slli_si256, __m256i, __m256i, 8) test_1 ( _mm256_srli_si256, __m256i, __m256i, 8) test_2 ( _mm_blend_epi32, __m128i, __m128i, __m128i, 1) diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c new file mode 100644 index 00000000000..3da714698d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c @@ -0,0 +1,166 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-options "-mcpu=power8 -O0" } */ + +/* Test that a number of newly added builtin overloads are accepted + by the compiler. */ + +#include <altivec.h> + +vector double y = { 2.0, 4.0 }; +vector double z; + +int main () +{ + vector float fa = {1.0, 2.0, 3.0, -4.0}; + vector float fb = {-2.0, -3.0, -4.0, -5.0}; + vector float fc = vec_cpsgn (fa, fb); + + vector long long la = {5L, 14L}; + vector long long lb = {3L, 86L}; + vector long long lc = vec_and (la, lb); + vector bool long long ld = {0, -1}; + vector long long le = vec_and (la, ld); + vector long long lf = vec_and (ld, lb); + + vector unsigned long long ua = {5L, 14L}; + vector unsigned long long ub = {3L, 86L}; + vector unsigned long long uc = vec_and (ua, ub); + vector bool long long ud = {0, -1}; + vector unsigned long long ue = vec_and (ua, ud); + vector unsigned long long uf = vec_and (ud, ub); + + vector long long lg = vec_andc (la, lb); + vector long long lh = vec_andc (la, ld); + vector long long li = vec_andc (ld, lb); + + vector unsigned long long ug = vec_andc (ua, ub); + vector unsigned long long uh = vec_andc (ua, ud); + vector unsigned long long ui = vec_andc (ud, ub); + + vector double da = {1.0, -4.0}; + vector double db = {-2.0, 5.0}; + vector double dc = vec_cpsgn (da, db); + + vector long long lj = vec_mergeh (la, lb); + vector long long lk = vec_mergeh (la, ld); + vector long long ll = vec_mergeh (ld, la); + + vector unsigned long long uj = vec_mergeh (ua, ub); + vector unsigned long long uk = vec_mergeh (ua, ud); + vector unsigned long long ul = vec_mergeh (ud, ua); + + vector long long lm = vec_mergel (la, lb); + vector long long ln = vec_mergel (la, ld); + vector long long lo = vec_mergel (ld, la); + + vector unsigned long long um = vec_mergel (ua, ub); + vector unsigned long long un = vec_mergel (ua, ud); + vector unsigned long long uo = vec_mergel (ud, ua); + + vector long long lp = vec_nor (la, lb); + vector long long lq = vec_nor (la, ld); + vector long long lr = vec_nor (ld, la); + + vector unsigned long long up = vec_nor (ua, ub); + vector unsigned long long uq = vec_nor (ua, ud); + vector unsigned long long ur = vec_nor (ud, ua); + + vector long long ls = vec_or (la, lb); + vector long long lt = vec_or (la, ld); + vector long long lu = vec_or (ld, la); + + vector unsigned long long us = vec_or (ua, ub); + vector unsigned long long ut = vec_or (ua, ud); + vector unsigned long long uu = vec_or (ud, ua); + + vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13}; + vector long long lv = vec_perm (la, lb, ca); + vector unsigned long long uv = vec_perm (ua, ub, ca); + + vector long long lw = vec_sel (la, lb, lc); + vector long long lx = vec_sel (la, lb, uc); + vector long long ly = vec_sel (la, lb, ld); + + vector unsigned long long uw = vec_sel (ua, ub, lc); + vector unsigned long long ux = vec_sel (ua, ub, uc); + vector unsigned long long uy = vec_sel (ua, ub, ld); + + vector long long lz = vec_xor (la, lb); + vector long long l0 = vec_xor (la, ld); + vector long long l1 = vec_xor (ld, la); + + vector unsigned long long uz = vec_xor (ua, ub); + vector unsigned long long u0 = vec_xor (ua, ud); + vector unsigned long long u1 = vec_xor (ud, ua); + + int ia = vec_all_eq (ua, ub); + int ib = vec_all_ge (ua, ub); + int ic = vec_all_gt (ua, ub); + int id = vec_all_le (ua, ub); + int ie = vec_all_lt (ua, ub); + int ig = vec_all_ne (ua, ub); + + int ih = vec_any_eq (ua, ub); + int ii = vec_any_ge (ua, ub); + int ij = vec_any_gt (ua, ub); + int ik = vec_any_le (ua, ub); + int il = vec_any_lt (ua, ub); + int im = vec_any_ne (ua, ub); + + vector int sia = {9, 16, 25, 36}; + vector int sib = {-8, -27, -64, -125}; + vector int sic = vec_mergee (sia, sib); + vector int sid = vec_mergeo (sia, sib); + + vector unsigned int uia = {9, 16, 25, 36}; + vector unsigned int uib = {8, 27, 64, 125}; + vector unsigned int uic = vec_mergee (uia, uib); + vector unsigned int uid = vec_mergeo (uia, uib); + + vector bool int bia = {0, -1, -1, 0}; + vector bool int bib = {-1, -1, 0, -1}; + vector bool int bic = vec_mergee (bia, bib); + vector bool int bid = vec_mergeo (bia, bib); + + vector unsigned int uie = vec_packsu (ua, ub); + + vector long long l2 = vec_cntlz (la); + vector unsigned long long u2 = vec_cntlz (ua); + vector int sie = vec_cntlz (sia); + vector unsigned int uif = vec_cntlz (uia); + vector short ssa = {20, -40, -60, 80, 100, -120, -140, 160}; + vector short ssb = vec_cntlz (ssa); + vector unsigned short usa = {81, 72, 63, 54, 45, 36, 27, 18}; + vector unsigned short usb = vec_cntlz (usa); + vector signed char sca = {-4, 3, -9, 15, -31, 31, 0, 0, + 1, 117, -36, 99, 98, 97, 96, 95}; + vector signed char scb = vec_cntlz (sca); + vector unsigned char cb = vec_cntlz (ca); + + vector double dd = vec_xl (0, &y); + vec_xst (dd, 0, &z); + + vector double de = vec_round (dd); + + vector double df = vec_splat (de, 0); + vector double dg = vec_splat (de, 1); + vector long long l3 = vec_splat (l2, 0); + vector long long l4 = vec_splat (l2, 1); + vector unsigned long long u3 = vec_splat (u2, 0); + vector unsigned long long u4 = vec_splat (u2, 1); + vector bool long long l5 = vec_splat (ld, 0); + vector bool long long l6 = vec_splat (ld, 1); + + vector long long l7 = vec_div (l3, l4); + vector unsigned long long u5 = vec_div (u3, u4); + + vector long long l8 = vec_mul (l3, l4); + vector unsigned long long u6 = vec_mul (u3, u4); + + vector double dh = vec_ctf (la, -2); + vector double di = vec_ctf (ua, 2); + vector long long l9 = vec_cts (dh, -2); + vector unsigned long long u7 = vec_ctu (di, 2); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-2.c b/gcc/testsuite/gcc.target/powerpc/builtins-2.c new file mode 100644 index 00000000000..7f4a3924efd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-2.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { powerpc64le-*-* } } } */ +/* { dg-options "-mcpu=power8 " } */ + +#include <altivec.h> + +void abort (void); + +int main () +{ + vector long long sa = {27L, -14L}; + vector long long sb = {-9L, -2L}; + + vector unsigned long long ua = {27L, 14L}; + vector unsigned long long ub = {9L, 2L}; + + vector long long sc = vec_div (sa, sb); + vector unsigned long long uc = vec_div (ua, ub); + + if (sc[0] != -3L || sc[1] != 7L || uc[0] != 3L || uc[1] != 7L) + abort (); + + vector long long sd = vec_mul (sa, sb); + vector unsigned long long ud = vec_mul (ua, ub); + + if (sd[0] != -243L || sd[1] != 28L || ud[0] != 243L || ud[1] != 28L) + abort (); + + vector long long se = vec_splat (sa, 0); + vector long long sf = vec_splat (sa, 1); + vector unsigned long long ue = vec_splat (ua, 0); + vector unsigned long long uf = vec_splat (ua, 1); + + if (se[0] != 27L || se[1] != 27L || sf[0] != -14L || sf[1] != -14L + || ue[0] != 27L || ue[1] != 27L || uf[0] != 14L || uf[1] != 14L) + abort (); + + vector double da = vec_ctf (sa, -2); + vector double db = vec_ctf (ua, 2); + vector long long sg = vec_cts (da, -2); + vector unsigned long long ug = vec_ctu (db, 2); + + if (da[0] != 108.0 || da[1] != -56.0 || db[0] != 6.75 || db[1] != 3.5 + || sg[0] != 27L || sg[1] != -14L || ug[0] != 27L || ug[1] != 14L) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gfortran.dg/dependency_45.f90 b/gcc/testsuite/gfortran.dg/dependency_45.f90 new file mode 100644 index 00000000000..8b43f7507b6 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/dependency_45.f90 @@ -0,0 +1,12 @@ +! { dg-do run } +! { dg-options "-Warray-temporaries" } +! PR 56867 - substrings were not checked for dependency. +program main + character(len=4) :: a + character(len=4) :: c(3) + c(1) = 'abcd' + c(2) = '1234' + c(3) = 'wxyz' + c(:)(1:2) = c(2)(2:3) ! { dg-warning "array temporary" } + if (c(3) .ne. '23yz') call abort +end program main diff --git a/gcc/testsuite/gfortran.dg/pr64528.f90 b/gcc/testsuite/gfortran.dg/pr64528.f90 new file mode 100644 index 00000000000..f6cca4f73e0 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr64528.f90 @@ -0,0 +1,20 @@ +! PR fortran/64528 +! { dg-do compile } +! { dg-options "-O -fno-tree-dce -fno-tree-ccp" } + +program pr64528 + interface + subroutine foo(x) + integer, value :: x + end subroutine foo + end interface + integer :: x + x = 10 + call foo(x) + if(x .ne. 10) then + endif +end program pr64528 +subroutine foo(x) + integer, value :: x + x = 11 +end subroutine foo diff --git a/gcc/testsuite/gfortran.dg/typebound_call_26.f90 b/gcc/testsuite/gfortran.dg/typebound_call_26.f90 new file mode 100644 index 00000000000..dffbf93e786 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/typebound_call_26.f90 @@ -0,0 +1,30 @@ +! { dg-do compile } +! +! PR 64244: [4.8/4.9/5 Regression] ICE at class.c:236 when using non_overridable +! +! Contributed by Ondřej Čertík <ondrej.certik@gmail.com> + +module m + implicit none + + type :: A + contains + generic :: f => g + procedure, non_overridable :: g + end type + +contains + + subroutine g(this) + class(A), intent(in) :: this + end subroutine + +end module + + +program test_non_overridable + use m, only: A + implicit none + class(A), allocatable :: h + call h%f() +end diff --git a/gcc/testsuite/gfortran.dg/typebound_operator_20.f90 b/gcc/testsuite/gfortran.dg/typebound_operator_20.f90 new file mode 100644 index 00000000000..26c49a188eb --- /dev/null +++ b/gcc/testsuite/gfortran.dg/typebound_operator_20.f90 @@ -0,0 +1,53 @@ +! { dg-do run } +! +! PR 63733: [4.8/4.9/5 Regression] [OOP] wrong resolution for OPERATOR generics +! +! Original test case from Alberto F. Martín Huertas <amartin@cimne.upc.edu> +! Slightly modified by Salvatore Filippone <sfilippone@uniroma2.it> +! Further modified by Janus Weil <janus@gcc.gnu.org> + +module overwrite + type parent + contains + procedure :: sum => sum_parent + generic :: operator(+) => sum + end type + + type, extends(parent) :: child + contains + procedure :: sum => sum_child + end type + +contains + + integer function sum_parent(op1,op2) + implicit none + class(parent), intent(in) :: op1, op2 + sum_parent = 0 + end function + + integer function sum_child(op1,op2) + implicit none + class(child) , intent(in) :: op1 + class(parent), intent(in) :: op2 + sum_child = 1 + end function + +end module + +program drive + use overwrite + implicit none + + type(parent) :: m1, m2 + class(parent), pointer :: mres + type(child) :: h1, h2 + class(parent), pointer :: hres + + if (m1 + m2 /= 0) call abort() + if (h1 + m2 /= 1) call abort() + if (h1%sum(h2) /= 1) call abort() + +end + +! { dg-final { cleanup-modules "overwrite" } } diff --git a/gcc/tree-data-ref.c b/gcc/tree-data-ref.c index ebb7f306f7f..8392e9568de 100644 --- a/gcc/tree-data-ref.c +++ b/gcc/tree-data-ref.c @@ -919,7 +919,6 @@ dr_analyze_indices (struct data_reference *dr, loop_p nest, loop_p loop) ref = fold_build2_loc (EXPR_LOCATION (ref), MEM_REF, TREE_TYPE (ref), base, memoff); - DR_UNCONSTRAINED_BASE (dr) = true; access_fns.safe_push (access_fn); } } @@ -1326,14 +1325,20 @@ dr_may_alias_p (const struct data_reference *a, const struct data_reference *b, return false; } - /* If we had an evolution in a MEM_REF BASE_OBJECT we do not know - the size of the base-object. So we cannot do any offset/overlap - based analysis but have to rely on points-to information only. */ + /* If we had an evolution in a pointer-based MEM_REF BASE_OBJECT we + do not know the size of the base-object. So we cannot do any + offset/overlap based analysis but have to rely on points-to + information only. */ if (TREE_CODE (addr_a) == MEM_REF - && DR_UNCONSTRAINED_BASE (a)) + && TREE_CODE (TREE_OPERAND (addr_a, 0)) == SSA_NAME) { - if (TREE_CODE (addr_b) == MEM_REF - && DR_UNCONSTRAINED_BASE (b)) + /* For true dependences we can apply TBAA. */ + if (flag_strict_aliasing + && DR_IS_WRITE (a) && DR_IS_READ (b) + && !alias_sets_conflict_p (get_alias_set (DR_REF (a)), + get_alias_set (DR_REF (b)))) + return false; + if (TREE_CODE (addr_b) == MEM_REF) return ptr_derefs_may_alias_p (TREE_OPERAND (addr_a, 0), TREE_OPERAND (addr_b, 0)); else @@ -1341,9 +1346,21 @@ dr_may_alias_p (const struct data_reference *a, const struct data_reference *b, build_fold_addr_expr (addr_b)); } else if (TREE_CODE (addr_b) == MEM_REF - && DR_UNCONSTRAINED_BASE (b)) - return ptr_derefs_may_alias_p (build_fold_addr_expr (addr_a), - TREE_OPERAND (addr_b, 0)); + && TREE_CODE (TREE_OPERAND (addr_b, 0)) == SSA_NAME) + { + /* For true dependences we can apply TBAA. */ + if (flag_strict_aliasing + && DR_IS_WRITE (a) && DR_IS_READ (b) + && !alias_sets_conflict_p (get_alias_set (DR_REF (a)), + get_alias_set (DR_REF (b)))) + return false; + if (TREE_CODE (addr_a) == MEM_REF) + return ptr_derefs_may_alias_p (TREE_OPERAND (addr_a, 0), + TREE_OPERAND (addr_b, 0)); + else + return ptr_derefs_may_alias_p (build_fold_addr_expr (addr_a), + TREE_OPERAND (addr_b, 0)); + } /* Otherwise DR_BASE_OBJECT is an access that covers the whole object that is being subsetted in the loop nest. */ diff --git a/gcc/tree-data-ref.h b/gcc/tree-data-ref.h index 93a75f2ef79..d56dc927ea6 100644 --- a/gcc/tree-data-ref.h +++ b/gcc/tree-data-ref.h @@ -81,10 +81,6 @@ struct indices /* A list of chrecs. Access functions of the indices. */ vec<tree> access_fns; - - /* Whether BASE_OBJECT is an access representing the whole object - or whether the access could not be constrained. */ - bool unconstrained_base; }; struct dr_alias @@ -195,7 +191,6 @@ struct data_reference #define DR_STMT(DR) (DR)->stmt #define DR_REF(DR) (DR)->ref #define DR_BASE_OBJECT(DR) (DR)->indices.base_object -#define DR_UNCONSTRAINED_BASE(DR) (DR)->indices.unconstrained_base #define DR_ACCESS_FNS(DR) (DR)->indices.access_fns #define DR_ACCESS_FN(DR, I) DR_ACCESS_FNS (DR)[I] #define DR_NUM_DIMENSIONS(DR) DR_ACCESS_FNS (DR).length () diff --git a/gcc/tree-nrv.c b/gcc/tree-nrv.c index 58e7e80c808..082c17871bf 100644 --- a/gcc/tree-nrv.c +++ b/gcc/tree-nrv.c @@ -178,8 +178,7 @@ tree_nrv (void) same type and alignment as the function's result. */ if (TREE_CODE (found) != VAR_DECL || TREE_THIS_VOLATILE (found) - || DECL_CONTEXT (found) != current_function_decl - || TREE_STATIC (found) + || !auto_var_in_fn_p (found, current_function_decl) || TREE_ADDRESSABLE (found) || DECL_ALIGN (found) > DECL_ALIGN (result) || !useless_type_conversion_p (result_type, diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index edcf92918b7..d617f5b625d 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -1438,7 +1438,8 @@ simplify_builtin_call (gimple_stmt_iterator *gsi_p, tree callee2) use_operand_p use_p; if (!host_integerp (val2, 0) - || !host_integerp (len2, 1)) + || !host_integerp (len2, 1) + || compare_tree_int (len2, 1024) == 1) break; if (is_gimple_call (stmt1)) { @@ -1504,7 +1505,8 @@ simplify_builtin_call (gimple_stmt_iterator *gsi_p, tree callee2) is not constant, or is bigger than memcpy length, bail out. */ if (diff == NULL || !host_integerp (diff, 1) - || tree_int_cst_lt (len1, diff)) + || tree_int_cst_lt (len1, diff) + || compare_tree_int (diff, 1024) == 1) break; /* Use maximum of difference plus memset length and memcpy length diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c index b3528391b85..05dc47f7d48 100644 --- a/gcc/tree-ssa-reassoc.c +++ b/gcc/tree-ssa-reassoc.c @@ -1898,7 +1898,7 @@ range_entry_cmp (const void *a, const void *b) else return -1; } - else if (p->high != NULL_TREE) + else if (q->high != NULL_TREE) return 1; /* If both ranges are the same, sort below by ascending idx. */ } @@ -3297,6 +3297,9 @@ acceptable_pow_call (gimple stmt, tree *base, HOST_WIDE_INT *exponent) switch (DECL_FUNCTION_CODE (fndecl)) { CASE_FLT_FN (BUILT_IN_POW): + if (flag_errno_math) + return false; + *base = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index dbad4a80d86..fbd51ec2c98 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -1777,7 +1777,7 @@ strlen_optimize_stmt (gimple_stmt_iterator *gsi) break; } } - else if (is_gimple_assign (stmt)) + else if (is_gimple_assign (stmt) && !gimple_clobber_p (stmt)) { tree lhs = gimple_assign_lhs (stmt); diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index 61add6e0445..3f35657e398 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -298,7 +298,8 @@ stmt_local_def (gimple stmt) def_operand_p def_p; if (gimple_has_side_effects (stmt) - || gimple_vdef (stmt) != NULL_TREE) + || gimple_vdef (stmt) != NULL_TREE + || gimple_vuse (stmt) != NULL_TREE) return false; def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF); @@ -1145,7 +1146,8 @@ gimple_equal_p (same_succ same_succ, gimple s1, gimple s2) gimple_assign_rhs1 (s2))); else if (TREE_CODE (lhs1) == SSA_NAME && TREE_CODE (lhs2) == SSA_NAME) - return vn_valueize (lhs1) == vn_valueize (lhs2); + return operand_equal_p (gimple_assign_rhs1 (s1), + gimple_assign_rhs1 (s2), 0); return false; case GIMPLE_COND: diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index 1cce19f68d6..b29fbd15b78 100644 --- a/gcc/tree-vect-slp.c +++ b/gcc/tree-vect-slp.c @@ -2380,13 +2380,21 @@ vect_get_constant_vectors (tree op, slp_tree slp_node, neutral_op = build_int_cst (TREE_TYPE (op), -1); break; - case MAX_EXPR: - case MIN_EXPR: - def_stmt = SSA_NAME_DEF_STMT (op); - loop = (gimple_bb (stmt))->loop_father; - neutral_op = PHI_ARG_DEF_FROM_EDGE (def_stmt, - loop_preheader_edge (loop)); - break; + /* For MIN/MAX we don't have an easy neutral operand but + the initial values can be used fine here. Only for + a reduction chain we have to force a neutral element. */ + case MAX_EXPR: + case MIN_EXPR: + if (!GROUP_FIRST_ELEMENT (stmt_vinfo)) + neutral_op = NULL; + else + { + def_stmt = SSA_NAME_DEF_STMT (op); + loop = (gimple_bb (stmt))->loop_father; + neutral_op = PHI_ARG_DEF_FROM_EDGE (def_stmt, + loop_preheader_edge (loop)); + } + break; default: neutral_op = NULL; diff --git a/gcc/tree-vrp.c b/gcc/tree-vrp.c index 96a439a9b8a..6363e453822 100644 --- a/gcc/tree-vrp.c +++ b/gcc/tree-vrp.c @@ -6811,7 +6811,7 @@ vrp_evaluate_conditional (enum tree_code code, tree op0, tree op1, gimple stmt) tree type = TREE_TYPE (op0); value_range_t *vr0 = get_value_range (op0); - if (vr0->type != VR_VARYING + if (vr0->type == VR_RANGE && INTEGRAL_TYPE_P (type) && vrp_val_is_min (vr0->min) && vrp_val_is_max (vr0->max) diff --git a/gcc/tree.c b/gcc/tree.c index 006c48134d4..077eed8ac08 100644 --- a/gcc/tree.c +++ b/gcc/tree.c @@ -1130,7 +1130,7 @@ int_cst_hash_hash (const void *x) const_tree const t = (const_tree) x; return (TREE_INT_CST_HIGH (t) ^ TREE_INT_CST_LOW (t) - ^ htab_hash_pointer (TREE_TYPE (t))); + ^ TYPE_UID (TREE_TYPE (t))); } /* Return nonzero if the value represented by *X (an INTEGER_CST tree node) diff --git a/gcc/tsan.c b/gcc/tsan.c index a3b65650e38..01ca69e93fd 100644 --- a/gcc/tsan.c +++ b/gcc/tsan.c @@ -644,25 +644,24 @@ instrument_memory_accesses (void) static void instrument_func_entry (void) { - basic_block succ_bb; - gimple_stmt_iterator gsi; tree ret_addr, builtin_decl; gimple g; - - succ_bb = single_succ (ENTRY_BLOCK_PTR); - gsi = gsi_after_labels (succ_bb); + gimple_seq seq = NULL; builtin_decl = builtin_decl_implicit (BUILT_IN_RETURN_ADDRESS); g = gimple_build_call (builtin_decl, 1, integer_zero_node); ret_addr = make_ssa_name (ptr_type_node, NULL); gimple_call_set_lhs (g, ret_addr); gimple_set_location (g, cfun->function_start_locus); - gsi_insert_before (&gsi, g, GSI_SAME_STMT); + gimple_seq_add_stmt_without_update (&seq, g); - builtin_decl = builtin_decl_implicit (BUILT_IN_TSAN_FUNC_ENTRY); + builtin_decl = builtin_decl_implicit (BUILT_IN_TSAN_FUNC_ENTRY); g = gimple_build_call (builtin_decl, 1, ret_addr); gimple_set_location (g, cfun->function_start_locus); - gsi_insert_before (&gsi, g, GSI_SAME_STMT); + gimple_seq_add_stmt_without_update (&seq, g); + + edge e = single_succ_edge (ENTRY_BLOCK_PTR); + gsi_insert_seq_on_edge_immediate (e, seq); } /* Instruments function exits. */ |