diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2014-10-15 11:47:17 +0000 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2014-10-15 11:47:17 +0000 |
| commit | ce5d70382839034a30e88904d826803f79a519f2 (patch) | |
| tree | 59993d91938397721015a9ea0cd3493d0fc94156 /gcc | |
| parent | e68953536c55973335f595adc0cbdbf6a121a644 (diff) | |
Merge branches/gcc-4_9-branch rev 216130
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@216256 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
157 files changed, 4038 insertions, 789 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fabb693341c..032bc6a1c6d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,532 @@ +2014-10-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63379 + * tree-vect-slp.c (vect_get_constant_vectors): Do not compute + a neutral operand for min/max when it is not a reduction chain. + +2014-10-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2014-10-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * configure.ac: Add --enable-fix-cortex-a53-835769 option. + * configure: Regenerate. + * config/aarch64/aarch64.c (aarch64_override_options): Handle + TARGET_FIX_ERR_A53_835769_DEFAULT. + * config/aarch64/aarch64.opt (mfix-cortex-a53-835769): Set Init + value to 2. + * doc/install.texi (aarch64*-*-*): Document new + --enable-fix-cortex-a53-835769 option. + +2014-10-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2014-10-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * config/aarch64/aarch64.h (FINAL_PRESCAN_INSN): Define. + (ADJUST_INSN_LENGTH): Define. + * config/aarch64/aarch64.opt (mfix-cortex-a53-835769): New option. + * config/aarch64/aarch64.c (is_mem_p): New function. + (is_memory_op): Likewise. + (aarch64_prev_real_insn): Likewise. + (is_madd_op): Likewise. + (dep_between_memop_and_curr): Likewise. + (aarch64_madd_needs_nop): Likewise. + (aarch64_final_prescan_insn): Likewise. + * doc/invoke.texi (AArch64 Options): Document -mfix-cortex-a53-835769 + and -mno-fix-cortex-a53-835769 options. + +2014-10-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63380 + * tree-ssa-tail-merge.c (stmt_local_def): Exclude stmts that + may trap. + +2014-10-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61969 + * tree-nrv.c (pass_nrv::execute): Properly test for automatic + variables. + +2014-10-09 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2014-10-09 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/57003 + * regcprop.c (copyprop_hardreg_forward_1): If ksvd.ignore_set_reg, + also check CALL_INSN_FUNCTION_USAGE for clobbers again after + killing regs_invalidated_by_call. + +2014-10-08 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-10-08 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/52941 + * config/sh/sync.md (atomic_exchangesi_hard, atomic_exchange<mode>_hard, + atomic_fetch_<fetchop_name>si_hard, + atomic_fetch_<fetchop_name><mode>_hard, atomic_fetch_nandsi_hard, + atomic_fetch_nand<mode>_hard, atomic_<fetchop_name>_fetchsi_hard, + atomic_<fetchop_name>_fetch<mode>_hard, atomic_nand_fetchsi_hard, + atomic_nand_fetch<mode>_hard): Add missing set of T_REG. + +2014-10-03 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/61144 + * varpool.c (ctor_for_folding): Do not fold WEAK symbols. + +2014-10-03 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/62121 + * ipa-devirt.c (restrict_to_inner_class): Do not ICE when type is + unknown. + +2014-10-03 Jan Hubicka <hubicka@ucw.cz> + + PR lto/62026 + * lto-streamer-out.c (lto_output): Handle thunks correctly. + * cgraphclones.c (duplicate_thunk_for_node): Get thunk's arguments. + +2014-10-03 Jakub Jelinek <jakub@redhat.com> + + PR libgomp/61200 + * omp-low.c (taskreg_contexts): New variable. + (scan_omp_parallel): Push newly created context into taskreg_contexts + vector and move record layout code to finish_taskreg_scan. + (scan_omp_task): Likewise. + (finish_taskreg_scan): New function. + (execute_lower_omp): Call finish_taskreg_scan on all taskreg_contexts + vector elements and release it. + +2014-10-02 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/63375 + * tree-sra.c (build_access_from_expr_1): Disqualify volatile + references. + +2014-10-01 Jakub Jelinek <jakub@redhat.com> + + PR debug/63342 + * dwarf2out.c (loc_list_from_tree): Handle TARGET_MEM_REF and + SSA_NAME. + + PR target/63428 + * config/i386/i386.c (expand_vec_perm_pshufb): Fix up rperm[0] + argument to avx2_permv2ti. + + PR c++/63306 + Backported from mainline + 2014-08-01 James Greenhalgh <james.greenhalgh@arm.com> + + PR regression/61510 + * cgraphunit.c (analyze_functions): Use get_create rather than get + for decls which are clones of abstract functions. + +2014-10-01 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-09-18 Vladimir Makarov <vmakarov@redhat.com> + + PR debug/63285 + * haifa-sched.c (schedule_block): Advance cycle at the end of BB + if advance != 0. + + 2014-09-10 Jan Hubicka <hubicka@ucw.cz> + + PR tree-optimization/63186 + * ipa-split.c (test_nonssa_use): Skip nonforced labels. + (mark_nonssa_use): Likewise. + (verify_non_ssa_vars): Verify all header blocks for label + definitions. + +2014-10-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2014-10-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/arm.md (*store_minmaxsi): Disable for arm_restrict_it. + +2014-10-01 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2014-09-30 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (fmodxf3): Enable for flag_finite_math_only only. + (fmod<mode>3): Ditto. + (fpremxf4_i387): Ditto. + (reminderxf3): Ditto. + (reminder<mode>3): Ditto. + (fprem1xf4_i387): Ditto. + +2014-09-30 David Malcolm <dmalcolm@redhat.com> + + PR plugins/63410 + * Makefile.in (PLUGIN_HEADERS): Add pass-instances.def. + +2014-09-30 Jakub Jelinek <jakub@redhat.com> + + PR inline-asm/63282 + * ifcvt.c (dead_or_predicable): Don't call redirect_jump_1 + or invert_jump_1 if jump isn't any_condjump_p. + +2014-09-29 James Clarke <jrtc27@jrtc27.com> + Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + PR target/61407 + * config/darwin-c.c (version_as_macro): Added extra 0 for OS X 10.10 + and above. + * config/darwin-driver.c (darwin_find_version_from_kernel): Removed + kernel version check to avoid incrementing it after every major OS X + release. + (darwin_default_min_version): Avoid static memory buffer. + +2014-09-29 Charles Baylis <charles.baylis@linaro.org> + + Backport from mainline r212303 + PR target/49423 + * config/arm/arm-protos.h (arm_legitimate_address_p, + arm_is_constant_pool_ref): Add prototypes. + * config/arm/arm.c (arm_legitimate_address_p): Remove static. + (arm_is_constant_pool_ref) New function. + * config/arm/arm.md (unaligned_loadhis, arm_zero_extendhisi2_v6, + arm_zero_extendqisi2_v6): Use Uh constraint for memory operand. + (arm_extendhisi2, arm_extendhisi2_v6): Use Uh constraint for memory + operand and remove pool_range and neg_pool_range attributes. + (arm_extendqihi_insn, arm_extendqisi, arm_extendqisi_v6): Remove + pool_range and neg_pool_range attributes. + * config/arm/constraints.md (Uh): New constraint. (Uq): Don't allow + constant pool references. + +2014-09-29 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/63247 + * omp-low.c (lower_omp_target): For OMP_CLAUSE_MAP_POINTER + of ARRAY_TYPE, if not OMP_CLAUSE_MAP_ZERO_BIAS_ARRAY_SECTION + use the alignment of avar rather than ovar. + +2014-09-28 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.c (pa_output_function_epilogue): Only update + last_address when a nonnote insn is found. + +2014-09-25 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-09-25 Nick Clifton <nickc@redhat.com> + 2014-09-25 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/62218 + * config/sh/sync.md (atomic_fetch_nand<mode>_soft_imask, + atomic_test_and_set_soft_imask): Fix typo in instruction sequence. + +2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215559 + 2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/63335 + * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): + Exclude VSX_BUILTIN_XVCMPGEDP_P from special handling. + +2014-09-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/63341 + * tree-vectorizer.h (vect_create_data_ref_ptr, + vect_create_addr_base_for_vector_ref): Add another tree argument + defaulting to NULL_TREE. + * tree-vect-data-refs.c (vect_create_data_ref_ptr): Add byte_offset + argument, pass it down to vect_create_addr_base_for_vector_ref. + (vect_create_addr_base_for_vector_ref): Add byte_offset argument, + add that to base_offset too if non-NULL. + * tree-vect-stmts.c (vectorizable_load): Add byte_offset variable, + for dr_explicit_realign_optimized set it to vector byte size + - 1 instead of setting offset, pass byte_offset down to + vect_create_data_ref_ptr. + +2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.md (f32_vsx): New mode attributes to + refine the constraints used on 32/64-bit floating point moves. + (f32_av): Likewise. + (f64_vsx): Likewise. + (f64_dm): Likewise. + (f64_av): Likewise. + (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for + 32/64-bit floating point moves. Do not use wa, instead use ww/ws + for moves involving VSX registers. Do not use constraints that + target VSX registers for decimal types. + (mov<mode>_hardfloat32, DFmode/DDmode): Likewise. + (mov<mode>_hardfloat64, DFmode/DDmode): Likewise. + +2014-09-22 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-05-21 Marek Polacek <polacek@redhat.com> + + PR sanitizer/61272 + * ubsan.c (is_ubsan_builtin_p): Turn assert into a condition. + +2014-09-22 Jakub Jelinek <jakub@redhat.com> + + PR debug/63328 + * omp-low.c (ipa_simd_modify_stmt_ops): For debug stmts + insert a debug source bind stmt setting DEBUG_EXPR_DECL + instead of a normal gimple assignment stmt. + +2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk: + 2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/predicates.md (fusion_gpr_mem_load): Move testing + for base_reg_operand to be common between LO_SUM and PLUS. + (fusion_gpr_mem_combo): New predicate to match a fused address + that combines the addis and memory offset address. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Change + calling signature. + (emit_fusion_gpr_load): Likewise. + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Change calling + signature to pass each argument separately, rather than + using an operands array. Rewrite the insns found by peephole2 to + be a single insn, rather than hoping the insns will still be + together when the peephole pass is done. Drop being called via a + normal peephole. + (emit_fusion_gpr_load): Change calling signature to be called from + the fusion_gpr_load_<mode> insns with a combined memory address + instead of the peephole pass passing the addis and offset + separately. + + * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): New unspec for GPR + fusion. + (power8 fusion peephole): Drop support for doing power8 via a + normal peephole that was created by the peephole2 pass. + (power8 fusion peephole2): Create a new insn with the fused + address, so that the fused operation is kept together after + register allocation is done. + (fusion_gpr_load_<mode>): Likewise. + +2014-09-18 Jakub Jelinek <jakub@redhat.com> + + PR c++/62017 + * asan.c (transform_statements): Don't instrument clobber statements. + +2014-09-17 Jakub Jelinek <jakub@redhat.com> + + PR debug/63284 + * tree-cfgcleanup.c (fixup_noreturn_call): Don't split block + if there are only debug stmts after the noreturn call, instead + remove the debug stmts. + +2014-09-17 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config.gcc (*-*-rtems*): Default to 'rtems' thread model. + Enable selection of 'posix' or no thread model. + +2014-09-16 John David Anglin <danglin@gcc.gnu.org> + + PR target/61853 + * config/pa/pa.c (pa_function_value): Directly handle aggregates + that fit exactly in a word or double word. + +2014-09-15 Markus Trippelsdorf <markus@trippelsdorf.de> + + * doc/install.texi (Options specification): add + --disable-libsanitizer item. + +2014-09-12 DJ Delorie <dj@redhat.com> + + * config/msp430/msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM. + (extend_and_shift1_hipsi2): Likewise. + (extend_and_shift2_hipsi2): Likewise. + +2014-09-12 Martin Jambor <mjambor@suse.cz> + + PR ipa/61654 + * cgraph.h (cgraph_analyze_function): Declare. + * cgraphunit.c: (analyze_function): Remove forward declaration, + rename to cgraph_analyze_function, made external. + * cgraphclones.c (duplicate_thunk_for_node): Copy arguments of the + new decl properly. Analyze the new thunk if it is expanded. + +2014-09-11 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-09-11 H.J. Lu <hongjiu.lu@intel.com> + + PR target/63228 + * config/i386/i386.c (ix86_option_override_internal): Also turn + off OPTION_MASK_ABI_X32 for -m16. + +2014-09-11 James Greenhalgh <james.greenhalgh@arm.com> + + Backport from mainline. + 2014-09-11 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/arm_neon.h (vmull_high_lane_s16): Fix argument + types. + (vmull_high_lane_s32): Likewise. + (vmull_high_lane_u16): Likewise. + (vmull_high_lane_u32): Likewise. + +2014-09-11 Alan Lawrence <alan.lawrence@arm.com> + + Backport r214946 from mainline + 2014-09-05 Alan Lawrence <alan.lawrence@arm.com> + + * config/aarch64/aarch64.md (adddi3_aarch64): Set type to neon_add. + +2014-09-11 Alan Lawrence <alan.lawrence@arm.com> + + Backport r214953 from mainline + 2014-09-05 Alan Lawrence <alan.lawrence@arm.com> + + * config/aarch64/arm_neon.h (int32x1_t, int16x1_t, int8x1_t, + uint32x1_t, uint16x1_t, uint8x1_t): Remove typedefs. + + (vqabsb_s8, vqabsh_s16, vqabss_s32, vqaddb_s8, vqaddh_s16, vqadds_s32, + vqaddb_u8, vqaddh_u16, vqadds_u32, vqdmlalh_s16, vqdmlalh_lane_s16, + vqdmlals_s32, vqdmlslh_s16, vqdmlslh_lane_s16, vqdmlsls_s32, + vqdmulhh_s16, vqdmulhh_lane_s16, vqdmulhs_s32, vqdmulhs_lane_s32, + vqdmullh_s16, vqdmullh_lane_s16, vqdmulls_s32, vqdmulls_lane_s32, + vqmovnh_s16, vqmovns_s32, vqmovnd_s64, vqmovnh_u16, vqmovns_u32, + vqmovnd_u64, vqmovunh_s16, vqmovuns_s32, vqmovund_s64, vqnegb_s8, + vqnegh_s16, vqnegs_s32, vqrdmulhh_s16, vqrdmulhh_lane_s16, + vqrdmulhs_s32, vqrdmulhs_lane_s32, vqrshlb_s8, vqrshlh_s16, + vqrshls_s32, vqrshlb_u8, vqrshlh_u16, vqrshls_u32, vqrshrnh_n_s16, + vqrshrns_n_s32, vqrshrnd_n_s64, vqrshrnh_n_u16, vqrshrns_n_u32, + vqrshrnd_n_u64, vqrshrunh_n_s16, vqrshruns_n_s32, vqrshrund_n_s64, + vqshlb_s8, vqshlh_s16, vqshls_s32, vqshlb_u8, vqshlh_u16, vqshls_u32, + vqshlb_n_s8, vqshlh_n_s16, vqshls_n_s32, vqshlb_n_u8, vqshlh_n_u16, + vqshls_n_u32, vqshlub_n_s8, vqshluh_n_s16, vqshlus_n_s32, + vqshrnh_n_s16, vqshrns_n_s32, vqshrnd_n_s64, vqshrnh_n_u16, + vqshrns_n_u32, vqshrnd_n_u64, vqshrunh_n_s16, vqshruns_n_s32, + vqshrund_n_s64, vqsubb_s8, vqsubh_s16, vqsubs_s32, vqsubb_u8, + vqsubh_u16, vqsubs_u32, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, + vuqaddb_s8, vuqaddh_s16, vuqadds_s32): Replace all int{32,16,8}x1_t + with int{32,16,8}_t. + +2014-09-11 Jason Merrill <jason@redhat.com> + + PR c++/58678 + * ipa-devirt.c (ipa_devirt): Don't check DECL_COMDAT. + +2014-09-11 Georg-Johann Lay <avr@gjlay.de> + + Backport from 2014-09-11 trunk r215152. + + PR target/63223 + * config/avr/avr.md (*tablejump.3byte-pc): New insn. + (*tablejump): Restrict to !AVR_HAVE_EIJMP_EICALL. Add void clobber. + (casesi): Expand to *tablejump.3byte-pc if AVR_HAVE_EIJMP_EICALL. + +2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for + V2DF, V4SF, DF, and DI modes. + (vsx_fmav2df2): Likewise. + (vsx_float_fix_<mode>2): Likewise. + (vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise. + +2014-09-10 Xinliang David Li <davidxl@google.com> + + Backport from mainline + PR target/63209 + * config/arm/arm.md (movcond_addsi): Handle case where source + and target operands are the same. + +2014-09-10 Alan Modra <amodra@gmail.com> + + PR debug/60655 + * dwarf2out.c (mem_loc_descriptor <PLUS>): Return NULL if addend + can't be output. + +2014-09-09 Bill Schmidt <wschmidt@us.ibm.com> + + Backported from mainline + 2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (*vsx_extract_<mode>_load): Always match + selection of 0th memory doubleword, regardless of endianness. + +2014-09-09 James Greenhalgh <james.greenhalgh@arm.com> + + Backport from mainline + 2014-09-09 James Greenhalgh <james.greenhalgh@arm.com> + + * doc/invoke.texi (-march): Use GNU/Linux rather than Linux. + (-mtune): Likewise. + (-mcpu): Likewise. + +2014-09-09 Jason Merrill <jason@redhat.com> + + PR c++/61214 + PR c++/62224 + * gimple-fold.c (can_refer_decl_in_current_unit_p): Don't allow + reference to a DECL_EXTERNAL COMDAT. + +2014-09-09 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-08-05 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/61672 + * emit-rtl.h (mem_attrs_eq_p): Declare. + * emit-rtl.c (mem_attrs_eq_p): Export. Handle NULL mem-attrs. + * cse.c (exp_equiv_p): Use mem_attrs_eq_p. + * cfgcleanup.c (merge_memattrs): Likewise. + Include emit-rtl.h. + + 2014-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62075 + * tree-vect-slp.c (vect_detect_hybrid_slp_stmts): Properly + handle uses in patterns. + + 2014-08-14 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/62079 + * recog.c (peephole2_optimize): If peep2_do_cleanup_cfg + run cleanup_cfg. + + 2014-08-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62175 + * tree-ssa-loop-niter.c (expand_simple_operations): Do not + expand possibly trapping operations. + +2014-09-08 DJ Delorie <dj@redhat.com> + + * doc/invoke.texi (MSP430 Options): Add -minrt. + +2014-09-05 Easwaran Raman <eraman@google.com> + + Backport from mainline + PR rtl-optimization/62146 + * ifcvt.c (dead_or_predicable): Make removal of REG_EQUAL note of + hoisted instruction unconditional. + +2014-09-04 Guozhi Wei <carrot@google.com> + + PR target/62040 + * config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators. + * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Split + it into two patterns. + (move_lo_quad_internal_be_<mode>): Likewise. + 2014-09-03 Martin Jambor <mjambor@suse.cz> PR ipa/62015 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 42c2c08a8bc..ac2dda7fb1b 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20140904 +20141013 diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 9369c4c426d..146b16c5a33 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -3132,7 +3132,7 @@ PLUGIN_HEADERS = $(TREE_H) $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ tree-parloops.h tree-ssa-address.h tree-ssa-coalesce.h tree-ssa-dom.h \ tree-ssa-loop.h tree-ssa-loop-ivopts.h tree-ssa-loop-manip.h \ tree-ssa-loop-niter.h tree-ssa-ter.h tree-ssa-threadedge.h \ - tree-ssa-threadupdate.h + tree-ssa-threadupdate.h pass-instances.def # generate the 'build fragment' b-header-vars s-header-vars: Makefile diff --git a/gcc/asan.c b/gcc/asan.c index 28a476fe4dd..08cc2c022ee 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -2099,6 +2099,7 @@ transform_statements (void) if (has_stmt_been_instrumented_p (s)) gsi_next (&i); else if (gimple_assign_single_p (s) + && !gimple_clobber_p (s) && maybe_instrument_assignment (&i)) /* Nothing to do as maybe_instrument_assignment advanced the iterator I. */; diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index e3c8c8300f9..159cd9d2b2a 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,16 @@ +2014-10-10 Jakub Jelinek <jakub@redhat.com> + + PR c/63495 + * c-common.c (min_align_of_type): Don't decrease alignment + through BIGGEST_FIELD_ALIGNMENT or ADJUST_FIELD_ALIGN if + TYPE_USER_ALIGN is set. + +2014-10-08 Edward Smith-Rowland <3dw4rd@verizon.net> + + Implement SD-6: SG10 Feature Test Recommendations + * c-cppbuiltin.c (c_cpp_builtins()): Define language feature + macros and the __has_header macro. + 2014-08-12 Igor Zamyatin <igor.zamyatin@intel.com> PR other/61962 diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index f3c0dea234a..487fb4ee277 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -4934,16 +4934,18 @@ min_align_of_type (tree type) { unsigned int align = TYPE_ALIGN (type); align = MIN (align, BIGGEST_ALIGNMENT); + if (!TYPE_USER_ALIGN (type)) + { #ifdef BIGGEST_FIELD_ALIGNMENT - align = MIN (align, BIGGEST_FIELD_ALIGNMENT); + align = MIN (align, BIGGEST_FIELD_ALIGNMENT); #endif - unsigned int field_align = align; + unsigned int field_align = align; #ifdef ADJUST_FIELD_ALIGN - tree field = build_decl (UNKNOWN_LOCATION, FIELD_DECL, NULL_TREE, - type); - field_align = ADJUST_FIELD_ALIGN (field, field_align); + tree field = build_decl (UNKNOWN_LOCATION, FIELD_DECL, NULL_TREE, type); + field_align = ADJUST_FIELD_ALIGN (field, field_align); #endif - align = MIN (align, field_align); + align = MIN (align, field_align); + } return align / BITS_PER_UNIT; } diff --git a/gcc/c-family/c-cppbuiltin.c b/gcc/c-family/c-cppbuiltin.c index 2f2e7bae824..b65e08f3b99 100644 --- a/gcc/c-family/c-cppbuiltin.c +++ b/gcc/c-family/c-cppbuiltin.c @@ -794,18 +794,66 @@ c_cpp_builtins (cpp_reader *pfile) /* For stddef.h. They require macros defined in c-common.c. */ c_stddef_cpp_builtins (); + /* Set include test macros for all C/C++ (not for just C++11 etc.) + the builtins __has_include__ and __has_include_next__ are defined + in libcpp. */ + cpp_define (pfile, "__has_include(STR)=__has_include__(STR)"); + cpp_define (pfile, "__has_include_next(STR)=__has_include_next__(STR)"); + if (c_dialect_cxx ()) { if (flag_weak && SUPPORTS_ONE_ONLY) cpp_define (pfile, "__GXX_WEAK__=1"); else cpp_define (pfile, "__GXX_WEAK__=0"); + if (warn_deprecated) cpp_define (pfile, "__DEPRECATED"); + if (flag_rtti) cpp_define (pfile, "__GXX_RTTI"); + if (cxx_dialect >= cxx11) cpp_define (pfile, "__GXX_EXPERIMENTAL_CXX0X__"); + + /* Binary literals have been allowed in g++ before C++11 + and were standardized for C++14. */ + if (!pedantic || cxx_dialect > cxx11) + cpp_define (pfile, "__cpp_binary_literals=201304"); + if (cxx_dialect >= cxx11) + { + /* Set feature test macros for C++11 */ + cpp_define (pfile, "__cpp_unicode_characters=200704"); + cpp_define (pfile, "__cpp_raw_strings=200710"); + cpp_define (pfile, "__cpp_unicode_literals=200710"); + cpp_define (pfile, "__cpp_user_defined_literals=200809"); + cpp_define (pfile, "__cpp_lambdas=200907"); + cpp_define (pfile, "__cpp_constexpr=200704"); + cpp_define (pfile, "__cpp_static_assert=200410"); + cpp_define (pfile, "__cpp_decltype=200707"); + cpp_define (pfile, "__cpp_attributes=200809"); + cpp_define (pfile, "__cpp_rvalue_reference=200610"); + cpp_define (pfile, "__cpp_variadic_templates=200704"); + cpp_define (pfile, "__cpp_alias_templates=200704"); + } + if (cxx_dialect > cxx11) + { + /* Set feature test macros for C++14 */ + cpp_define (pfile, "__cpp_return_type_deduction=201304"); + cpp_define (pfile, "__cpp_init_captures=201304"); + cpp_define (pfile, "__cpp_generic_lambdas=201304"); + //cpp_undef (pfile, "__cpp_constexpr"); + //cpp_define (pfile, "__cpp_constexpr=201304"); + cpp_define (pfile, "__cpp_decltype_auto=201304"); + //cpp_define (pfile, "__cpp_aggregate_nsdmi=201304"); + //cpp_define (pfile, "__cpp_variable_templates=201304"); + cpp_define (pfile, "__cpp_digit_separators=201309"); + cpp_define (pfile, "__cpp_attribute_deprecated=201309"); + //cpp_define (pfile, "__cpp_sized_deallocation=201309"); + /* We'll have to see where runtime arrays wind up. + Let's put it in C++14 for now. */ + cpp_define (pfile, "__cpp_runtime_arrays=201304"); + } } /* Note that we define this for C as well, so that we know if __attribute__((cleanup)) will interface with EH. */ diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 4afd58170b3..6cf964c1c4a 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,9 @@ +2014-09-25 Thomas Schwinge <thomas@codesourcery.com> + + PR c++/63249 + * c-parser.c (c_parser_omp_variable_list): Call mark_exp_read + on low_bound and length. + 2014-09-03 Marek Polacek <polacek@redhat.com> PR c/62294 diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c index 060233765c9..3ab01c0d7de 100644 --- a/gcc/c/c-parser.c +++ b/gcc/c/c-parser.c @@ -9767,7 +9767,10 @@ c_parser_omp_variable_list (c_parser *parser, c_parser_consume_token (parser); if (!c_parser_next_token_is (parser, CPP_COLON)) - low_bound = c_parser_expression (parser).value; + { + low_bound = c_parser_expression (parser).value; + mark_exp_read (low_bound); + } if (c_parser_next_token_is (parser, CPP_CLOSE_SQUARE)) length = integer_one_node; else @@ -9780,7 +9783,10 @@ c_parser_omp_variable_list (c_parser *parser, break; } if (!c_parser_next_token_is (parser, CPP_CLOSE_SQUARE)) - length = c_parser_expression (parser).value; + { + length = c_parser_expression (parser).value; + mark_exp_read (length); + } } /* Look for the closing `]'. */ if (!c_parser_require (parser, CPP_CLOSE_SQUARE, diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c index 77196ee6bf7..de307da542c 100644 --- a/gcc/cfgcleanup.c +++ b/gcc/cfgcleanup.c @@ -53,6 +53,7 @@ along with GCC; see the file COPYING3. If not see #include "df.h" #include "dce.h" #include "dbgcnt.h" +#include "emit-rtl.h" #define FORWARDER_BLOCK_P(BB) ((BB)->flags & BB_FORWARDER_BLOCK) @@ -882,7 +883,7 @@ merge_memattrs (rtx x, rtx y) if (GET_MODE (x) != GET_MODE (y)) return; - if (code == MEM && MEM_ATTRS (x) != MEM_ATTRS (y)) + if (code == MEM && !mem_attrs_eq_p (MEM_ATTRS (x), MEM_ATTRS (y))) { if (! MEM_ATTRS (x)) MEM_ATTRS (y) = 0; diff --git a/gcc/cgraph.h b/gcc/cgraph.h index 6c3be6d7508..0d13ebe9a21 100644 --- a/gcc/cgraph.h +++ b/gcc/cgraph.h @@ -797,6 +797,7 @@ void cgraph_unnest_node (struct cgraph_node *); enum availability cgraph_function_body_availability (struct cgraph_node *); void cgraph_add_new_function (tree, bool); +void cgraph_analyze_function (struct cgraph_node *); const char* cgraph_inline_failed_string (cgraph_inline_failed_t); cgraph_inline_failed_type_t cgraph_inline_failed_type (cgraph_inline_failed_t); diff --git a/gcc/cgraphclones.c b/gcc/cgraphclones.c index 972ca0708c4..e310b1ce801 100644 --- a/gcc/cgraphclones.c +++ b/gcc/cgraphclones.c @@ -310,6 +310,11 @@ duplicate_thunk_for_node (cgraph_node *thunk, cgraph_node *node) if (thunk_of->thunk.thunk_p) node = duplicate_thunk_for_node (thunk_of, node); + /* We need to copy arguments, at LTO these mat not be read from function + section. */ + if (!DECL_ARGUMENTS (thunk->decl)) + cgraph_get_body (thunk); + struct cgraph_edge *cs; for (cs = node->callers; cs; cs = cs->next_caller) if (cs->caller->thunk.thunk_p @@ -334,6 +339,22 @@ duplicate_thunk_for_node (cgraph_node *thunk, cgraph_node *node) node->clone.args_to_skip, false); } + + tree *link = &DECL_ARGUMENTS (new_decl); + int i = 0; + for (tree pd = DECL_ARGUMENTS (thunk->decl); pd; pd = DECL_CHAIN (pd), i++) + { + if (!node->clone.args_to_skip + || !bitmap_bit_p (node->clone.args_to_skip, i)) + { + tree nd = copy_node (pd); + DECL_CONTEXT (nd) = new_decl; + *link = nd; + link = &DECL_CHAIN (nd); + } + } + *link = NULL_TREE; + gcc_checking_assert (!DECL_STRUCT_FUNCTION (new_decl)); gcc_checking_assert (!DECL_INITIAL (new_decl)); gcc_checking_assert (!DECL_RESULT (new_decl)); @@ -358,6 +379,11 @@ duplicate_thunk_for_node (cgraph_node *thunk, cgraph_node *node) cgraph_call_edge_duplication_hooks (thunk->callees, e); if (!expand_thunk (new_thunk, false)) new_thunk->analyzed = true; + else + { + new_thunk->thunk.thunk_p = false; + cgraph_analyze_function (new_thunk); + } cgraph_call_node_duplication_hooks (thunk, new_thunk); return new_thunk; } diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index 8abdc5d3f8e..8f576076b65 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -219,7 +219,6 @@ cgraph_node_set cgraph_new_nodes; static void expand_all_functions (void); static void mark_functions_to_output (void); static void expand_function (struct cgraph_node *); -static void analyze_function (struct cgraph_node *); static void handle_alias_pairs (void); FILE *cgraph_dump_file; @@ -331,7 +330,7 @@ cgraph_process_new_functions (void) gimple_register_cfg_hooks (); if (!node->analyzed) - analyze_function (node); + cgraph_analyze_function (node); push_cfun (DECL_STRUCT_FUNCTION (fndecl)); if (cgraph_state == CGRAPH_STATE_IPA_SSA && !gimple_in_ssa_p (DECL_STRUCT_FUNCTION (fndecl))) @@ -541,7 +540,7 @@ cgraph_add_new_function (tree fndecl, bool lowered) if (lowered) node->lowered = true; node->definition = true; - analyze_function (node); + cgraph_analyze_function (node); push_cfun (DECL_STRUCT_FUNCTION (fndecl)); gimple_register_cfg_hooks (); bitmap_obstack_initialize (NULL); @@ -598,8 +597,8 @@ output_asm_statements (void) } /* Analyze the function scheduled to be output. */ -static void -analyze_function (struct cgraph_node *node) +void +cgraph_analyze_function (struct cgraph_node *node) { tree decl = node->decl; location_t saved_loc = input_location; @@ -1014,7 +1013,7 @@ analyze_functions (void) } if (!cnode->analyzed) - analyze_function (cnode); + cgraph_analyze_function (cnode); for (edge = cnode->callees; edge; edge = edge->next_callee) if (edge->callee->definition) @@ -1039,7 +1038,7 @@ analyze_functions (void) if (DECL_ABSTRACT_ORIGIN (decl)) { struct cgraph_node *origin_node - = cgraph_get_node (DECL_ABSTRACT_ORIGIN (decl)); + = cgraph_get_create_node (DECL_ABSTRACT_ORIGIN (decl)); origin_node->used_as_abstract_origin = true; } } diff --git a/gcc/config.gcc b/gcc/config.gcc index e6fd076a10d..314dbef601d 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -791,7 +791,13 @@ case ${target} in ;; *-*-rtems*) case ${enable_threads} in - yes) thread_file='rtems' ;; + "" | yes | rtems) thread_file='rtems' ;; + posix) thread_file='posix' ;; + no) ;; + *) + echo 'Unknown thread configuration for RTEMS' + exit 1 + ;; esac tmake_file="${tmake_file} t-rtems" extra_options="${extra_options} rtems.opt" diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 271d20185e5..430f6fc396e 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -309,6 +309,8 @@ aarch64_builtin_vectorized_function (tree fndecl, extern void aarch64_split_combinev16qi (rtx operands[3]); extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); +extern bool aarch64_madd_needs_nop (rtx); +extern void aarch64_final_prescan_insn (rtx); extern bool aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 6929b7704af..b1cabd94ea1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -962,8 +962,8 @@ ;; On big-endian this is { zeroes, operand } (define_insn "move_lo_quad_internal_<mode>" - [(set (match_operand:VQ 0 "register_operand" "=w,w,w") - (vec_concat:VQ + [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_NO2E (match_operand:<VHALF> 1 "register_operand" "w,r,r") (vec_duplicate:<VHALF> (const_int 0))))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" @@ -977,9 +977,25 @@ (set_attr "length" "4")] ) +(define_insn "move_lo_quad_internal_<mode>" + [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_2E + (match_operand:<VHALF> 1 "register_operand" "w,r,r") + (const_int 0)))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "@ + dup\\t%d0, %1.d[0] + fmov\\t%d0, %1 + dup\\t%d0, %1" + [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") + (set_attr "simd" "yes,*,yes") + (set_attr "fp" "*,yes,*") + (set_attr "length" "4")] +) + (define_insn "move_lo_quad_internal_be_<mode>" - [(set (match_operand:VQ 0 "register_operand" "=w,w,w") - (vec_concat:VQ + [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_NO2E (vec_duplicate:<VHALF> (const_int 0)) (match_operand:<VHALF> 1 "register_operand" "w,r,r")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" @@ -993,6 +1009,22 @@ (set_attr "length" "4")] ) +(define_insn "move_lo_quad_internal_be_<mode>" + [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_2E + (const_int 0) + (match_operand:<VHALF> 1 "register_operand" "w,r,r")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "@ + dup\\t%d0, %1.d[0] + fmov\\t%d0, %1 + dup\\t%d0, %1" + [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") + (set_attr "simd" "yes,*,yes") + (set_attr "fp" "*,yes,*") + (set_attr "length" "4")] +) + (define_expand "move_lo_quad_<mode>" [(match_operand:VQ 0 "register_operand") (match_operand:VQ 1 "register_operand")] diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 6c6fcfb6b44..7ed7faaabe5 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6291,6 +6291,15 @@ aarch64_override_options (void) aarch64_tune = selected_tune->core; aarch64_tune_params = selected_tune->tune; + if (aarch64_fix_a53_err835769 == 2) + { +#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT + aarch64_fix_a53_err835769 = 1; +#else + aarch64_fix_a53_err835769 = 0; +#endif + } + aarch64_override_options_after_change (); } @@ -7487,6 +7496,128 @@ aarch64_mangle_type (const_tree type) return NULL; } +static int +is_mem_p (rtx *x, void *data ATTRIBUTE_UNUSED) +{ + return MEM_P (*x); +} + +static bool +is_memory_op (rtx mem_insn) +{ + rtx pattern = PATTERN (mem_insn); + return for_each_rtx (&pattern, is_mem_p, NULL); +} + +/* Find the first rtx before insn that will generate an assembly + instruction. */ + +static rtx +aarch64_prev_real_insn (rtx insn) +{ + if (!insn) + return NULL; + + do + { + insn = prev_real_insn (insn); + } + while (insn && recog_memoized (insn) < 0); + + return insn; +} + +static bool +is_madd_op (enum attr_type t1) +{ + unsigned int i; + /* A number of these may be AArch32 only. */ + enum attr_type mlatypes[] = { + TYPE_MLA, TYPE_MLAS, TYPE_SMLAD, TYPE_SMLADX, TYPE_SMLAL, TYPE_SMLALD, + TYPE_SMLALS, TYPE_SMLALXY, TYPE_SMLAWX, TYPE_SMLAWY, TYPE_SMLAXY, + TYPE_SMMLA, TYPE_UMLAL, TYPE_UMLALS,TYPE_SMLSD, TYPE_SMLSDX, TYPE_SMLSLD + }; + + for (i = 0; i < sizeof (mlatypes) / sizeof (enum attr_type); i++) + { + if (t1 == mlatypes[i]) + return true; + } + + return false; +} + +/* Check if there is a register dependency between a load and the insn + for which we hold recog_data. */ + +static bool +dep_between_memop_and_curr (rtx memop) +{ + rtx load_reg; + int opno; + + if (!memop) + return false; + + if (!REG_P (SET_DEST (memop))) + return false; + + load_reg = SET_DEST (memop); + for (opno = 0; opno < recog_data.n_operands; opno++) + { + rtx operand = recog_data.operand[opno]; + if (REG_P (operand) + && reg_overlap_mentioned_p (load_reg, operand)) + return true; + + } + return false; +} + +bool +aarch64_madd_needs_nop (rtx insn) +{ + enum attr_type attr_type; + rtx prev; + rtx body; + + if (!aarch64_fix_a53_err835769) + return false; + + if (recog_memoized (insn) < 0) + return false; + + attr_type = get_attr_type (insn); + if (!is_madd_op (attr_type)) + return false; + + prev = aarch64_prev_real_insn (insn); + if (!prev) + return false; + + body = single_set (prev); + + /* If the previous insn is a memory op and there is no dependency between + it and the madd, emit a nop between them. If we know the previous insn is + a memory op but body is NULL, emit the nop to be safe, it's probably a + load/store pair insn. */ + if (is_memory_op (prev) + && GET_MODE (recog_data.operand[0]) == DImode + && (!dep_between_memop_and_curr (body))) + return true; + + return false; + +} + +void +aarch64_final_prescan_insn (rtx insn) +{ + if (aarch64_madd_needs_nop (insn)) + fprintf (asm_out_file, "\tnop // between mem op and mult-accumulate\n"); +} + + /* Return the equivalent letter for size. */ static char sizetochar (int size) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index cd05f68f3f2..1b9cbcba21b 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -489,6 +489,15 @@ enum target_cpus (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) #endif +/* If inserting NOP before a mult-accumulate insn remember to adjust the + length so that conditional branching code is updated appropriately. */ +#define ADJUST_INSN_LENGTH(insn, length) \ + if (aarch64_madd_needs_nop (insn)) \ + length += 4; + +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ + aarch64_final_prescan_insn (INSN); \ + /* The processor for which instructions should be scheduled. */ extern enum aarch64_processor aarch64_tune; diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b013f4cf4a0..8dcfa3dce57 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1180,7 +1180,7 @@ add\\t%x0, %x1, %x2 sub\\t%x0, %x1, #%n2 add\\t%d0, %d1, %d2" - [(set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg") + [(set_attr "type" "alu_imm,alu_reg,alu_imm,neon_add") (set_attr "simd" "*,*,*,yes")] ) diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index f5a15b7298e..fc0307e2869 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -67,6 +67,10 @@ mgeneral-regs-only Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Generate code which uses only the general registers +mfix-cortex-a53-835769 +Target Report Var(aarch64_fix_a53_err835769) Init(2) +Workaround for ARM Cortex-A53 Erratum number 835769 + mlittle-endian Target Report RejectNegative InverseMask(BIG_END) Assume target CPU is configured as little endian diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index b782236b7ba..9596dcff157 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -39,9 +39,6 @@ typedef __builtin_aarch64_simd_hi int16x4_t typedef __builtin_aarch64_simd_si int32x2_t __attribute__ ((__vector_size__ (8))); typedef int64_t int64x1_t; -typedef int32_t int32x1_t; -typedef int16_t int16x1_t; -typedef int8_t int8x1_t; typedef double float64x1_t; typedef __builtin_aarch64_simd_sf float32x2_t __attribute__ ((__vector_size__ (8))); @@ -56,9 +53,6 @@ typedef __builtin_aarch64_simd_uhi uint16x4_t typedef __builtin_aarch64_simd_usi uint32x2_t __attribute__ ((__vector_size__ (8))); typedef uint64_t uint64x1_t; -typedef uint32_t uint32x1_t; -typedef uint16_t uint16x1_t; -typedef uint8_t uint8x1_t; typedef __builtin_aarch64_simd_qi int8x16_t __attribute__ ((__vector_size__ (16))); typedef __builtin_aarch64_simd_hi int16x8_t @@ -8297,7 +8291,7 @@ vmul_n_u32 (uint32x2_t a, uint32_t b) #define vmull_high_lane_s16(a, b, c) \ __extension__ \ ({ \ - int16x8_t b_ = (b); \ + int16x4_t b_ = (b); \ int16x8_t a_ = (a); \ int32x4_t result; \ __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]" \ @@ -8310,7 +8304,7 @@ vmul_n_u32 (uint32x2_t a, uint32_t b) #define vmull_high_lane_s32(a, b, c) \ __extension__ \ ({ \ - int32x4_t b_ = (b); \ + int32x2_t b_ = (b); \ int32x4_t a_ = (a); \ int64x2_t result; \ __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]" \ @@ -8323,7 +8317,7 @@ vmul_n_u32 (uint32x2_t a, uint32_t b) #define vmull_high_lane_u16(a, b, c) \ __extension__ \ ({ \ - uint16x8_t b_ = (b); \ + uint16x4_t b_ = (b); \ uint16x8_t a_ = (a); \ uint32x4_t result; \ __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]" \ @@ -8336,7 +8330,7 @@ vmul_n_u32 (uint32x2_t a, uint32_t b) #define vmull_high_lane_u32(a, b, c) \ __extension__ \ ({ \ - uint32x4_t b_ = (b); \ + uint32x2_t b_ = (b); \ uint32x4_t a_ = (a); \ uint64x2_t result; \ __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]" \ @@ -19085,22 +19079,22 @@ vqabsq_s64 (int64x2_t __a) return (int64x2_t) __builtin_aarch64_sqabsv2di (__a); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqabsb_s8 (int8x1_t __a) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqabsb_s8 (int8_t __a) { - return (int8x1_t) __builtin_aarch64_sqabsqi (__a); + return (int8_t) __builtin_aarch64_sqabsqi (__a); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqabsh_s16 (int16x1_t __a) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqabsh_s16 (int16_t __a) { - return (int16x1_t) __builtin_aarch64_sqabshi (__a); + return (int16_t) __builtin_aarch64_sqabshi (__a); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqabss_s32 (int32x1_t __a) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqabss_s32 (int32_t __a) { - return (int32x1_t) __builtin_aarch64_sqabssi (__a); + return (int32_t) __builtin_aarch64_sqabssi (__a); } __extension__ static __inline int64_t __attribute__ ((__always_inline__)) @@ -19111,22 +19105,22 @@ vqabsd_s64 (int64_t __a) /* vqadd */ -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqaddb_s8 (int8x1_t __a, int8x1_t __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqaddb_s8 (int8_t __a, int8_t __b) { - return (int8x1_t) __builtin_aarch64_sqaddqi (__a, __b); + return (int8_t) __builtin_aarch64_sqaddqi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqaddh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqaddh_s16 (int16_t __a, int16_t __b) { - return (int16x1_t) __builtin_aarch64_sqaddhi (__a, __b); + return (int16_t) __builtin_aarch64_sqaddhi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqadds_s32 (int32x1_t __a, int32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqadds_s32 (int32_t __a, int32_t __b) { - return (int32x1_t) __builtin_aarch64_sqaddsi (__a, __b); + return (int32_t) __builtin_aarch64_sqaddsi (__a, __b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) @@ -19135,22 +19129,22 @@ vqaddd_s64 (int64x1_t __a, int64x1_t __b) return (int64x1_t) __builtin_aarch64_sqadddi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqaddb_u8 (uint8x1_t __a, uint8x1_t __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqaddb_u8 (uint8_t __a, uint8_t __b) { - return (uint8x1_t) __builtin_aarch64_uqaddqi_uuu (__a, __b); + return (uint8_t) __builtin_aarch64_uqaddqi_uuu (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqaddh_u16 (uint16x1_t __a, uint16x1_t __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqaddh_u16 (uint16_t __a, uint16_t __b) { - return (uint16x1_t) __builtin_aarch64_uqaddhi_uuu (__a, __b); + return (uint16_t) __builtin_aarch64_uqaddhi_uuu (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -vqadds_u32 (uint32x1_t __a, uint32x1_t __b) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vqadds_u32 (uint32_t __a, uint32_t __b) { - return (uint32x1_t) __builtin_aarch64_uqaddsi_uuu (__a, __b); + return (uint32_t) __builtin_aarch64_uqaddsi_uuu (__a, __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) @@ -19262,26 +19256,26 @@ vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) return __builtin_aarch64_sqdmlal_nv2si (__a, __b, __c); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmlalh_s16 (int32x1_t __a, int16x1_t __b, int16x1_t __c) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmlalh_s16 (int32_t __a, int16_t __b, int16_t __c) { return __builtin_aarch64_sqdmlalhi (__a, __b, __c); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmlalh_lane_s16 (int32x1_t __a, int16x1_t __b, int16x4_t __c, const int __d) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmlalh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d) { return __builtin_aarch64_sqdmlal_lanehi (__a, __b, __c, __d); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vqdmlals_s32 (int64x1_t __a, int32x1_t __b, int32x1_t __c) +vqdmlals_s32 (int64x1_t __a, int32_t __b, int32_t __c) { return __builtin_aarch64_sqdmlalsi (__a, __b, __c); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vqdmlals_lane_s32 (int64x1_t __a, int32x1_t __b, int32x2_t __c, const int __d) +vqdmlals_lane_s32 (int64x1_t __a, int32_t __b, int32x2_t __c, const int __d) { return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d); } @@ -19388,26 +19382,26 @@ vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) return __builtin_aarch64_sqdmlsl_nv2si (__a, __b, __c); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmlslh_s16 (int32x1_t __a, int16x1_t __b, int16x1_t __c) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmlslh_s16 (int32_t __a, int16_t __b, int16_t __c) { return __builtin_aarch64_sqdmlslhi (__a, __b, __c); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmlslh_lane_s16 (int32x1_t __a, int16x1_t __b, int16x4_t __c, const int __d) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmlslh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d) { return __builtin_aarch64_sqdmlsl_lanehi (__a, __b, __c, __d); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vqdmlsls_s32 (int64x1_t __a, int32x1_t __b, int32x1_t __c) +vqdmlsls_s32 (int64x1_t __a, int32_t __b, int32_t __c) { return __builtin_aarch64_sqdmlslsi (__a, __b, __c); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vqdmlsls_lane_s32 (int64x1_t __a, int32x1_t __b, int32x2_t __c, const int __d) +vqdmlsls_lane_s32 (int64x1_t __a, int32_t __b, int32x2_t __c, const int __d) { return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d); } @@ -19438,26 +19432,26 @@ vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqdmulhh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqdmulhh_s16 (int16_t __a, int16_t __b) { - return (int16x1_t) __builtin_aarch64_sqdmulhhi (__a, __b); + return (int16_t) __builtin_aarch64_sqdmulhhi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqdmulhh_lane_s16 (int16x1_t __a, int16x4_t __b, const int __c) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c) { return __builtin_aarch64_sqdmulh_lanehi (__a, __b, __c); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmulhs_s32 (int32x1_t __a, int32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmulhs_s32 (int32_t __a, int32_t __b) { - return (int32x1_t) __builtin_aarch64_sqdmulhsi (__a, __b); + return (int32_t) __builtin_aarch64_sqdmulhsi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmulhs_lane_s32 (int32x1_t __a, int32x2_t __b, const int __c) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c) { return __builtin_aarch64_sqdmulh_lanesi (__a, __b, __c); } @@ -19560,26 +19554,26 @@ vqdmull_n_s32 (int32x2_t __a, int32_t __b) return __builtin_aarch64_sqdmull_nv2si (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmullh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmullh_s16 (int16_t __a, int16_t __b) { - return (int32x1_t) __builtin_aarch64_sqdmullhi (__a, __b); + return (int32_t) __builtin_aarch64_sqdmullhi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqdmullh_lane_s16 (int16x1_t __a, int16x4_t __b, const int __c) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqdmullh_lane_s16 (int16_t __a, int16x4_t __b, const int __c) { return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vqdmulls_s32 (int32x1_t __a, int32x1_t __b) +vqdmulls_s32 (int32_t __a, int32_t __b) { return (int64x1_t) __builtin_aarch64_sqdmullsi (__a, __b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vqdmulls_lane_s32 (int32x1_t __a, int32x2_t __b, const int __c) +vqdmulls_lane_s32 (int32_t __a, int32x2_t __b, const int __c) { return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c); } @@ -19622,40 +19616,40 @@ vqmovn_u64 (uint64x2_t __a) return (uint32x2_t) __builtin_aarch64_uqmovnv2di ((int64x2_t) __a); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqmovnh_s16 (int16x1_t __a) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqmovnh_s16 (int16_t __a) { - return (int8x1_t) __builtin_aarch64_sqmovnhi (__a); + return (int8_t) __builtin_aarch64_sqmovnhi (__a); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqmovns_s32 (int32x1_t __a) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqmovns_s32 (int32_t __a) { - return (int16x1_t) __builtin_aarch64_sqmovnsi (__a); + return (int16_t) __builtin_aarch64_sqmovnsi (__a); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) vqmovnd_s64 (int64x1_t __a) { - return (int32x1_t) __builtin_aarch64_sqmovndi (__a); + return (int32_t) __builtin_aarch64_sqmovndi (__a); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqmovnh_u16 (uint16x1_t __a) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqmovnh_u16 (uint16_t __a) { - return (uint8x1_t) __builtin_aarch64_uqmovnhi (__a); + return (uint8_t) __builtin_aarch64_uqmovnhi (__a); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqmovns_u32 (uint32x1_t __a) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqmovns_u32 (uint32_t __a) { - return (uint16x1_t) __builtin_aarch64_uqmovnsi (__a); + return (uint16_t) __builtin_aarch64_uqmovnsi (__a); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vqmovnd_u64 (uint64x1_t __a) { - return (uint32x1_t) __builtin_aarch64_uqmovndi (__a); + return (uint32_t) __builtin_aarch64_uqmovndi (__a); } /* vqmovun */ @@ -19678,22 +19672,22 @@ vqmovun_s64 (int64x2_t __a) return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqmovunh_s16 (int16x1_t __a) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqmovunh_s16 (int16_t __a) { - return (int8x1_t) __builtin_aarch64_sqmovunhi (__a); + return (int8_t) __builtin_aarch64_sqmovunhi (__a); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqmovuns_s32 (int32x1_t __a) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqmovuns_s32 (int32_t __a) { - return (int16x1_t) __builtin_aarch64_sqmovunsi (__a); + return (int16_t) __builtin_aarch64_sqmovunsi (__a); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) vqmovund_s64 (int64x1_t __a) { - return (int32x1_t) __builtin_aarch64_sqmovundi (__a); + return (int32_t) __builtin_aarch64_sqmovundi (__a); } /* vqneg */ @@ -19704,22 +19698,22 @@ vqnegq_s64 (int64x2_t __a) return (int64x2_t) __builtin_aarch64_sqnegv2di (__a); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqnegb_s8 (int8x1_t __a) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqnegb_s8 (int8_t __a) { - return (int8x1_t) __builtin_aarch64_sqnegqi (__a); + return (int8_t) __builtin_aarch64_sqnegqi (__a); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqnegh_s16 (int16x1_t __a) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqnegh_s16 (int16_t __a) { - return (int16x1_t) __builtin_aarch64_sqneghi (__a); + return (int16_t) __builtin_aarch64_sqneghi (__a); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqnegs_s32 (int32x1_t __a) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqnegs_s32 (int32_t __a) { - return (int32x1_t) __builtin_aarch64_sqnegsi (__a); + return (int32_t) __builtin_aarch64_sqnegsi (__a); } __extension__ static __inline int64_t __attribute__ ((__always_inline__)) @@ -19754,26 +19748,26 @@ vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqrdmulhh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqrdmulhh_s16 (int16_t __a, int16_t __b) { - return (int16x1_t) __builtin_aarch64_sqrdmulhhi (__a, __b); + return (int16_t) __builtin_aarch64_sqrdmulhhi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqrdmulhh_lane_s16 (int16x1_t __a, int16x4_t __b, const int __c) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqrdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c) { return __builtin_aarch64_sqrdmulh_lanehi (__a, __b, __c); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqrdmulhs_s32 (int32x1_t __a, int32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqrdmulhs_s32 (int32_t __a, int32_t __b) { - return (int32x1_t) __builtin_aarch64_sqrdmulhsi (__a, __b); + return (int32_t) __builtin_aarch64_sqrdmulhsi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqrdmulhs_lane_s32 (int32x1_t __a, int32x2_t __b, const int __c) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqrdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c) { return __builtin_aarch64_sqrdmulh_lanesi (__a, __b, __c); } @@ -19876,20 +19870,20 @@ vqrshlq_u64 (uint64x2_t __a, int64x2_t __b) return __builtin_aarch64_uqrshlv2di_uus ( __a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqrshlb_s8 (int8x1_t __a, int8x1_t __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqrshlb_s8 (int8_t __a, int8_t __b) { return __builtin_aarch64_sqrshlqi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqrshlh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqrshlh_s16 (int16_t __a, int16_t __b) { return __builtin_aarch64_sqrshlhi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqrshls_s32 (int32x1_t __a, int32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqrshls_s32 (int32_t __a, int32_t __b) { return __builtin_aarch64_sqrshlsi (__a, __b); } @@ -19900,20 +19894,20 @@ vqrshld_s64 (int64x1_t __a, int64x1_t __b) return __builtin_aarch64_sqrshldi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqrshlb_u8 (uint8x1_t __a, uint8x1_t __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqrshlb_u8 (uint8_t __a, uint8_t __b) { return __builtin_aarch64_uqrshlqi_uus (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqrshlh_u16 (uint16x1_t __a, uint16x1_t __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqrshlh_u16 (uint16_t __a, uint16_t __b) { return __builtin_aarch64_uqrshlhi_uus (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -vqrshls_u32 (uint32x1_t __a, uint32x1_t __b) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vqrshls_u32 (uint32_t __a, uint32_t __b) { return __builtin_aarch64_uqrshlsi_uus (__a, __b); } @@ -19962,37 +19956,37 @@ vqrshrn_n_u64 (uint64x2_t __a, const int __b) return __builtin_aarch64_uqrshrn_nv2di_uus ( __a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqrshrnh_n_s16 (int16x1_t __a, const int __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqrshrnh_n_s16 (int16_t __a, const int __b) { - return (int8x1_t) __builtin_aarch64_sqrshrn_nhi (__a, __b); + return (int8_t) __builtin_aarch64_sqrshrn_nhi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqrshrns_n_s32 (int32x1_t __a, const int __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqrshrns_n_s32 (int32_t __a, const int __b) { - return (int16x1_t) __builtin_aarch64_sqrshrn_nsi (__a, __b); + return (int16_t) __builtin_aarch64_sqrshrn_nsi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) vqrshrnd_n_s64 (int64x1_t __a, const int __b) { - return (int32x1_t) __builtin_aarch64_sqrshrn_ndi (__a, __b); + return (int32_t) __builtin_aarch64_sqrshrn_ndi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqrshrnh_n_u16 (uint16x1_t __a, const int __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqrshrnh_n_u16 (uint16_t __a, const int __b) { return __builtin_aarch64_uqrshrn_nhi_uus (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqrshrns_n_u32 (uint32x1_t __a, const int __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqrshrns_n_u32 (uint32_t __a, const int __b) { return __builtin_aarch64_uqrshrn_nsi_uus (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vqrshrnd_n_u64 (uint64x1_t __a, const int __b) { return __builtin_aarch64_uqrshrn_ndi_uus (__a, __b); @@ -20018,22 +20012,22 @@ vqrshrun_n_s64 (int64x2_t __a, const int __b) return (uint32x2_t) __builtin_aarch64_sqrshrun_nv2di (__a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqrshrunh_n_s16 (int16x1_t __a, const int __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqrshrunh_n_s16 (int16_t __a, const int __b) { - return (int8x1_t) __builtin_aarch64_sqrshrun_nhi (__a, __b); + return (int8_t) __builtin_aarch64_sqrshrun_nhi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqrshruns_n_s32 (int32x1_t __a, const int __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqrshruns_n_s32 (int32_t __a, const int __b) { - return (int16x1_t) __builtin_aarch64_sqrshrun_nsi (__a, __b); + return (int16_t) __builtin_aarch64_sqrshrun_nsi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) vqrshrund_n_s64 (int64x1_t __a, const int __b) { - return (int32x1_t) __builtin_aarch64_sqrshrun_ndi (__a, __b); + return (int32_t) __builtin_aarch64_sqrshrun_ndi (__a, __b); } /* vqshl */ @@ -20134,20 +20128,20 @@ vqshlq_u64 (uint64x2_t __a, int64x2_t __b) return __builtin_aarch64_uqshlv2di_uus ( __a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqshlb_s8 (int8x1_t __a, int8x1_t __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqshlb_s8 (int8_t __a, int8_t __b) { return __builtin_aarch64_sqshlqi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqshlh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqshlh_s16 (int16_t __a, int16_t __b) { return __builtin_aarch64_sqshlhi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqshls_s32 (int32x1_t __a, int32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqshls_s32 (int32_t __a, int32_t __b) { return __builtin_aarch64_sqshlsi (__a, __b); } @@ -20158,20 +20152,20 @@ vqshld_s64 (int64x1_t __a, int64x1_t __b) return __builtin_aarch64_sqshldi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqshlb_u8 (uint8x1_t __a, uint8x1_t __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqshlb_u8 (uint8_t __a, uint8_t __b) { return __builtin_aarch64_uqshlqi_uus (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqshlh_u16 (uint16x1_t __a, uint16x1_t __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqshlh_u16 (uint16_t __a, uint16_t __b) { return __builtin_aarch64_uqshlhi_uus (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -vqshls_u32 (uint32x1_t __a, uint32x1_t __b) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vqshls_u32 (uint32_t __a, uint32_t __b) { return __builtin_aarch64_uqshlsi_uus (__a, __b); } @@ -20278,22 +20272,22 @@ vqshlq_n_u64 (uint64x2_t __a, const int __b) return __builtin_aarch64_uqshl_nv2di_uus (__a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqshlb_n_s8 (int8x1_t __a, const int __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqshlb_n_s8 (int8_t __a, const int __b) { - return (int8x1_t) __builtin_aarch64_sqshl_nqi (__a, __b); + return (int8_t) __builtin_aarch64_sqshl_nqi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqshlh_n_s16 (int16x1_t __a, const int __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqshlh_n_s16 (int16_t __a, const int __b) { - return (int16x1_t) __builtin_aarch64_sqshl_nhi (__a, __b); + return (int16_t) __builtin_aarch64_sqshl_nhi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqshls_n_s32 (int32x1_t __a, const int __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqshls_n_s32 (int32_t __a, const int __b) { - return (int32x1_t) __builtin_aarch64_sqshl_nsi (__a, __b); + return (int32_t) __builtin_aarch64_sqshl_nsi (__a, __b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) @@ -20302,20 +20296,20 @@ vqshld_n_s64 (int64x1_t __a, const int __b) return (int64x1_t) __builtin_aarch64_sqshl_ndi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqshlb_n_u8 (uint8x1_t __a, const int __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqshlb_n_u8 (uint8_t __a, const int __b) { return __builtin_aarch64_uqshl_nqi_uus (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqshlh_n_u16 (uint16x1_t __a, const int __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqshlh_n_u16 (uint16_t __a, const int __b) { return __builtin_aarch64_uqshl_nhi_uus (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -vqshls_n_u32 (uint32x1_t __a, const int __b) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vqshls_n_u32 (uint32_t __a, const int __b) { return __builtin_aarch64_uqshl_nsi_uus (__a, __b); } @@ -20376,22 +20370,22 @@ vqshluq_n_s64 (int64x2_t __a, const int __b) return __builtin_aarch64_sqshlu_nv2di_uss (__a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqshlub_n_s8 (int8x1_t __a, const int __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqshlub_n_s8 (int8_t __a, const int __b) { - return (int8x1_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b); + return (int8_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqshluh_n_s16 (int16x1_t __a, const int __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqshluh_n_s16 (int16_t __a, const int __b) { - return (int16x1_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b); + return (int16_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqshlus_n_s32 (int32x1_t __a, const int __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqshlus_n_s32 (int32_t __a, const int __b) { - return (int32x1_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b); + return (int32_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) @@ -20438,37 +20432,37 @@ vqshrn_n_u64 (uint64x2_t __a, const int __b) return __builtin_aarch64_uqshrn_nv2di_uus ( __a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqshrnh_n_s16 (int16x1_t __a, const int __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqshrnh_n_s16 (int16_t __a, const int __b) { - return (int8x1_t) __builtin_aarch64_sqshrn_nhi (__a, __b); + return (int8_t) __builtin_aarch64_sqshrn_nhi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqshrns_n_s32 (int32x1_t __a, const int __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqshrns_n_s32 (int32_t __a, const int __b) { - return (int16x1_t) __builtin_aarch64_sqshrn_nsi (__a, __b); + return (int16_t) __builtin_aarch64_sqshrn_nsi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) vqshrnd_n_s64 (int64x1_t __a, const int __b) { - return (int32x1_t) __builtin_aarch64_sqshrn_ndi (__a, __b); + return (int32_t) __builtin_aarch64_sqshrn_ndi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqshrnh_n_u16 (uint16x1_t __a, const int __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqshrnh_n_u16 (uint16_t __a, const int __b) { return __builtin_aarch64_uqshrn_nhi_uus (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqshrns_n_u32 (uint32x1_t __a, const int __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqshrns_n_u32 (uint32_t __a, const int __b) { return __builtin_aarch64_uqshrn_nsi_uus (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vqshrnd_n_u64 (uint64x1_t __a, const int __b) { return __builtin_aarch64_uqshrn_ndi_uus (__a, __b); @@ -20494,42 +20488,42 @@ vqshrun_n_s64 (int64x2_t __a, const int __b) return (uint32x2_t) __builtin_aarch64_sqshrun_nv2di (__a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqshrunh_n_s16 (int16x1_t __a, const int __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqshrunh_n_s16 (int16_t __a, const int __b) { - return (int8x1_t) __builtin_aarch64_sqshrun_nhi (__a, __b); + return (int8_t) __builtin_aarch64_sqshrun_nhi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqshruns_n_s32 (int32x1_t __a, const int __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqshruns_n_s32 (int32_t __a, const int __b) { - return (int16x1_t) __builtin_aarch64_sqshrun_nsi (__a, __b); + return (int16_t) __builtin_aarch64_sqshrun_nsi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) vqshrund_n_s64 (int64x1_t __a, const int __b) { - return (int32x1_t) __builtin_aarch64_sqshrun_ndi (__a, __b); + return (int32_t) __builtin_aarch64_sqshrun_ndi (__a, __b); } /* vqsub */ -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vqsubb_s8 (int8x1_t __a, int8x1_t __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vqsubb_s8 (int8_t __a, int8_t __b) { - return (int8x1_t) __builtin_aarch64_sqsubqi (__a, __b); + return (int8_t) __builtin_aarch64_sqsubqi (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vqsubh_s16 (int16x1_t __a, int16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vqsubh_s16 (int16_t __a, int16_t __b) { - return (int16x1_t) __builtin_aarch64_sqsubhi (__a, __b); + return (int16_t) __builtin_aarch64_sqsubhi (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vqsubs_s32 (int32x1_t __a, int32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vqsubs_s32 (int32_t __a, int32_t __b) { - return (int32x1_t) __builtin_aarch64_sqsubsi (__a, __b); + return (int32_t) __builtin_aarch64_sqsubsi (__a, __b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) @@ -20538,22 +20532,22 @@ vqsubd_s64 (int64x1_t __a, int64x1_t __b) return (int64x1_t) __builtin_aarch64_sqsubdi (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vqsubb_u8 (uint8x1_t __a, uint8x1_t __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vqsubb_u8 (uint8_t __a, uint8_t __b) { - return (uint8x1_t) __builtin_aarch64_uqsubqi_uuu (__a, __b); + return (uint8_t) __builtin_aarch64_uqsubqi_uuu (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vqsubh_u16 (uint16x1_t __a, uint16x1_t __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vqsubh_u16 (uint16_t __a, uint16_t __b) { - return (uint16x1_t) __builtin_aarch64_uqsubhi_uuu (__a, __b); + return (uint16_t) __builtin_aarch64_uqsubhi_uuu (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -vqsubs_u32 (uint32x1_t __a, uint32x1_t __b) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vqsubs_u32 (uint32_t __a, uint32_t __b) { - return (uint32x1_t) __builtin_aarch64_uqsubsi_uuu (__a, __b); + return (uint32_t) __builtin_aarch64_uqsubsi_uuu (__a, __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) @@ -22056,20 +22050,20 @@ vsqaddq_u64 (uint64x2_t __a, int64x2_t __b) return __builtin_aarch64_usqaddv2di_uus (__a, __b); } -__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -vsqaddb_u8 (uint8x1_t __a, int8x1_t __b) +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vsqaddb_u8 (uint8_t __a, int8_t __b) { return __builtin_aarch64_usqaddqi_uus (__a, __b); } -__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -vsqaddh_u16 (uint16x1_t __a, int16x1_t __b) +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vsqaddh_u16 (uint16_t __a, int16_t __b) { return __builtin_aarch64_usqaddhi_uus (__a, __b); } -__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -vsqadds_u32 (uint32x1_t __a, int32x1_t __b) +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vsqadds_u32 (uint32_t __a, int32_t __b) { return __builtin_aarch64_usqaddsi_uus (__a, __b); } @@ -24127,20 +24121,20 @@ vuqaddq_s64 (int64x2_t __a, uint64x2_t __b) return __builtin_aarch64_suqaddv2di_ssu (__a, __b); } -__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -vuqaddb_s8 (int8x1_t __a, uint8x1_t __b) +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vuqaddb_s8 (int8_t __a, uint8_t __b) { return __builtin_aarch64_suqaddqi_ssu (__a, __b); } -__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -vuqaddh_s16 (int16x1_t __a, uint16x1_t __b) +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vuqaddh_s16 (int16_t __a, uint16_t __b) { return __builtin_aarch64_suqaddhi_ssu (__a, __b); } -__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -vuqadds_s32 (int32x1_t __a, uint32x1_t __b) +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vuqadds_s32 (int32_t __a, uint32_t __b) { return __builtin_aarch64_suqaddsi_ssu (__a, __b); } diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 36e1aa590d8..6edc8d17454 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -66,6 +66,12 @@ ;; Quad vector modes. (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF]) +;; VQ without 2 element modes. +(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF]) + +;; Quad vector with only 2 element modes. +(define_mode_iterator VQ_2E [V2DI V2DF]) + ;; All vector modes, except double. (define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI]) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 1ea249e9278..76352f8357c 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -56,6 +56,7 @@ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, extern int legitimate_pic_operand_p (rtx); extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); extern rtx legitimize_tls_address (rtx, rtx); +extern bool arm_legitimate_address_p (enum machine_mode, rtx, bool); extern int arm_legitimate_address_outer_p (enum machine_mode, rtx, RTX_CODE, int); extern int thumb_legitimate_offset_p (enum machine_mode, HOST_WIDE_INT); extern bool arm_legitimize_reload_address (rtx *, enum machine_mode, int, int, @@ -298,4 +299,6 @@ extern void arm_emit_eabi_attribute (const char *, int, int); /* Defined in gcc/common/config/arm-common.c. */ extern const char *arm_rewrite_selected_cpu (const char *name); +extern bool arm_is_constant_pool_ref (rtx); + #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e38c44fc326..8bb4ba6602f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -91,7 +91,6 @@ static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); static reg_class_t arm_preferred_reload_class (rtx, reg_class_t); static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); inline static int thumb1_index_register_rtx_p (rtx, int); -static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); static int thumb_far_jump_used_p (void); static bool thumb_force_lr_save (void); static unsigned arm_size_return_regs (void); @@ -31689,4 +31688,13 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) reload_fenv, restore_fnenv), update_call); } +/* return TRUE if x is a reference to a value in a constant pool */ +extern bool +arm_is_constant_pool_ref (rtx x) +{ + return (MEM_P (x) + && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))); +} + #include "gt-arm.h" diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 86fe5977aa9..f3a3eba69b0 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3643,7 +3643,7 @@ [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "s_register_operand" "r")])) (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT && optimize_function_for_size_p (cfun)" + "TARGET_32BIT && optimize_function_for_size_p (cfun) && !arm_restrict_it" "* operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode, operands[1], operands[2]); @@ -4386,7 +4386,7 @@ (define_insn "unaligned_loadhis" [(set (match_operand:SI 0 "s_register_operand" "=l,r") (sign_extend:SI - (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")] + (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,Uh")] UNSPEC_UNALIGNED_LOAD)))] "unaligned_access && TARGET_32BIT" "ldr%(sh%)\t%0, %1\t@ unaligned" @@ -5299,7 +5299,7 @@ (define_insn "*arm_zero_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch6" "@ uxth%?\\t%0, %1 @@ -5393,7 +5393,7 @@ (define_insn "*arm_zero_extendqisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch6" "@ uxtb%(%)\\t%0, %1 @@ -5627,31 +5627,27 @@ (define_insn "*arm_extendhisi2" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch4 && !arm_arch6" "@ # ldr%(sh%)\\t%0, %1" [(set_attr "length" "8,4") (set_attr "type" "alu_shift_reg,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) ;; ??? Check Thumb-2 pool range (define_insn "*arm_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_32BIT && arm_arch6" "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable_short_it" "no")] ) (define_insn "*arm_extendhisi2addsi" @@ -5694,9 +5690,7 @@ "TARGET_ARM && arm_arch4" "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "256") - (set_attr "neg_pool_range" "244")] + (set_attr "predicable" "yes")] ) (define_expand "extendqisi2" @@ -5736,9 +5730,7 @@ ldr%(sb%)\\t%0, %1" [(set_attr "length" "8,4") (set_attr "type" "alu_shift_reg,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendqisi_v6" @@ -5750,9 +5742,7 @@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" [(set_attr "type" "extend,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendqisi2addsi" diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 85dd116cec0..f848664d57d 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -36,7 +36,7 @@ ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us +;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us ;; in ARM state: Uq ;; in Thumb state: Uu, Uw @@ -348,6 +348,12 @@ An address valid for loading/storing register exclusive" (match_operand 0 "mem_noofs_operand")) +(define_memory_constraint "Uh" + "@internal + An address suitable for byte and half-word loads which does not point inside a constant pool" + (and (match_code "mem") + (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)"))) + (define_memory_constraint "Ut" "@internal In ARM/Thumb-2 state an address valid for loading/storing opaque structure @@ -394,7 +400,8 @@ (and (match_code "mem") (match_test "TARGET_ARM && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0), - SIGN_EXTEND, 0)"))) + SIGN_EXTEND, 0) + && !arm_is_constant_pool_ref (op)"))) (define_memory_constraint "Q" "@internal diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 3bb2a914a33..2d90b7684d8 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -4931,8 +4931,9 @@ (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")] UNSPEC_INDEX_JMP)) (use (label_ref (match_operand 1 "" ""))) - (clobber (match_dup 0))] - "" + (clobber (match_dup 0)) + (clobber (const_int 0))] + "!AVR_HAVE_EIJMP_EICALL" "@ ijmp push %A0\;push %B0\;ret @@ -4941,6 +4942,19 @@ (set_attr "isa" "rjmp,rjmp,jmp") (set_attr "cc" "none,none,clobber")]) +(define_insn "*tablejump.3byte-pc" + [(set (pc) + (unspec:HI [(reg:HI REG_Z)] + UNSPEC_INDEX_JMP)) + (use (label_ref (match_operand 0 "" ""))) + (clobber (reg:HI REG_Z)) + (clobber (reg:QI 24))] + "AVR_HAVE_EIJMP_EICALL" + "clr r24\;subi r30,pm_lo8(-(%0))\;sbci r31,pm_hi8(-(%0))\;sbci r24,pm_hh8(-(%0))\;jmp __tablejump2__" + [(set_attr "length" "6") + (set_attr "isa" "eijmp") + (set_attr "cc" "clobber")]) + (define_expand "casesi" [(parallel [(set (match_dup 6) @@ -4958,15 +4972,31 @@ (label_ref (match_operand 4 "" "")) (pc))) - (set (match_dup 6) - (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" "")))) + (set (match_dup 10) + (match_dup 7)) - (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP)) + (parallel [(set (pc) + (unspec:HI [(match_dup 10)] UNSPEC_INDEX_JMP)) (use (label_ref (match_dup 3))) - (clobber (match_dup 6))])] + (clobber (match_dup 10)) + (clobber (match_dup 8))])] "" { operands[6] = gen_reg_rtx (HImode); + + if (AVR_HAVE_EIJMP_EICALL) + { + operands[7] = operands[6]; + operands[8] = all_regs_rtx[24]; + operands[10] = gen_rtx_REG (HImode, REG_Z); + } + else + { + operands[7] = gen_rtx_PLUS (HImode, operands[6], + gen_rtx_LABEL_REF (VOIDmode, operands[3])); + operands[8] = const0_rtx; + operands[10] = operands[6]; + } }) diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c index 892ba354786..7fe4b1f2e40 100644 --- a/gcc/config/darwin-c.c +++ b/gcc/config/darwin-c.c @@ -571,21 +571,34 @@ find_subframework_header (cpp_reader *pfile, const char *header, cpp_dir **dirp) } /* Return the value of darwin_macosx_version_min suitable for the - __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ macro, - so '10.4.2' becomes 1040. The lowest digit is always zero. + __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ macro, so '10.4.2' + becomes 1040 and '10.10.0' becomes 101000. The lowest digit is + always zero, as is the second lowest for '10.10.x' and above. Print a warning if the version number can't be understood. */ static const char * version_as_macro (void) { - static char result[] = "1000"; + static char result[7] = "1000"; + int minorDigitIdx; if (strncmp (darwin_macosx_version_min, "10.", 3) != 0) goto fail; if (! ISDIGIT (darwin_macosx_version_min[3])) goto fail; - result[2] = darwin_macosx_version_min[3]; - if (darwin_macosx_version_min[4] != '\0' - && darwin_macosx_version_min[4] != '.') + + minorDigitIdx = 3; + result[2] = darwin_macosx_version_min[minorDigitIdx++]; + if (ISDIGIT (darwin_macosx_version_min[minorDigitIdx])) + { + /* Starting with OS X 10.10, the macro ends '00' rather than '0', + i.e. 10.10.x becomes 101000 rather than 10100. */ + result[3] = darwin_macosx_version_min[minorDigitIdx++]; + result[4] = '0'; + result[5] = '0'; + result[6] = '\0'; + } + if (darwin_macosx_version_min[minorDigitIdx] != '\0' + && darwin_macosx_version_min[minorDigitIdx] != '.') goto fail; return result; diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c index 8b6ae93911f..541e10bc098 100644 --- a/gcc/config/darwin-driver.c +++ b/gcc/config/darwin-driver.c @@ -29,8 +29,8 @@ along with GCC; see the file COPYING3. If not see #include <sys/sysctl.h> #include "xregex.h" -static bool -darwin_find_version_from_kernel (char *new_flag) +static char * +darwin_find_version_from_kernel (void) { char osversion[32]; size_t osversion_len = sizeof (osversion) - 1; @@ -39,6 +39,7 @@ darwin_find_version_from_kernel (char *new_flag) char minor_vers[6]; char * version_p; char * version_pend; + char * new_flag; /* Determine the version of the running OS. If we can't, warn user, and do nothing. */ @@ -46,7 +47,7 @@ darwin_find_version_from_kernel (char *new_flag) &osversion_len, NULL, 0) == -1) { warning (0, "sysctl for kern.osversion failed: %m"); - return false; + return NULL; } /* Try to parse the first two parts of the OS version number. Warn @@ -57,8 +58,6 @@ darwin_find_version_from_kernel (char *new_flag) version_p = osversion + 1; if (ISDIGIT (*version_p)) major_vers = major_vers * 10 + (*version_p++ - '0'); - if (major_vers > 4 + 9) - goto parse_failed; if (*version_p++ != '.') goto parse_failed; version_pend = strchr(version_p, '.'); @@ -74,17 +73,16 @@ darwin_find_version_from_kernel (char *new_flag) if (major_vers - 4 <= 4) /* On 10.4 and earlier, the old linker is used which does not support three-component system versions. */ - sprintf (new_flag, "10.%d", major_vers - 4); + asprintf (&new_flag, "10.%d", major_vers - 4); else - sprintf (new_flag, "10.%d.%s", major_vers - 4, - minor_vers); + asprintf (&new_flag, "10.%d.%s", major_vers - 4, minor_vers); - return true; + return new_flag; parse_failed: warning (0, "couldn%'t understand kern.osversion %q.*s", (int) osversion_len, osversion); - return false; + return NULL; } #endif @@ -105,7 +103,7 @@ darwin_default_min_version (unsigned int *decoded_options_count, const unsigned int argc = *decoded_options_count; struct cl_decoded_option *const argv = *decoded_options; unsigned int i; - static char new_flag[sizeof ("10.0.0") + 6]; + const char *new_flag; /* If the command-line is empty, just return. */ if (argc <= 1) @@ -142,16 +140,16 @@ darwin_default_min_version (unsigned int *decoded_options_count, #ifndef CROSS_DIRECTORY_STRUCTURE - /* Try to find the version from the kernel, if we fail - we print a message - and give up. */ - if (!darwin_find_version_from_kernel (new_flag)) - return; + /* Try to find the version from the kernel, if we fail - we print a message + and give up. */ + new_flag = darwin_find_version_from_kernel (); + if (!new_flag) + return; #else - /* For cross-compilers, default to the target OS version. */ - - strncpy (new_flag, DEF_MIN_OSX_VERSION, sizeof (new_flag)); + /* For cross-compilers, default to the target OS version. */ + new_flag = DEF_MIN_OSX_VERSION; #endif /* CROSS_DIRECTORY_STRUCTURE */ @@ -165,7 +163,6 @@ darwin_default_min_version (unsigned int *decoded_options_count, memcpy (*decoded_options + 2, argv + 1, (argc - 1) * sizeof (struct cl_decoded_option)); return; - } /* Translate -filelist and -framework options in *DECODED_OPTIONS diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c7c504c35e1..102334d3d6e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3332,8 +3332,9 @@ ix86_option_override_internal (bool main_args_p, /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is on and OPTION_MASK_ABI_64 is off. We turn off OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by - -m64. */ - if (TARGET_LP64_P (opts->x_ix86_isa_flags)) + -m64 or OPTION_MASK_CODE16 is turned on by -m16. */ + if (TARGET_LP64_P (opts->x_ix86_isa_flags) + || TARGET_16BIT_P (opts->x_ix86_isa_flags)) opts->x_ix86_isa_flags &= ~OPTION_MASK_ABI_X32; #endif } @@ -42703,8 +42704,8 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d) op0 = gen_lowpart (V4DImode, d->op0); op1 = gen_lowpart (V4DImode, d->op1); rperm[0] - = GEN_INT (((d->perm[0] & (nelt / 2)) ? 1 : 0) - || ((d->perm[nelt / 2] & (nelt / 2)) ? 2 : 0)); + = GEN_INT ((d->perm[0] / (nelt / 2)) + | ((d->perm[nelt / 2] / (nelt / 2)) * 16)); emit_insn (gen_avx2_permv2ti (target, op0, op1, rperm[0])); if (target != d->target) emit_move_insn (d->target, gen_lowpart (d->vmode, target)); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index e63be9bf7fe..cd7eadb55d9 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -13496,7 +13496,8 @@ (set (reg:CCFP FPSR_REG) (unspec:CCFP [(match_dup 2) (match_dup 3)] UNSPEC_C2_FLAG))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" "fprem" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -13505,7 +13506,8 @@ [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "general_operand")) (use (match_operand:XF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx label = gen_label_rtx (); @@ -13528,7 +13530,8 @@ [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) (use (match_operand:MODEF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx (*gen_truncxf) (rtx, rtx); @@ -13567,7 +13570,8 @@ (set (reg:CCFP FPSR_REG) (unspec:CCFP [(match_dup 2) (match_dup 3)] UNSPEC_C2_FLAG))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" "fprem1" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -13576,7 +13580,8 @@ [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "general_operand")) (use (match_operand:XF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx label = gen_label_rtx (); @@ -13599,7 +13604,8 @@ [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) (use (match_operand:MODEF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx (*gen_truncxf) (rtx, rtx); diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 5e890ecedc1..3f29d6d62d8 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -559,7 +559,7 @@ [(set (match_operand:PSI 0 "nonimmediate_operand" "=r") (subreg:PSI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")) 0))] "TARGET_LARGE" - "RLAM #4, %0 { RRAM #4, %0" + "RLAM.A #4, %0 { RRAM.A #4, %0" ) ;; Look for cases where integer/pointer conversions are suboptimal due @@ -587,7 +587,7 @@ (ashift:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")) (const_int 1)))] "TARGET_LARGE" - "RLAM #4, %0 { RRAM #3, %0" + "RLAM.A #4, %0 { RRAM.A #3, %0" ) (define_insn "extend_and_shift2_hipsi2" @@ -595,7 +595,7 @@ (ashift:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")) (const_int 2)))] "TARGET_LARGE" - "RLAM #4, %0 { RRAM #2, %0" + "RLAM.A #4, %0 { RRAM.A #2, %0" ) ; Nasty - we are sign-extending a 20-bit PSI value in one register into diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 28978bb1684..80198206851 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -4208,9 +4208,12 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { last_address = extra_nop ? 4 : 0; insn = get_last_nonnote_insn (); - last_address += INSN_ADDRESSES (INSN_UID (insn)); - if (INSN_P (insn)) - last_address += insn_default_length (insn); + if (insn) + { + last_address += INSN_ADDRESSES (INSN_UID (insn)); + if (INSN_P (insn)) + last_address += insn_default_length (insn); + } last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); } @@ -9313,6 +9316,12 @@ pa_function_value (const_tree valtype, || TREE_CODE (valtype) == COMPLEX_TYPE || TREE_CODE (valtype) == VECTOR_TYPE) { + HOST_WIDE_INT valsize = int_size_in_bytes (valtype); + + /* Handle aggregates that fit exactly in a word or double word. */ + if ((valsize & (UNITS_PER_WORD - 1)) == 0) + return gen_rtx_REG (TYPE_MODE (valtype), 28); + if (TARGET_64BIT) { /* Aggregates with a size less than or equal to 128 bits are @@ -9321,7 +9330,7 @@ pa_function_value (const_tree valtype, memory. */ rtx loc[2]; int i, offset = 0; - int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; + int ub = valsize <= UNITS_PER_WORD ? 1 : 2; for (i = 0; i < ub; i++) { @@ -9333,7 +9342,7 @@ pa_function_value (const_tree valtype, return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); } - else if (int_size_in_bytes (valtype) > UNITS_PER_WORD) + else if (valsize > UNITS_PER_WORD) { /* Aggregates 5 to 8 bytes in size are returned in general registers r28-r29 in the same manner as other non diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 8c384b3808a..2f40462159e 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1783,7 +1783,7 @@ (define_predicate "fusion_gpr_mem_load" (match_code "mem,sign_extend,zero_extend") { - rtx addr; + rtx addr, base, offset; /* Handle sign/zero extend. */ if (GET_CODE (op) == ZERO_EXTEND @@ -1813,24 +1813,79 @@ } addr = XEXP (op, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return 0; + + base = XEXP (addr, 0); + if (!base_reg_operand (base, GET_MODE (base))) + return 0; + + offset = XEXP (addr, 1); + if (GET_CODE (addr) == PLUS) + return satisfies_constraint_I (offset); + + else if (GET_CODE (addr) == LO_SUM) { - rtx base = XEXP (addr, 0); - rtx offset = XEXP (addr, 1); + if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + return small_toc_ref (offset, GET_MODE (offset)); - return (base_reg_operand (base, GET_MODE (base)) - && satisfies_constraint_I (offset)); + else if (TARGET_ELF && !TARGET_POWERPC64) + return CONSTANT_P (offset); } - else if (GET_CODE (addr) == LO_SUM) + return 0; +}) + +;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the +;; memory field with both the addis and the memory offset. Sign extension +;; is not handled here, since lha and lwa are not fused. +(define_predicate "fusion_gpr_mem_combo" + (match_code "mem,zero_extend") +{ + rtx addr, base, offset; + + /* Handle zero extend. */ + if (GET_CODE (op) == ZERO_EXTEND) { - rtx base = XEXP (addr, 0); - rtx offset = XEXP (addr, 1); + op = XEXP (op, 0); + mode = GET_MODE (op); + } + + if (!MEM_P (op)) + return 0; - if (!base_reg_operand (base, GET_MODE (base))) + switch (mode) + { + case QImode: + case HImode: + case SImode: + break; + + case DImode: + if (!TARGET_POWERPC64) return 0; + break; - else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + default: + return 0; + } + + addr = XEXP (op, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return 0; + + base = XEXP (addr, 0); + if (!fusion_gpr_addis (base, GET_MODE (base))) + return 0; + + offset = XEXP (addr, 1); + if (GET_CODE (addr) == PLUS) + return satisfies_constraint_I (offset); + + else if (GET_CODE (addr) == LO_SUM) + { + if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) return small_toc_ref (offset, GET_MODE (offset)); else if (TARGET_ELF && !TARGET_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 46c4a9d8c2e..016be9e10bd 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4128,7 +4128,8 @@ altivec_build_resolved_builtin (tree *args, int n, argument) is reversed. Patch the arguments here before building the resolved CALL_EXPR. */ if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P - && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P) + && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P + && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P) { tree t; t = args[2], args[2] = args[1], args[1] = t; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 067a74aa679..e1355b3a615 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -79,9 +79,9 @@ extern int mems_ok_for_quad_peep (rtx, rtx); extern bool gpr_or_gpr_p (rtx, rtx); extern bool direct_move_p (rtx, rtx); extern bool quad_load_store_p (rtx, rtx); -extern bool fusion_gpr_load_p (rtx *, bool); +extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx); extern void expand_fusion_gpr_load (rtx *); -extern const char *emit_fusion_gpr_load (rtx *); +extern const char *emit_fusion_gpr_load (rtx, rtx); extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class); extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 28ccf86df19..bad4a1b2217 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -32755,25 +32755,14 @@ rs6000_split_logical (rtx operands[3], /* Return true if the peephole2 can combine a load involving a combination of an addis instruction and a load with an offset that can be fused together on - a power8. - - The operands are: - operands[0] register set with addis - operands[1] value set via addis - operands[2] target register being loaded - operands[3] D-form memory reference using operands[0]. - - In addition, we are passed a boolean that is true if this is a peephole2, - and we can use see if the addis_reg is dead after the insn and can be - replaced by the target register. */ + a power8. */ bool -fusion_gpr_load_p (rtx *operands, bool peep2_p) +fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */ + rtx addis_value, /* addis value. */ + rtx target, /* target register that is loaded. */ + rtx mem) /* bottom part of the memory addr. */ { - rtx addis_reg = operands[0]; - rtx addis_value = operands[1]; - rtx target = operands[2]; - rtx mem = operands[3]; rtx addr; rtx base_reg; @@ -32787,9 +32776,6 @@ fusion_gpr_load_p (rtx *operands, bool peep2_p) if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value))) return false; - if (!fusion_gpr_mem_load (mem, GET_MODE (mem))) - return false; - /* Allow sign/zero extension. */ if (GET_CODE (mem) == ZERO_EXTEND || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN)) @@ -32798,22 +32784,22 @@ fusion_gpr_load_p (rtx *operands, bool peep2_p) if (!MEM_P (mem)) return false; + if (!fusion_gpr_mem_load (mem, GET_MODE (mem))) + return false; + addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) return false; /* Validate that the register used to load the high value is either the - register being loaded, or we can safely replace its use in a peephole2. + register being loaded, or we can safely replace its use. - If this is a peephole2, we assume that there are 2 instructions in the - peephole (addis and load), so we want to check if the target register was - not used in the memory address and the register to hold the addis result - is dead after the peephole. */ + This function is only called from the peephole2 pass and we assume that + there are 2 instructions in the peephole (addis and load), so we want to + check if the target register was not used in the memory address and the + register to hold the addis result is dead after the peephole. */ if (REGNO (addis_reg) != REGNO (target)) { - if (!peep2_p) - return false; - if (reg_mentioned_p (target, mem)) return false; @@ -32854,9 +32840,6 @@ expand_fusion_gpr_load (rtx *operands) enum machine_mode extend_mode = target_mode; enum machine_mode ptr_mode = Pmode; enum rtx_code extend = UNKNOWN; - rtx addis_reg = ((ptr_mode == target_mode) - ? target - : simplify_subreg (ptr_mode, target, target_mode, 0)); if (GET_CODE (orig_mem) == ZERO_EXTEND || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND)) @@ -32873,13 +32856,14 @@ expand_fusion_gpr_load (rtx *operands) gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM); offset = XEXP (orig_addr, 1); - new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_reg, offset); - new_mem = change_address (orig_mem, target_mode, new_addr); + new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset); + new_mem = replace_equiv_address_nv (orig_mem, new_addr); if (extend != UNKNOWN) new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem); - emit_insn (gen_rtx_SET (VOIDmode, addis_reg, addis_value)); + new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem), + UNSPEC_FUSION_GPR); emit_insn (gen_rtx_SET (VOIDmode, target, new_mem)); if (extend == SIGN_EXTEND) @@ -32898,55 +32882,40 @@ expand_fusion_gpr_load (rtx *operands) } /* Return a string to fuse an addis instruction with a gpr load to the same - register that we loaded up the addis instruction. The code is complicated, - so we call output_asm_insn directly, and just return "". + register that we loaded up the addis instruction. The address that is used + is the logical address that was formed during peephole2: + (lo_sum (high) (low-part)) - The operands are: - operands[0] register set with addis (must be same reg as target). - operands[1] value set via addis - operands[2] target register being loaded - operands[3] D-form memory reference using operands[0]. */ + The code is complicated, so we call output_asm_insn directly, and just + return "". */ const char * -emit_fusion_gpr_load (rtx *operands) +emit_fusion_gpr_load (rtx target, rtx mem) { - rtx addis_reg = operands[0]; - rtx addis_value = operands[1]; - rtx target = operands[2]; - rtx mem = operands[3]; + rtx addis_value; rtx fuse_ops[10]; rtx addr; rtx load_offset; const char *addis_str = NULL; const char *load_str = NULL; - const char *extend_insn = NULL; const char *mode_name = NULL; char insn_template[80]; enum machine_mode mode; const char *comment_str = ASM_COMMENT_START; - bool sign_p = false; - - gcc_assert (REG_P (addis_reg) && REG_P (target)); - gcc_assert (REGNO (addis_reg) == REGNO (target)); - - if (*comment_str == ' ') - comment_str++; - /* Allow sign/zero extension. */ if (GET_CODE (mem) == ZERO_EXTEND) mem = XEXP (mem, 0); - else if (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN) - { - sign_p = true; - mem = XEXP (mem, 0); - } + gcc_assert (REG_P (target) && MEM_P (mem)); + + if (*comment_str == ' ') + comment_str++; - gcc_assert (MEM_P (mem)); addr = XEXP (mem, 0); if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) gcc_unreachable (); + addis_value = XEXP (addr, 0); load_offset = XEXP (addr, 1); /* Now emit the load instruction to the same register. */ @@ -32956,29 +32925,22 @@ emit_fusion_gpr_load (rtx *operands) case QImode: mode_name = "char"; load_str = "lbz"; - extend_insn = "extsb %0,%0"; break; case HImode: mode_name = "short"; load_str = "lhz"; - extend_insn = "extsh %0,%0"; break; case SImode: mode_name = "int"; load_str = "lwz"; - extend_insn = "extsw %0,%0"; break; case DImode: - if (TARGET_POWERPC64) - { - mode_name = "long"; - load_str = "ld"; - } - else - gcc_unreachable (); + gcc_assert (TARGET_POWERPC64); + mode_name = "long"; + load_str = "ld"; break; default: @@ -33122,14 +33084,6 @@ emit_fusion_gpr_load (rtx *operands) else fatal_insn ("Unable to generate load offset for fusion", load_offset); - /* Handle sign extension. The peephole2 pass generates this as a separate - insn, but we handle it just in case it got reattached. */ - if (sign_p) - { - gcc_assert (extend_insn != NULL); - output_asm_insn (extend_insn, fuse_ops); - } - return ""; } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d078491e1f2..46837e15389 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -137,6 +137,7 @@ UNSPEC_UNPACK_128BIT UNSPEC_PACK_128BIT UNSPEC_LSQ + UNSPEC_FUSION_GPR ]) ;; @@ -328,8 +329,25 @@ (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")]) ; Definitions for 32-bit fpr direct move +; At present, the decimal modes are not allowed in the traditional altivec +; registers, so restrict the constraints to just the traditional FPRs. (define_mode_attr f32_dm [(SF "wn") (SD "wh")]) +; Definitions for 32-bit VSX +(define_mode_attr f32_vsx [(SF "ww") (SD "wn")]) + +; Definitions for 32-bit use of altivec registers +(define_mode_attr f32_av [(SF "wu") (SD "wn")]) + +; Definitions for 64-bit VSX +(define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) + +; Definitions for 64-bit direct move +(define_mode_attr f64_dm [(DF "wk") (DD "wh")]) + +; Definitions for 64-bit use of altivec registers +(define_mode_attr f64_av [(DF "wv") (DD "wn")]) + ; These modes do not fit in integer registers in 32-bit mode. ; but on e500v2, the gpr are 64 bit registers (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD]) @@ -435,7 +453,7 @@ ;; either. ;; Mode attribute for boolean operation register constraints for output -(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v") +(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v") (PTI "&r,r,r") (V16QI "wa,v,&?r,?r,?r") (V8HI "wa,v,&?r,?r,?r") @@ -446,7 +464,7 @@ (V1TI "wa,v,&?r,?r,?r")]) ;; Mode attribute for boolean operation register constraints for operand1 -(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v") +(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v") (PTI "r,0,r") (V16QI "wa,v,r,0,r") (V8HI "wa,v,r,0,r") @@ -457,7 +475,7 @@ (V1TI "wa,v,r,0,r")]) ;; Mode attribute for boolean operation register constraints for operand2 -(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v") +(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v") (PTI "r,r,0") (V16QI "wa,v,r,r,0") (V8HI "wa,v,r,r,0") @@ -470,7 +488,7 @@ ;; Mode attribute for boolean operation register constraints for operand1 ;; for one_cmpl. To simplify things, we repeat the constraint where 0 ;; is used for operand1 or operand2 -(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v") +(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v") (PTI "r,0,0") (V16QI "wa,v,r,0,0") (V8HI "wa,v,r,0,0") @@ -9188,8 +9206,8 @@ }") (define_insn "mov<mode>_hardfloat" - [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r") - (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))] + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r") + (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r, h, 0, G,Fn"))] "(gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode)) && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" @@ -9390,8 +9408,8 @@ ;; reloading. (define_insn "*mov<mode>_hardfloat32" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -9459,8 +9477,8 @@ ; ld/std require word-aligned displacements -> 'Y' constraint. ; List Y->r and r->Y before r->r for reload. (define_insn "*mov<mode>_hardfloat64" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -15714,22 +15732,9 @@ ;; a GPR. The addis instruction must be adjacent to the load, and use the same ;; register that is being loaded. The fused ops must be physically adjacent. -;; We use define_peephole for the actual addis/load, and the register used to -;; hold the addis value must be the same as the register being loaded. We use -;; define_peephole2 to change the register used for addis to be the register -;; being loaded, since we can look at whether it is dead after the load insn. - -(define_peephole - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:INT1 2 "base_reg_operand" "") - (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] - "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)" -{ - return emit_fusion_gpr_load (operands); -} - [(set_attr "type" "load") - (set_attr "length" "8")]) +;; Find cases where the addis that feeds into a load instruction is either used +;; once or is the same as the target register, and replace it with the fusion +;; insn (define_peephole2 [(set (match_operand:P 0 "base_reg_operand" "") @@ -15737,15 +15742,28 @@ (set (match_operand:INT1 2 "base_reg_operand" "") (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] "TARGET_P8_FUSION - && (REGNO (operands[0]) != REGNO (operands[2]) - || GET_CODE (operands[3]) == SIGN_EXTEND) - && fusion_gpr_load_p (operands, true)" + && fusion_gpr_load_p (operands[0], operands[1], operands[2], + operands[3])" [(const_int 0)] { expand_fusion_gpr_load (operands); DONE; }) +;; Fusion insn, created by the define_peephole2 above (and eventually by +;; reload) + +(define_insn "fusion_gpr_load_<mode>" + [(set (match_operand:INT1 0 "base_reg_operand" "=&b") + (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")] + UNSPEC_FUSION_GPR))] + "TARGET_P8_FUSION" +{ + return emit_fusion_gpr_load (operands[0], operands[1]); +} + [(set_attr "type" "load") + (set_attr "length" "8")]) + ;; Miscellaneous ISA 2.06 (power7) instructions (define_insn "addg6s" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2cf5e7a9490..84bf81a85af 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -904,11 +904,11 @@ ;; multiply. (define_insn "*vsx_fmav4sf4" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v") (fma:V4SF - (match_operand:V4SF 1 "vsx_register_operand" "%ws,ws,wa,wa,v") - (match_operand:V4SF 2 "vsx_register_operand" "ws,0,wa,0,v") - (match_operand:V4SF 3 "vsx_register_operand" "0,ws,0,wa,v")))] + (match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v") + (match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v") + (match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))] "VECTOR_UNIT_VSX_P (V4SFmode)" "@ xvmaddasp %x0,%x1,%x2 @@ -919,11 +919,11 @@ [(set_attr "type" "vecfloat")]) (define_insn "*vsx_fmav2df4" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa") + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,wd,?wa,?wa") (fma:V2DF - (match_operand:V2DF 1 "vsx_register_operand" "%ws,ws,wa,wa") - (match_operand:V2DF 2 "vsx_register_operand" "ws,0,wa,0") - (match_operand:V2DF 3 "vsx_register_operand" "0,ws,0,wa")))] + (match_operand:V2DF 1 "vsx_register_operand" "%wd,wd,wa,wa") + (match_operand:V2DF 2 "vsx_register_operand" "wd,0,wa,0") + (match_operand:V2DF 3 "vsx_register_operand" "0,wd,0,wa")))] "VECTOR_UNIT_VSX_P (V2DFmode)" "@ xvmaddadp %x0,%x1,%x2 @@ -1359,8 +1359,8 @@ (define_insn "vsx_concat_<mode>" [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?<VSa>") (vec_concat:VSX_D - (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,<VSa>") - (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,<VSa>")))] + (match_operand:<VS_scalar> 1 "vsx_register_operand" "<VS_64reg>,<VSa>") + (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" { if (BYTES_BIG_ENDIAN) @@ -1647,7 +1647,7 @@ [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,wv,wr") (vec_select:<VS_scalar> (match_operand:VSX_D 1 "memory_operand" "m,Z,m") - (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] + (parallel [(const_int 0)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ lfd%U1%X1 %0,%1 @@ -2041,7 +2041,7 @@ ;; to the top element of the V2DF array without doing an extract. (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar" - [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?wa,ws,?wa") + [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws") (vec_select:DF (VEC_reduc:V2DF (vec_concat:V2DF diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index aac8de848ac..866de858cf0 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -9130,11 +9130,14 @@ s390_emit_epilogue (bool sibcall) if (! sibcall) { /* Fetch return address from stack before load multiple, - this will do good for scheduling. */ - - if (cfun_frame_layout.save_return_addr_p - || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM - && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM)) + this will do good for scheduling. + + Only do this if we already decided that r14 needs to be + saved to a stack slot. (And not just because r14 happens to + be in between two GPRs which need saving.) Otherwise it + would be difficult to take that decision back in + s390_optimize_prologue. */ + if (cfun_gpr_save_slot (RETURN_REGNUM) == -1) { int return_regnum = find_unused_clobbered_reg(); if (!return_regnum) @@ -9149,6 +9152,12 @@ s390_emit_epilogue (bool sibcall) addr = gen_rtx_MEM (Pmode, addr); set_mem_alias_set (addr, get_frame_alias_set ()); emit_move_insn (return_reg, addr); + + /* Once we did that optimization we have to make sure + s390_optimize_prologue does not try to remove the + store of r14 since we will not be able to find the + load issued here. */ + cfun_frame_layout.save_return_addr_p = true; } } diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md index a0a22a1f5b7..a3acaac5617 100644 --- a/gcc/config/sh/sync.md +++ b/gcc/config/sh/sync.md @@ -466,6 +466,7 @@ (set (mem:SI (match_dup 1)) (unspec:SI [(match_operand:SI 2 "arith_operand" "rI08")] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" @@ -484,6 +485,7 @@ (set (mem:QIHI (match_dup 1)) (unspec:QIHI [(match_operand:QIHI 2 "register_operand" "r")] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -617,6 +619,7 @@ [(FETCHOP:SI (mem:SI (match_dup 1)) (match_operand:SI 2 "<fetchop_predicate>" "<fetchop_constraint>"))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" @@ -637,6 +640,7 @@ [(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_operand:QIHI 2 "<fetchop_predicate>" "<fetchop_constraint>"))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -784,6 +788,7 @@ [(not:SI (and:SI (mem:SI (match_dup 1)) (match_operand:SI 2 "logical_operand" "rK08")))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" @@ -805,6 +810,7 @@ [(not:QIHI (and:QIHI (mem:QIHI (match_dup 1)) (match_operand:QIHI 2 "logical_operand" "rK08")))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -903,7 +909,7 @@ " and %0,%3" "\n" " not %3,%3" "\n" " mov.<bwl> %3,@%1" "\n" - " stc %4,sr"; + " ldc %4,sr"; } [(set_attr "length" "20")]) @@ -960,7 +966,8 @@ (set (mem:SI (match_dup 1)) (unspec:SI [(FETCHOP:SI (mem:SI (match_dup 1)) (match_dup 2))] - UNSPEC_ATOMIC))] + UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { @@ -980,6 +987,7 @@ (unspec:QIHI [(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_dup 2))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -1124,7 +1132,8 @@ (set (mem:SI (match_dup 1)) (unspec:SI [(not:SI (and:SI (mem:SI (match_dup 1)) (match_dup 2)))] - UNSPEC_ATOMIC))] + UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { @@ -1145,6 +1154,7 @@ (unspec:QIHI [(not:QIHI (and:QIHI (mem:QIHI (match_dup 1)) (match_dup 2)))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -1353,7 +1363,7 @@ " ldc r0,sr" "\n" " mov.b @%0,r0" "\n" " mov.b %1,@%0" "\n" - " stc %2,sr" "\n" + " ldc %2,sr" "\n" " tst r0,r0"; } [(set_attr "length" "16")]) diff --git a/gcc/configure b/gcc/configure index 40b7bca07d5..23e873aaf53 100755 --- a/gcc/configure +++ b/gcc/configure @@ -919,6 +919,7 @@ with_plugin_ld enable_gnu_indirect_function enable_initfini_array enable_comdat +enable_fix_cortex_a53_835769 with_glibc_version enable_gnu_unique_object enable_linker_build_id @@ -1635,6 +1636,14 @@ Optional Features: glibc systems --enable-initfini-array use .init_array/.fini_array sections --enable-comdat enable COMDAT group support + + --enable-fix-cortex-a53-835769 + enable workaround for AArch64 Cortex-A53 erratum + 835769 by default + --disable-fix-cortex-a53-835769 + disable workaround for AArch64 Cortex-A53 erratum + 835769 by default + --enable-gnu-unique-object enable the use of the @gnu_unique_object ELF extension on glibc systems @@ -17928,7 +17937,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 17931 "configure" +#line 17940 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -18034,7 +18043,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 18037 "configure" +#line 18046 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -24005,6 +24014,25 @@ $as_echo "#define HAVE_AS_MABI_OPTION 1" >>confdefs.h done fi fi + # Enable default workaround for AArch64 Cortex-A53 erratum 835769. + # Check whether --enable-fix-cortex-a53-835769 was given. +if test "${enable_fix_cortex_a53_835769+set}" = set; then : + enableval=$enable_fix_cortex_a53_835769; + case $enableval in + yes) + tm_defines="${tm_defines} TARGET_FIX_ERR_A53_835769_DEFAULT=1" + ;; + no) + ;; + *) + as_fn_error "'$enableval' is an invalid value for --enable-fix-cortex-a53-835769.\ + Valid choices are 'yes' and 'no'." "$LINENO" 5 + ;; + + esac + +fi + ;; # All TARGET_ABI_OSF targets. diff --git a/gcc/configure.ac b/gcc/configure.ac index 96ea0820645..f2d11db3955 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3541,6 +3541,29 @@ case "$target" in done fi fi + # Enable default workaround for AArch64 Cortex-A53 erratum 835769. + AC_ARG_ENABLE(fix-cortex-a53-835769, + [ +AS_HELP_STRING([--enable-fix-cortex-a53-835769], + [enable workaround for AArch64 Cortex-A53 erratum 835769 by default]) +AS_HELP_STRING([--disable-fix-cortex-a53-835769], + [disable workaround for AArch64 Cortex-A53 erratum 835769 by default]) + ], + [ + case $enableval in + yes) + tm_defines="${tm_defines} TARGET_FIX_ERR_A53_835769_DEFAULT=1" + ;; + no) + ;; + *) + AC_MSG_ERROR(['$enableval' is an invalid value for --enable-fix-cortex-a53-835769.\ + Valid choices are 'yes' and 'no'.]) + ;; + + esac + ], + []) ;; # All TARGET_ABI_OSF targets. diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 0c7ab3320dc..2cd0f1a2f77 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,75 @@ +2014-10-09 Jason Merrill <jason@redhat.com> + + PR c++/63415 + * pt.c (value_dependent_expression_p) [CONSTRUCTOR]: Check the type. + (iterative_hash_template_arg): Likewise. + + PR c++/63437 + * cp-tree.h (REF_PARENTHESIZED_P): Also allow INDIRECT_REF. + * semantics.c (force_paren_expr): And set it. + * typeck.c (check_return_expr): And handle it. + +2014-10-08 Jason Merrill <jason@redhat.com> + + PR c++/63405 + * pt.c (tsubst_pack_expansion): Limit simple expansion to type packs. + +2014-09-25 Jakub Jelinek <jakub@redhat.com> + + PR c++/63249 + * semantics.c (handle_omp_array_sections_1): Call mark_rvalue_use + on low_bound and length. + +2014-09-22 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/62219 + * pt.c (check_default_tmpl_args): Check LAMBDA_FUNCTION_P. + +2014-09-19 Jason Merrill <jason@redhat.com> + + PR c++/61465 + * call.c (convert_like_real) [ck_identity]: Call mark_rvalue_use + after pulling out an element from a CONSTRUCTOR. + +2014-09-18 Jakub Jelinek <jakub@redhat.com> + + PR c++/63248 + * semantics.c (finish_omp_clauses): Don't call cp_omp_mappable_type + on type of type dependent expressions, and don't call it if + handle_omp_array_sections has kept TREE_LIST because something + was type dependent. + * pt.c (tsubst_expr) <case OMP_TARGET, case OMP_TARGET_DATA>: + Use keep_next_level, begin_omp_structured_block and + finish_omp_structured_block instead of push_stmt_list and + pop_stmt_list. + +2014-09-10 Jason Merrill <jason@redhat.com> + + PR c++/63139 + * pt.c (tsubst_pack_expansion): Simplify substitution into T.... + +2014-09-09 Jason Merrill <jason@redhat.com> + + PR lto/53808 + PR c++/61659 + * decl2.c (note_comdat_fn): New. + (set_comdat): New. + (cp_write_global_declarations): Call set_comdat. + * method.c (implicitly_declare_fn): Call note_comdat_fn. + * pt.c (tsubst_decl) [FUNCTION_DECL]: Likewise. + * decl2.c (mark_needed): Mark clones. + (import_export_decl): Not here. + + PR c++/61214 + PR c++/62224 + * decl2.c (decl_needed_p): Revert virtual functions change. + +2014-09-05 Jason Merrill <jason@redhat.com> + + PR c++/62659 + * semantics.c (potential_constant_expression_1): Handle un-folded + pointer to member constants. + 2014-08-26 Jason Merrill <jason@redhat.com> PR c++/58624 diff --git a/gcc/cp/call.c b/gcc/cp/call.c index cd053f0adfd..709b6be0e3d 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -6078,7 +6078,6 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, return expr; } case ck_identity: - expr = mark_rvalue_use (expr); if (BRACE_ENCLOSED_INITIALIZER_P (expr)) { int nelts = CONSTRUCTOR_NELTS (expr); @@ -6089,6 +6088,7 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, else gcc_unreachable (); } + expr = mark_rvalue_use (expr); if (type_unknown_p (expr)) expr = instantiate_type (totype, expr, complain); diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 0b52dff3fdb..d149810bc42 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -100,7 +100,7 @@ c-common.h, not after. TARGET_EXPR_DIRECT_INIT_P (in TARGET_EXPR) FNDECL_USED_AUTO (in FUNCTION_DECL) DECLTYPE_FOR_LAMBDA_PROXY (in DECLTYPE_TYPE) - REF_PARENTHESIZED_P (in COMPONENT_REF, SCOPE_REF) + REF_PARENTHESIZED_P (in COMPONENT_REF, INDIRECT_REF) AGGR_INIT_ZERO_FIRST (in AGGR_INIT_EXPR) 3: (TREE_REFERENCE_EXPR) (in NON_LVALUE_EXPR) (commented-out). ICS_BAD_FLAG (in _CONV) @@ -3038,11 +3038,12 @@ extern void decl_shadowed_for_var_insert (tree, tree); #define PAREN_STRING_LITERAL_P(NODE) \ TREE_LANG_FLAG_0 (STRING_CST_CHECK (NODE)) -/* Indicates whether a COMPONENT_REF has been parenthesized. Currently - only set some of the time in C++14 mode. */ +/* Indicates whether a COMPONENT_REF has been parenthesized, or an + INDIRECT_REF comes from parenthesizing a VAR_DECL. Currently only set + some of the time in C++14 mode. */ #define REF_PARENTHESIZED_P(NODE) \ - TREE_LANG_FLAG_2 (COMPONENT_REF_CHECK (NODE)) + TREE_LANG_FLAG_2 (TREE_CHECK2 ((NODE), COMPONENT_REF, INDIRECT_REF)) /* Nonzero if this AGGR_INIT_EXPR provides for initialization via a constructor call, rather than an ordinary function call. */ @@ -5352,6 +5353,7 @@ extern tree get_tls_wrapper_fn (tree); extern void mark_needed (tree); extern bool decl_needed_p (tree); extern void note_vague_linkage_fn (tree); +extern void note_comdat_fn (tree); extern tree build_artificial_parm (tree, tree); extern bool possibly_inlined_p (tree); extern int parm_index (tree); diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index 77ab5fbdfd1..a2626d4c77b 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -99,6 +99,10 @@ static GTY(()) vec<tree, va_gc> *pending_statics; may need to emit outline anyway. */ static GTY(()) vec<tree, va_gc> *deferred_fns; +/* A list of functions which we might want to set DECL_COMDAT on at EOF. */ + +static GTY(()) vec<tree, va_gc> *maybe_comdat_fns; + /* A list of decls that use types with no linkage, which we need to make sure are defined. */ static GTY(()) vec<tree, va_gc> *no_linkage_decls; @@ -1896,6 +1900,12 @@ mark_needed (tree decl) definition. */ struct cgraph_node *node = cgraph_get_create_node (decl); node->forced_by_abi = true; + + /* #pragma interface and -frepo code can call mark_needed for + maybe-in-charge 'tors; mark the clones as well. */ + tree clone; + FOR_EACH_CLONE (clone, decl) + mark_needed (clone); } else if (TREE_CODE (decl) == VAR_DECL) { @@ -1934,11 +1944,6 @@ decl_needed_p (tree decl) if (flag_keep_inline_dllexport && lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl))) return true; - /* Virtual functions might be needed for devirtualization. */ - if (flag_devirtualize - && TREE_CODE (decl) == FUNCTION_DECL - && DECL_VIRTUAL_P (decl)) - return true; /* Otherwise, DECL does not need to be emitted -- yet. A subsequent reference to DECL might cause it to be emitted later. */ return false; @@ -2683,17 +2688,7 @@ import_export_decl (tree decl) { /* The repository indicates that this entity should be defined here. Make sure the back end honors that request. */ - if (VAR_P (decl)) - mark_needed (decl); - else if (DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl) - || DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl)) - { - tree clone; - FOR_EACH_CLONE (clone, decl) - mark_needed (clone); - } - else - mark_needed (decl); + mark_needed (decl); /* Output the definition as an ordinary strong definition. */ DECL_EXTERNAL (decl) = 0; DECL_INTERFACE_KNOWN (decl) = 1; @@ -4236,6 +4231,34 @@ dump_tu (void) } } +/* Much like the above, but not necessarily defined. 4.9 hack for setting + DECL_COMDAT on DECL_EXTERNAL functions, along with set_comdat. */ + +void +note_comdat_fn (tree decl) +{ + vec_safe_push (maybe_comdat_fns, decl); +} + +/* DECL is a function with vague linkage that was not + instantiated/synthesized in this translation unit. Set DECL_COMDAT for + the benefit of can_refer_decl_in_current_unit_p. */ + +static void +set_comdat (tree decl) +{ + DECL_COMDAT (decl) = true; + + tree clone; + FOR_EACH_CLONE (clone, decl) + set_comdat (clone); + + if (DECL_VIRTUAL_P (decl)) + for (tree thunk = DECL_THUNKS (decl); thunk; + thunk = DECL_CHAIN (thunk)) + DECL_COMDAT (thunk) = true; +} + /* This routine is called at the end of compilation. Its job is to create all the code needed to initialize and destroy the global aggregates. We do the destruction @@ -4613,6 +4636,10 @@ cp_write_global_declarations (void) vtv_build_vtable_verify_fndecl (); } + FOR_EACH_VEC_SAFE_ELT (maybe_comdat_fns, i, decl) + if (!DECL_COMDAT (decl) && vague_linkage_p (decl)) + set_comdat (decl); + finalize_compilation_unit (); if (flag_vtable_verify) diff --git a/gcc/cp/method.c b/gcc/cp/method.c index 11bff7f4587..b074d7471ed 100644 --- a/gcc/cp/method.c +++ b/gcc/cp/method.c @@ -1773,6 +1773,7 @@ implicitly_declare_fn (special_function_kind kind, tree type, DECL_EXTERNAL (fn) = true; DECL_NOT_REALLY_EXTERN (fn) = 1; DECL_DECLARED_INLINE_P (fn) = 1; + note_comdat_fn (fn); gcc_assert (!TREE_USED (fn)); /* Restore PROCESSING_TEMPLATE_DECL. */ diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 3296fda4734..0f989097442 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -1601,6 +1601,7 @@ iterative_hash_template_arg (tree arg, hashval_t val) case CONSTRUCTOR: { tree field, value; + iterative_hash_template_arg (TREE_TYPE (arg), val); FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (arg), i, field, value) { val = iterative_hash_template_arg (field, val); @@ -4430,9 +4431,11 @@ check_default_tmpl_args (tree decl, tree parms, bool is_primary, local scope. */ return true; - if (TREE_CODE (decl) == TYPE_DECL - && TREE_TYPE (decl) - && LAMBDA_TYPE_P (TREE_TYPE (decl))) + if ((TREE_CODE (decl) == TYPE_DECL + && TREE_TYPE (decl) + && LAMBDA_TYPE_P (TREE_TYPE (decl))) + || (TREE_CODE (decl) == FUNCTION_DECL + && LAMBDA_FUNCTION_P (decl))) /* A lambda doesn't have an explicit declaration; don't complain about the parms of the enclosing class. */ return true; @@ -9816,6 +9819,17 @@ tsubst_pack_expansion (tree t, tree args, tsubst_flags_t complain, } } + /* If the expansion is just T..., return the matching argument pack. */ + if (!unsubstituted_packs + && TREE_PURPOSE (packs) == pattern) + { + tree args = ARGUMENT_PACK_ARGS (TREE_VALUE (packs)); + if (TREE_CODE (t) == TYPE_PACK_EXPANSION + || pack_expansion_args_count (args)) + return args; + /* Otherwise use the normal path so we get convert_from_reference. */ + } + /* We cannot expand this expansion expression, because we don't have all of the argument packs we need. */ if (use_pack_expansion_extra_args_p (packs, len, unsubstituted_packs)) @@ -10677,6 +10691,9 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain) the type earlier (template/friend54.C). */ RETURN (new_r); + if (!DECL_FRIEND_P (r)) + note_comdat_fn (r); + /* We're not supposed to instantiate default arguments until they are called, for a template. But, for a declaration like: @@ -13860,8 +13877,6 @@ tsubst_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl, case OMP_SECTIONS: case OMP_SINGLE: case OMP_TEAMS: - case OMP_TARGET_DATA: - case OMP_TARGET: tmp = tsubst_omp_clauses (OMP_CLAUSES (t), false, args, complain, in_decl); stmt = push_stmt_list (); @@ -13874,6 +13889,22 @@ tsubst_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl, add_stmt (t); break; + case OMP_TARGET_DATA: + case OMP_TARGET: + tmp = tsubst_omp_clauses (OMP_CLAUSES (t), false, + args, complain, in_decl); + keep_next_level (true); + stmt = begin_omp_structured_block (); + + RECUR (OMP_BODY (t)); + stmt = finish_omp_structured_block (stmt); + + t = copy_node (t); + OMP_BODY (t) = stmt; + OMP_CLAUSES (t) = tmp; + add_stmt (t); + break; + case OMP_TARGET_UPDATE: tmp = tsubst_omp_clauses (OMP_TARGET_UPDATE_CLAUSES (t), false, args, complain, in_decl); @@ -20765,6 +20796,8 @@ value_dependent_expression_p (tree expression) { unsigned ix; tree val; + if (dependent_type_p (TREE_TYPE (expression))) + return true; FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (expression), ix, val) if (value_dependent_expression_p (val)) return true; diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index f38b5ba034e..5c6a9d3ce83 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -1630,6 +1630,8 @@ force_paren_expr (tree expr) bool rval = !!(kind & clk_rvalueref); type = cp_build_reference_type (type, rval); expr = build_static_cast (type, expr, tf_error); + if (expr != error_mark_node) + REF_PARENTHESIZED_P (expr) = true; } } @@ -4262,6 +4264,10 @@ handle_omp_array_sections_1 (tree c, tree t, vec<tree> &types, length); return error_mark_node; } + if (low_bound) + low_bound = mark_rvalue_use (low_bound); + if (length) + length = mark_rvalue_use (length); if (low_bound && TREE_CODE (low_bound) == INTEGER_CST && TYPE_PRECISION (TREE_TYPE (low_bound)) @@ -5627,7 +5633,9 @@ finish_omp_clauses (tree clauses) else { t = OMP_CLAUSE_DECL (c); - if (!cp_omp_mappable_type (TREE_TYPE (t))) + if (TREE_CODE (t) != TREE_LIST + && !type_dependent_expression_p (t) + && !cp_omp_mappable_type (TREE_TYPE (t))) { error_at (OMP_CLAUSE_LOCATION (c), "array section does not have mappable type " @@ -5667,6 +5675,7 @@ finish_omp_clauses (tree clauses) remove = true; else if (!(OMP_CLAUSE_CODE (c) == OMP_CLAUSE_MAP && OMP_CLAUSE_MAP_KIND (c) == OMP_CLAUSE_MAP_POINTER) + && !type_dependent_expression_p (t) && !cp_omp_mappable_type ((TREE_CODE (TREE_TYPE (t)) == REFERENCE_TYPE) ? TREE_TYPE (TREE_TYPE (t)) @@ -10181,6 +10190,11 @@ potential_constant_expression_1 (tree t, bool want_rval, tsubst_flags_t flags) designates an object with thread or automatic storage duration; */ t = TREE_OPERAND (t, 0); + + if (TREE_CODE (t) == OFFSET_REF && PTRMEM_OK_P (t)) + /* A pointer-to-member constant. */ + return true; + #if 0 /* FIXME adjust when issue 1197 is fully resolved. For now don't do any checking here, as we might dereference the pointer later. If diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index 9a80727dd8e..03d7ab807d7 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -8579,6 +8579,20 @@ check_return_expr (tree retval, bool *no_warning) if (VOID_TYPE_P (functype)) return error_mark_node; + /* If we had an id-expression obfuscated by force_paren_expr, we need + to undo it so we can try to treat it as an rvalue below. */ + if (cxx_dialect >= cxx1y + && INDIRECT_REF_P (retval) + && REF_PARENTHESIZED_P (retval)) + { + retval = TREE_OPERAND (retval, 0); + while (TREE_CODE (retval) == NON_LVALUE_EXPR + || TREE_CODE (retval) == NOP_EXPR) + retval = TREE_OPERAND (retval, 0); + gcc_assert (TREE_CODE (retval) == ADDR_EXPR); + retval = TREE_OPERAND (retval, 0); + } + /* Under C++0x [12.8/16 class.copy], a returned lvalue is sometimes treated as an rvalue for the purposes of overload resolution to favor move constructors over copy constructors. diff --git a/gcc/cse.c b/gcc/cse.c index b8223f7a35e..ec9aff4195a 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -2680,7 +2680,7 @@ exp_equiv_p (const_rtx x, const_rtx y, int validate, bool for_gcse) But because really all MEM attributes should be the same for equivalent MEMs, we just use the invariant that MEMs that have the same attributes share the same mem_attrs data structure. */ - if (MEM_ATTRS (x) != MEM_ATTRS (y)) + if (!mem_attrs_eq_p (MEM_ATTRS (x), MEM_ATTRS (y))) return 0; } break; diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 5c1703b4476..1daedff69bf 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1451,6 +1451,10 @@ be built. This can be useful for debugging, or for compatibility with previous Ada build procedures, when it was required to explicitly do a @samp{make -C gcc gnatlib_and_tools}. +@item --disable-libsanitizer +Specify that the run-time libraries for the various sanitizers should +not be built. + @item --disable-libssp Specify that the run-time libraries for stack smashing protection should not be built. @@ -3762,6 +3766,16 @@ Binutils pre 2.24 does not have support for selecting @option{-mabi} and does not support ILP32. If it is used to build GCC 4.9 or later, GCC will not support option @option{-mabi=ilp32}. +To enable a workaround for the Cortex-A53 erratum number 835769 by default +(for all CPUs regardless of -mcpu option given) at configure time use the +@option{--enable-fix-cortex-a53-835769} option. This will enable the fix by +default and can be explicitly disabled during during compilation by passing the +@option{-mno-fix-cortex-a53-835769} option. Conversely, +@option{--disable-fix-cortex-a53-835769} will disable the workaround by +default. The workaround is disabled by default if neither of +@option{--enable-fix-cortex-a53-835769} or +@option{--disable-fix-cortex-a53-835769} is given at configure time. + @html <hr /> <!-- rs6000-ibm-aix*, powerpc-ibm-aix* --> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d94e373bac6..a152472f0d0 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -479,6 +479,7 @@ Objective-C and Objective-C++ Dialects}. -mstrict-align @gol -momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol -mtls-dialect=desc -mtls-dialect=traditional @gol +-mfix-cortex-a53-835769 -mno-fix-cortex-a53-835769 @gol -march=@var{name} -mcpu=@var{name} -mtune=@var{name}} @emph{Adapteva Epiphany Options} @@ -826,7 +827,7 @@ Objective-C and Objective-C++ Dialects}. @emph{MSP430 Options} @gccoptlist{-msim -masm-hex -mmcu= -mcpu= -mlarge -msmall -mrelax @gol --mhwmult=} +-mhwmult= -minrt} @emph{NDS32 Options} @gccoptlist{-mbig-endian -mlittle-endian @gol @@ -11407,6 +11408,14 @@ of TLS variables. This is the default. Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables. +@item -mfix-cortex-a53-835769 +@itemx -mno-fix-cortex-a53-835769 +@opindex -mfix-cortex-a53-835769 +@opindex -mno-fix-cortex-a53-835769 +Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. +This will involve inserting a NOP instruction between memory instructions and +64-bit integer multiply-accumulate instructions. + @item -march=@var{name} @opindex march Specify the name of the target architecture, optionally suffixed by one or @@ -12275,8 +12284,8 @@ architecture together with the optional CRC32 extensions. @option{-march=native} causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. @item -mtune=@var{name} @opindex mtune @@ -12327,7 +12336,7 @@ this option may change in future GCC versions as CPU models come and go. @option{-mtune=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is +GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @item -mcpu=@var{name} @@ -12348,8 +12357,8 @@ See @option{-mtune} for more information. @option{-mcpu=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. @item -mfpu=@var{name} @opindex mfpu @@ -18261,6 +18270,13 @@ The hardware multiply routines disable interrupts whilst running and restore the previous interrupt state when they finish. This makes them safe to use inside interrupt handlers as well as in normal code. +@item -minrt +@opindex minrt +Enable the use of a minimum runtime environment - no static +initializers or constructors. This is intended for memory-constrained +devices. The compiler will include special symbols in some objects +that tell the linker and runtime which code fragments are required. + @end table @node NDS32 Options diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 13b2de74c5b..d48895cde6e 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -12561,7 +12561,7 @@ mem_loc_descriptor (rtx rtl, enum machine_mode mode, op1 = mem_loc_descriptor (XEXP (rtl, 1), mode, mem_mode, VAR_INIT_STATUS_INITIALIZED); if (op1 == 0) - break; + return NULL; add_loc_descr (&mem_loc_result, op1); add_loc_descr (&mem_loc_result, new_loc_descr (DW_OP_plus, 0, 0)); @@ -14223,6 +14223,10 @@ loc_list_from_tree (tree loc, int want_address) have_address = 1; break; + case TARGET_MEM_REF: + case SSA_NAME: + return NULL; + case COMPOUND_EXPR: return loc_list_from_tree (TREE_OPERAND (loc, 1), want_address); diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c index 89b676837b2..3041b9e7a18 100644 --- a/gcc/emit-rtl.c +++ b/gcc/emit-rtl.c @@ -248,6 +248,10 @@ const_fixed_htab_eq (const void *x, const void *y) bool mem_attrs_eq_p (const struct mem_attrs *p, const struct mem_attrs *q) { + if (p == q) + return true; + if (!p || !q) + return false; return (p->alias == q->alias && p->offset_known_p == q->offset_known_p && (!p->offset_known_p || p->offset == q->offset) diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 6a47227acd3..18f360da9b5 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2014-10-10 Jakub Jelinek <jakub@redhat.com> + + PR fortran/59488 + * trans-openmp.c (gfc_omp_predetermined_sharing): Return + OMP_CLAUSE_DEFAULT_SHARED for parameters or vtables. + 2014-09-03 Marek Polacek <polacek@redhat.com> Backport from trunk diff --git a/gcc/fortran/trans-openmp.c b/gcc/fortran/trans-openmp.c index 548b5d3a485..e31ede29bfa 100644 --- a/gcc/fortran/trans-openmp.c +++ b/gcc/fortran/trans-openmp.c @@ -135,6 +135,16 @@ gfc_omp_predetermined_sharing (tree decl) if (GFC_DECL_RESULT (decl) && ! DECL_HAS_VALUE_EXPR_P (decl)) return OMP_CLAUSE_DEFAULT_SHARED; + /* These are either array or derived parameters, or vtables. + In the former cases, the OpenMP standard doesn't consider them to be + variables at all (they can't be redefined), but they can nevertheless appear + in parallel/task regions and for default(none) purposes treat them as shared. + For vtables likely the same handling is desirable. */ + if (TREE_CODE (decl) == VAR_DECL + && TREE_READONLY (decl) + && TREE_STATIC (decl)) + return OMP_CLAUSE_DEFAULT_SHARED; + return OMP_CLAUSE_DEFAULT_UNSPECIFIED; } diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index c6aea6529ef..2527d292aef 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -146,7 +146,8 @@ can_refer_decl_in_current_unit_p (tree decl, tree from_decl) The second is important when devirtualization happens during final compilation stage when making a new reference no longer makes callee to be compiled. */ - if (!node || !node->definition || node->global.inlined_to) + if (!node || !node->definition + || DECL_EXTERNAL (decl) || node->global.inlined_to) { gcc_checking_assert (!TREE_ASM_WRITTEN (decl)); return false; diff --git a/gcc/go/gofrontend/gogo.cc b/gcc/go/gofrontend/gogo.cc index 9739f289f4d..f042f64d492 100644 --- a/gcc/go/gofrontend/gogo.cc +++ b/gcc/go/gofrontend/gogo.cc @@ -255,10 +255,7 @@ Gogo::pkgpath_for_symbol(const std::string& pkgpath) char c = s[i]; if ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') - || (c >= '0' && c <= '9') - || c == '_' - || c == '.' - || c == '$') + || (c >= '0' && c <= '9')) ; else s[i] = '_'; diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c index 653cb8272ea..e437e0a429c 100644 --- a/gcc/haifa-sched.c +++ b/gcc/haifa-sched.c @@ -6368,7 +6368,7 @@ schedule_block (basic_block *target_bb, state_t init_state) if (ls.modulo_epilogue) success = true; end_schedule: - if (!ls.first_cycle_insn_p) + if (!ls.first_cycle_insn_p || advance) advance_one_cycle (); perform_replacements_new_cycle (); if (modulo_ii > 0) diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index 49ff85c7f53..2097de6820c 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -4337,6 +4337,9 @@ dead_or_predicable (basic_block test_bb, basic_block merge_bb, old_dest = JUMP_LABEL (jump); if (other_bb != new_dest) { + if (!any_condjump_p (jump)) + goto cancel; + if (JUMP_P (BB_END (dest_edge->src))) new_dest_label = JUMP_LABEL (BB_END (dest_edge->src)); else if (new_dest == EXIT_BLOCK_PTR_FOR_FN (cfun)) @@ -4387,17 +4390,14 @@ dead_or_predicable (basic_block test_bb, basic_block merge_bb, insn = head; do { - rtx note, set; + rtx note; if (! INSN_P (insn)) continue; note = find_reg_note (insn, REG_EQUAL, NULL_RTX); if (! note) continue; - set = single_set (insn); - if (!set || !function_invariant_p (SET_SRC (set)) - || !function_invariant_p (XEXP (note, 0))) - remove_note (insn, note); + remove_note (insn, note); } while (insn != end && (insn = NEXT_INSN (insn))); /* PR46315: when moving insns above a conditional branch, the REG_EQUAL diff --git a/gcc/ipa-devirt.c b/gcc/ipa-devirt.c index 0671a8b781c..db00b285fc9 100644 --- a/gcc/ipa-devirt.c +++ b/gcc/ipa-devirt.c @@ -994,7 +994,8 @@ give_up: if ((TREE_CODE (type) != RECORD_TYPE || !TYPE_BINFO (type) || !polymorphic_type_binfo_p (TYPE_BINFO (type))) - && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST + && (!TYPE_SIZE (type) + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST || (offset + tree_to_uhwi (TYPE_SIZE (expected_type)) <= tree_to_uhwi (TYPE_SIZE (type))))) return true; @@ -1869,8 +1870,7 @@ ipa_devirt (void) /* Don't use an implicitly-declared destructor (c++/58678). */ struct cgraph_node *non_thunk_target = cgraph_function_node (likely_target); - if (DECL_ARTIFICIAL (non_thunk_target->decl) - && DECL_COMDAT (non_thunk_target->decl)) + if (DECL_ARTIFICIAL (non_thunk_target->decl)) { if (dump_file) fprintf (dump_file, "Target is artificial\n\n"); diff --git a/gcc/ipa-split.c b/gcc/ipa-split.c index 38bd88365d8..0d1495da0ff 100644 --- a/gcc/ipa-split.c +++ b/gcc/ipa-split.c @@ -167,7 +167,11 @@ test_nonssa_use (gimple, tree t, tree, void *data) || (TREE_CODE (t) == VAR_DECL && auto_var_in_fn_p (t, current_function_decl)) || TREE_CODE (t) == RESULT_DECL - || TREE_CODE (t) == LABEL_DECL) + /* Normal labels are part of CFG and will be handled gratefuly. + Forced labels however can be used directly by statements and + need to stay in one partition along with their uses. */ + || (TREE_CODE (t) == LABEL_DECL + && FORCED_LABEL (t))) return bitmap_bit_p ((bitmap)data, DECL_UID (t)); /* For DECL_BY_REFERENCE, the return value is actually a pointer. We want @@ -213,6 +217,7 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, edge e; edge_iterator ei; bool ok = true; + basic_block bb; FOR_EACH_EDGE (e, ei, current->entry_bb->preds) if (e->src != ENTRY_BLOCK_PTR_FOR_FN (cfun) @@ -225,8 +230,8 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, while (!worklist.is_empty ()) { gimple_stmt_iterator bsi; - basic_block bb = worklist.pop (); + bb = worklist.pop (); FOR_EACH_EDGE (e, ei, bb->preds) if (e->src != ENTRY_BLOCK_PTR_FOR_FN (cfun) && bitmap_set_bit (seen, e->src->index)) @@ -250,10 +255,10 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, if (gimple_code (stmt) == GIMPLE_LABEL && test_nonssa_use (stmt, gimple_label_label (stmt), NULL_TREE, non_ssa_vars)) - { - ok = false; - goto done; - } + { + ok = false; + goto done; + } } for (bsi = gsi_start_phis (bb); !gsi_end_p (bsi); gsi_next (&bsi)) { @@ -286,6 +291,27 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, } } } + + /* Verify that the rest of function does not define any label + used by the split part. */ + FOR_EACH_BB_FN (bb, cfun) + if (!bitmap_bit_p (current->split_bbs, bb->index) + && !bitmap_bit_p (seen, bb->index)) + { + gimple_stmt_iterator bsi; + for (bsi = gsi_start_bb (bb); !gsi_end_p (bsi); gsi_next (&bsi)) + if (gimple_code (gsi_stmt (bsi)) == GIMPLE_LABEL + && test_nonssa_use (gsi_stmt (bsi), + gimple_label_label (gsi_stmt (bsi)), + NULL_TREE, non_ssa_vars)) + { + ok = false; + goto done; + } + else if (gimple_code (gsi_stmt (bsi)) != GIMPLE_LABEL) + break; + } + done: BITMAP_FREE (seen); worklist.release (); @@ -734,7 +760,8 @@ mark_nonssa_use (gimple, tree t, tree, void *data) if ((TREE_CODE (t) == VAR_DECL && auto_var_in_fn_p (t, current_function_decl)) || TREE_CODE (t) == RESULT_DECL - || TREE_CODE (t) == LABEL_DECL) + || (TREE_CODE (t) == LABEL_DECL + && FORCED_LABEL (t))) bitmap_set_bit ((bitmap)data, DECL_UID (t)); /* For DECL_BY_REFERENCE, the return value is actually a pointer. We want diff --git a/gcc/lto-streamer-out.c b/gcc/lto-streamer-out.c index b193d730d75..6b5df1a611c 100644 --- a/gcc/lto-streamer-out.c +++ b/gcc/lto-streamer-out.c @@ -2077,7 +2077,10 @@ lto_output (void) #endif decl_state = lto_new_out_decl_state (); lto_push_out_decl_state (decl_state); - if (gimple_has_body_p (node->decl) || !flag_wpa) + if (gimple_has_body_p (node->decl) || !flag_wpa + /* Thunks have no body but they may be synthetized + at WPA time. */ + || DECL_ARGUMENTS (node->decl)) output_function (node); else copy_function (node); diff --git a/gcc/omp-low.c b/gcc/omp-low.c index 1753cad456c..f77df897679 100644 --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -204,6 +204,7 @@ static int taskreg_nesting_level; static int target_nesting_level; static struct omp_region *root_omp_region; static bitmap task_shared_vars; +static vec<omp_context *> taskreg_contexts; static void scan_omp (gimple_seq *, omp_context *); static tree scan_omp_1_op (tree *, int *, void *); @@ -2024,6 +2025,7 @@ scan_omp_parallel (gimple_stmt_iterator *gsi, omp_context *outer_ctx) } ctx = new_omp_context (stmt, outer_ctx); + taskreg_contexts.safe_push (ctx); if (taskreg_nesting_level > 1) ctx->is_nested = true; ctx->field_map = splay_tree_new (splay_tree_compare_pointers, 0, 0); @@ -2043,11 +2045,6 @@ scan_omp_parallel (gimple_stmt_iterator *gsi, omp_context *outer_ctx) if (TYPE_FIELDS (ctx->record_type) == NULL) ctx->record_type = ctx->receiver_decl = NULL; - else - { - layout_type (ctx->record_type); - fixup_child_record_type (ctx); - } } /* Scan an OpenMP task directive. */ @@ -2058,7 +2055,6 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) omp_context *ctx; tree name, t; gimple stmt = gsi_stmt (*gsi); - location_t loc = gimple_location (stmt); /* Ignore task directives with empty bodies. */ if (optimize > 0 @@ -2069,6 +2065,7 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) } ctx = new_omp_context (stmt, outer_ctx); + taskreg_contexts.safe_push (ctx); if (taskreg_nesting_level > 1) ctx->is_nested = true; ctx->field_map = splay_tree_new (splay_tree_compare_pointers, 0, 0); @@ -2106,8 +2103,71 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) t = build_int_cst (long_integer_type_node, 1); gimple_omp_task_set_arg_align (stmt, t); } +} + + +/* If any decls have been made addressable during scan_omp, + adjust their fields if needed, and layout record types + of parallel/task constructs. */ + +static void +finish_taskreg_scan (omp_context *ctx) +{ + if (ctx->record_type == NULL_TREE) + return; + + /* If any task_shared_vars were needed, verify all + OMP_CLAUSE_SHARED clauses on GIMPLE_OMP_{PARALLEL,TASK} + statements if use_pointer_for_field hasn't changed + because of that. If it did, update field types now. */ + if (task_shared_vars) + { + tree c; + + for (c = gimple_omp_taskreg_clauses (ctx->stmt); + c; c = OMP_CLAUSE_CHAIN (c)) + if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_SHARED) + { + tree decl = OMP_CLAUSE_DECL (c); + + /* Global variables don't need to be copied, + the receiver side will use them directly. */ + if (is_global_var (maybe_lookup_decl_in_outer_ctx (decl, ctx))) + continue; + if (!bitmap_bit_p (task_shared_vars, DECL_UID (decl)) + || !use_pointer_for_field (decl, ctx)) + continue; + tree field = lookup_field (decl, ctx); + if (TREE_CODE (TREE_TYPE (field)) == POINTER_TYPE + && TREE_TYPE (TREE_TYPE (field)) == TREE_TYPE (decl)) + continue; + TREE_TYPE (field) = build_pointer_type (TREE_TYPE (decl)); + TREE_THIS_VOLATILE (field) = 0; + DECL_USER_ALIGN (field) = 0; + DECL_ALIGN (field) = TYPE_ALIGN (TREE_TYPE (field)); + if (TYPE_ALIGN (ctx->record_type) < DECL_ALIGN (field)) + TYPE_ALIGN (ctx->record_type) = DECL_ALIGN (field); + if (ctx->srecord_type) + { + tree sfield = lookup_sfield (decl, ctx); + TREE_TYPE (sfield) = TREE_TYPE (field); + TREE_THIS_VOLATILE (sfield) = 0; + DECL_USER_ALIGN (sfield) = 0; + DECL_ALIGN (sfield) = DECL_ALIGN (field); + if (TYPE_ALIGN (ctx->srecord_type) < DECL_ALIGN (sfield)) + TYPE_ALIGN (ctx->srecord_type) = DECL_ALIGN (sfield); + } + } + } + + if (gimple_code (ctx->stmt) == GIMPLE_OMP_PARALLEL) + { + layout_type (ctx->record_type); + fixup_child_record_type (ctx); + } else { + location_t loc = gimple_location (ctx->stmt); tree *p, vla_fields = NULL_TREE, *q = &vla_fields; /* Move VLA fields to the end. */ p = &TYPE_FIELDS (ctx->record_type); @@ -2127,12 +2187,12 @@ scan_omp_task (gimple_stmt_iterator *gsi, omp_context *outer_ctx) fixup_child_record_type (ctx); if (ctx->srecord_type) layout_type (ctx->srecord_type); - t = fold_convert_loc (loc, long_integer_type_node, - TYPE_SIZE_UNIT (ctx->record_type)); - gimple_omp_task_set_arg_size (stmt, t); + tree t = fold_convert_loc (loc, long_integer_type_node, + TYPE_SIZE_UNIT (ctx->record_type)); + gimple_omp_task_set_arg_size (ctx->stmt, t); t = build_int_cst (long_integer_type_node, TYPE_ALIGN_UNIT (ctx->record_type)); - gimple_omp_task_set_arg_align (stmt, t); + gimple_omp_task_set_arg_align (ctx->stmt, t); } } @@ -9827,6 +9887,9 @@ lower_omp_target (gimple_stmt_iterator *gsi_p, omp_context *ctx) continue; } + unsigned int talign = TYPE_ALIGN_UNIT (TREE_TYPE (ovar)); + if (DECL_P (ovar) && DECL_ALIGN_UNIT (ovar) > talign) + talign = DECL_ALIGN_UNIT (ovar); if (nc) { tree var = lookup_decl_in_outer_ctx (ovar, ctx); @@ -9841,6 +9904,7 @@ lower_omp_target (gimple_stmt_iterator *gsi_p, omp_context *ctx) = create_tmp_var (TREE_TYPE (TREE_TYPE (x)), NULL); mark_addressable (avar); gimplify_assign (avar, build_fold_addr_expr (var), &ilist); + talign = DECL_ALIGN_UNIT (avar); avar = build_fold_addr_expr (avar); gimplify_assign (x, avar, &ilist); } @@ -9893,9 +9957,6 @@ lower_omp_target (gimple_stmt_iterator *gsi_p, omp_context *ctx) default: gcc_unreachable (); } - unsigned int talign = TYPE_ALIGN_UNIT (TREE_TYPE (ovar)); - if (DECL_P (ovar) && DECL_ALIGN_UNIT (ovar) > talign) - talign = DECL_ALIGN_UNIT (ovar); talign = ceil_log2 (talign); tkind |= talign << 3; CONSTRUCTOR_APPEND_ELT (vkind, purpose, @@ -10269,6 +10330,8 @@ static unsigned int execute_lower_omp (void) { gimple_seq body; + int i; + omp_context *ctx; /* This pass always runs, to provide PROP_gimple_lomp. But there is nothing to do unless -fopenmp is given. */ @@ -10281,6 +10344,9 @@ execute_lower_omp (void) body = gimple_body (current_function_decl); scan_omp (&body, NULL); gcc_assert (taskreg_nesting_level == 0); + FOR_EACH_VEC_ELT (taskreg_contexts, i, ctx) + finish_taskreg_scan (ctx); + taskreg_contexts.release (); if (all_contexts->root) { @@ -11436,9 +11502,22 @@ ipa_simd_modify_stmt_ops (tree *tp, int *walk_subtrees, void *data) if (tp != orig_tp) { repl = build_fold_addr_expr (repl); - gimple stmt - = gimple_build_assign (make_ssa_name (TREE_TYPE (repl), NULL), repl); - repl = gimple_assign_lhs (stmt); + gimple stmt; + if (is_gimple_debug (info->stmt)) + { + tree vexpr = make_node (DEBUG_EXPR_DECL); + stmt = gimple_build_debug_source_bind (vexpr, repl, NULL); + DECL_ARTIFICIAL (vexpr) = 1; + TREE_TYPE (vexpr) = TREE_TYPE (repl); + DECL_MODE (vexpr) = TYPE_MODE (TREE_TYPE (repl)); + repl = vexpr; + } + else + { + stmt = gimple_build_assign (make_ssa_name (TREE_TYPE (repl), + NULL), repl); + repl = gimple_assign_lhs (stmt); + } gimple_stmt_iterator gsi = gsi_for_stmt (info->stmt); gsi_insert_before (&gsi, stmt, GSI_SAME_STMT); *orig_tp = repl; diff --git a/gcc/recog.c b/gcc/recog.c index f2647e39aae..0481d7dbbfd 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -3659,6 +3659,8 @@ peephole2_optimize (void) BITMAP_FREE (live); if (peep2_do_rebuild_jump_labels) rebuild_jump_labels (get_insns ()); + if (peep2_do_cleanup_cfg) + cleanup_cfg (CLEANUP_CFG_CHANGED); } #endif /* HAVE_peephole2 */ diff --git a/gcc/regcprop.c b/gcc/regcprop.c index 101de76ef10..fd5fb1d2bf9 100644 --- a/gcc/regcprop.c +++ b/gcc/regcprop.c @@ -1039,7 +1039,17 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) but instead among CLOBBERs on the CALL_INSN, we could wrongly assume the value in it is still live. */ if (ksvd.ignore_set_reg) - note_stores (PATTERN (insn), kill_clobbered_value, vd); + { + note_stores (PATTERN (insn), kill_clobbered_value, vd); + for (exp = CALL_INSN_FUNCTION_USAGE (insn); + exp; + exp = XEXP (exp, 1)) + { + rtx x = XEXP (exp, 0); + if (GET_CODE (x) == CLOBBER) + kill_value (SET_DEST (x), vd); + } + } } /* Notice stores. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0200c69a518..0e7553e97fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,247 @@ +2014-10-11 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from mainline r216117. + 2014-10-11 Christophe Lyon <christophe.lyon@linaro.org> + * lib/target-supports.exp (check_effective_target_shared): New + function. + * g++.dg/ipa/devirt-28a.C: Check if -shared is supported. + +2014-10-10 Jakub Jelinek <jakub@redhat.com> + + PR c/63495 + * gcc.target/i386/pr63495.c: New test. + +2014-10-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63379 + * gcc.dg/vect/pr63379.c: New testcase. + +2014-10-10 Jakub Jelinek <jakub@redhat.com> + + PR fortran/59488 + * gfortran.dg/gomp/pr59488-1.f90: New test. + * gfortran.dg/gomp/pr59488-2.f90: New test. + +2014-10-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63380 + * gcc.dg/torture/pr63380-1.c: New testcase. + * gcc.dg/torture/pr63380-2.c: Likewise. + +2014-10-10 Uros Bizjak <ubizjak@gmail.com> + + * g++.dg/cpp1y/feat-cxx14.C: Variable templates not in yet. + (dg-do): Use c++1y target. + +2014-10-08 Edward Smith-Rowland <3dw4rd@verizon.net> + + Implement SD-6: SG10 Feature Test Recommendations + * g++.dg/cpp1y/feat-cxx11-neg.C: New. + * g++.dg/cpp1y/feat-cxx11.C: New. + * g++.dg/cpp1y/feat-cxx14.C: New. + * g++.dg/cpp1y/feat-cxx98.C: New. + * g++.dg/cpp1y/feat-cxx98-neg.C: New. + * g++.dg/cpp1y/phoobhar.h: New. + * g++.dg/cpp1y/testinc/phoobhar.h: New. + +2014-10-03 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/61144 + * gcc.dg/tree-ssa/pr61144.c: New testcase. + +2014-10-03 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/62121 + * g++.dg/torture/pr62121.C: New testcase. + +2014-10-03 Jan Hubicka <hubicka@ucw.cz> + + PR lto/62026 + * g++.dg/lto/pr62026.C: New testcase. + +2014-10-03 Jakub Jelinek <jakub@redhat.com> + + PR libgomp/61200 + * c-c++-common/gomp/pr61200.c: New test. + +2014-10-01 Jakub Jelinek <jakub@redhat.com> + + PR debug/63342 + * gcc.dg/pr63342.c: New test. + + PR target/63428 + * gcc.dg/torture/vshuf-4.inc: Move test 122 from EXPTESTS + to test 24 in TESTS. + + PR c++/63306 + * g++.dg/ipa/pr63306.C: New test. + + 2014-09-18 Vladimir Makarov <vmakarov@redhat.com> + + PR debug/63285 + * gcc.target/i386/pr63285.c: New test. + + 2014-09-10 Jan Hubicka <hubicka@ucw.cz> + + PR tree-optimization/63186 + * gcc.dg/pr63186.c: New testcase. + +2014-09-30 Jakub Jelinek <jakub@redhat.com> + + PR inline-asm/63282 + * gcc.c-torture/compile/pr63282.c: New test. + +2014-09-29 James Clarke <jrtc27@jrtc27.com> + + PR target/61407 + * gcc.dg/darwin-minversion-1.c: Fixed formatting. + * gcc.dg/darwin-minversion-2.c: Fixed formatting. + * gcc.dg/darwin-minversion-3.c: Fixed formatting. + * gcc.dg/darwin-minversion-4.c: Added test for OS X 10.10. + +2014-09-26 Jakub Jelinek <jakub@redhat.com> + + * g++.dg/compat/struct-layout-1_generate.c: Add -Wno-abi + to default options. + +2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215559 + 2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/63335 + * gcc.target/powerpc/pr63335.c: New test. + +2014-09-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/63341 + * gcc.dg/vect/pr63341-1.c: New test. + * gcc.dg/vect/pr63341-2.c: New test. + + PR c++/63249 + * g++.dg/gomp/pr63249.C: New test. + * c-c++-common/gomp/pr63249.c: New test. + +2014-09-22 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/62219 + * g++.dg/cpp0x/lambda/lambda-template14.C: New. + +2014-09-22 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-05-21 Marek Polacek <polacek@redhat.com> + + PR sanitizer/61272 + * g++.dg/ubsan/pr61272.C: New test. + +2014-09-22 Jakub Jelinek <jakub@redhat.com> + + PR debug/63328 + * c-c++-common/gomp/pr63328.c: New test. + +2014-09-18 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-09-18 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/pr61053.c: Updated for x32. + +2014-09-18 Jakub Jelinek <jakub@redhat.com> + + PR c++/62017 + * g++.dg/asan/pr62017.C: New test. + + PR testsuite/63292 + * gcc.dg/vect/pr59594.c (b): Increase size to N + 2 elements. + +2014-09-18 Joseph Myers <joseph@codesourcery.com> + + * gcc.dg/torture/float128-exact-underflow.c: New test. + +2014-09-17 Jakub Jelinek <jakub@redhat.com> + + PR debug/63284 + * gcc.dg/pr63284.c: New test. + +2014-09-17 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/63241 + * g++.dg/cpp0x/constexpr-63241.C: New. + +2014-09-12 Martin Jambor <mjambor@suse.cz> + + PR ipa/61654 + * g++.dg/ipa/pr61654.C: New test. + +2014-09-11 Alan Lawrence <alan.lawrence@arm.com> + + Backport r214953 from mainline + 2014-09-05 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/aarch64/scalar_intrinsics.c (*): Replace all + int{32,16,8}x1_t with int{32,16,8}_t. + * gcc.target/aarch64/simd/vqdmlalh_lane_s16.c: Likewise. + * gcc.target/aarch64/simd/vqdmlslh_lane_s16.c: Likewise. + * gcc.target/aarch64/simd/vqdmullh_lane_s16.c: Likewise. + * gcc.target/aarch64/simd/vqdmulls_lane_s32.c: Likewise. + +2014-09-10 Xinliang David Li <davidxl@google.com> + + Backport from mainline + PR target/63209 + * gcc.c-torture/execute/pr63209.c: New test. + +2014-09-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backported from mainline + 2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/vsx-extract-1.c: Test 0th doubleword + regardless of endianness. + +2014-09-09 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62075 + * gcc.dg/vect/pr62075.c: New testcase. + + 2014-08-14 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/62079 + * g++.dg/pr62079.C: New testcase. + + 2014-08-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62175 + * g++.dg/torture/pr62175.C: New testcase. + +2014-09-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/60196 + PR tree-optimization/63189 + * gcc.dg/vect/pr63189.c: New test. + * gcc.dg/vect/pr60196-1.c: New test. + * gcc.dg/vect/pr60196-2.c: New test. + +2014-09-06 John David Anglin <danglin@gcc.gnu.org> + + PR testsuite/56194 + * g++.dg/init/const9.C: Skip scan-assembler-not "rodata" on hppa*-*-*. + +2014-09-05 Easwaran Raman <eraman@google.com> + + Backport from mainline + PR rtl-optimization/62146 + * testsuite/g++.dg/opt/pr62146.C: New. + +2014-09-04 Guozhi Wei <carrot@google.com> + + PR target/62040 + * gcc.target/aarch64/pr62040.c: New test. + 2014-09-03 Martin Jambor <mjambor@suse.cz> PR ipa/62015 diff --git a/gcc/testsuite/c-c++-common/gomp/pr61200.c b/gcc/testsuite/c-c++-common/gomp/pr61200.c new file mode 100644 index 00000000000..d0d699dfa0b --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/pr61200.c @@ -0,0 +1,13 @@ +/* PR libgomp/61200 */ + +int +main () +{ + int var = 1; + #pragma omp parallel + if (var != 1) + __builtin_abort (); + #pragma omp task shared(var) + var = 2; + return 0; +} diff --git a/gcc/testsuite/c-c++-common/gomp/pr63249.c b/gcc/testsuite/c-c++-common/gomp/pr63249.c new file mode 100644 index 00000000000..878788ad7ef --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/pr63249.c @@ -0,0 +1,16 @@ +/* PR c++/63249 */ +/* { dg-do compile } */ +/* { dg-options "-Wall -W -fopenmp" } */ + +int +foo (int *v, int A, int B) /* { dg-bogus "set but not used" } */ +{ + int r = 0; + int a = 2; /* { dg-bogus "set but not used" } */ + int b = 4; /* { dg-bogus "set but not used" } */ +#pragma omp target map(to: v[a:b]) + r |= v[3]; +#pragma omp target map(to: v[A:B]) + r |= v[3]; + return r; +} diff --git a/gcc/testsuite/c-c++-common/gomp/pr63328.c b/gcc/testsuite/c-c++-common/gomp/pr63328.c new file mode 100644 index 00000000000..3958abe166b --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/pr63328.c @@ -0,0 +1,5 @@ +/* PR debug/63328 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fopenmp-simd -fno-strict-aliasing -fcompare-debug" } */ + +#include "pr60823-3.c" diff --git a/gcc/testsuite/g++.dg/abi/no-weak1.C b/gcc/testsuite/g++.dg/abi/no-weak1.C new file mode 100644 index 00000000000..d539015312f --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/no-weak1.C @@ -0,0 +1,13 @@ +// { dg-options "-fno-weak" } +// { dg-final { scan-assembler "local\[ \t\]*_ZZL1fvE1i" { target x86_64-*-*gnu } } } + +static inline void f() +{ + static int i; + ++i; +}; + +int main() +{ + f(); +} diff --git a/gcc/testsuite/g++.dg/abi/spec1.C b/gcc/testsuite/g++.dg/abi/spec1.C new file mode 100644 index 00000000000..153c0cfe7f0 --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/spec1.C @@ -0,0 +1,4 @@ +// { dg-final { scan-assembler-not "weak" } } + +template <class T> struct A { static int i; }; +template<> int A<int>::i = 42; diff --git a/gcc/testsuite/g++.dg/asan/pr62017.C b/gcc/testsuite/g++.dg/asan/pr62017.C new file mode 100644 index 00000000000..74ef37fd2c0 --- /dev/null +++ b/gcc/testsuite/g++.dg/asan/pr62017.C @@ -0,0 +1,17 @@ +// PR c++/62017 +// { dg-do run } + +struct A +{ + int x; + virtual ~A () {} +}; +struct B : public virtual A {}; +struct C : public virtual A {}; +struct D : public B, virtual public C {}; + +int +main () +{ + D d; +} diff --git a/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c b/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c index 2cf08946e36..2884c25f337 100644 --- a/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c +++ b/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c @@ -1,5 +1,5 @@ /* Structure layout test generator. - Copyright (C) 2004, 2005, 2007, 2008, 2009, 2011, 2012 + Copyright (C) 2004-2014 Free Software Foundation, Inc. Contributed by Jakub Jelinek <jakub@redhat.com>. @@ -44,7 +44,7 @@ along with GCC; see the file COPYING3. If not see #endif const char *dg_options[] = { -"/* { dg-options \"%s-I%s\" } */\n", +"/* { dg-options \"%s-I%s -Wno-abi\" } */\n", "/* { dg-options \"%s-I%s -mno-mmx -Wno-abi\" { target i?86-*-* x86_64-*-* } } */\n", "/* { dg-options \"%s-I%s -fno-common\" { target hppa*-*-hpux* powerpc*-*-darwin* *-*-mingw32* *-*-cygwin* } } */\n", "/* { dg-options \"%s-I%s -mno-mmx -fno-common -Wno-abi\" { target i?86-*-darwin* x86_64-*-darwin* i?86-*-mingw32* x86_64-*-mingw32* i?86-*-cygwin* } } */\n", diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-63241.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-63241.C new file mode 100644 index 00000000000..2553cae349c --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-63241.C @@ -0,0 +1,13 @@ +// PR c++/63241 +// { dg-do compile { target c++11 } } + +struct A { + constexpr A(int){} +}; + +int main() { + int i = 1; + A array[2][2] = + {{{0}, {i}}, + {{0}, {0}}}; +} diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-initlist8.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-initlist8.C new file mode 100644 index 00000000000..3d859a8524d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-initlist8.C @@ -0,0 +1,7 @@ +// PR c++/63415 +// { dg-do compile { target c++11 } } + +template <typename T> +struct A { + static constexpr int value = int(T{}); +}; diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template14.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template14.C new file mode 100644 index 00000000000..b73ef753e08 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template14.C @@ -0,0 +1,11 @@ +// PR c++/62219 +// { dg-do compile { target c++11 } } + +template< class = void > +struct S +{ + friend void foo( S ) + { + [](){}; + } +}; diff --git a/gcc/testsuite/g++.dg/cpp0x/variadic161.C b/gcc/testsuite/g++.dg/cpp0x/variadic161.C new file mode 100644 index 00000000000..ac6eaf6a36a --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/variadic161.C @@ -0,0 +1,51 @@ +// PR c++/63139 +// { dg-do compile { target c++11 } } + +template<typename ...T> +struct type_list {}; + +template<typename ...T> +struct make_type_list +{ + using type = type_list<T...>; +}; + +// The bug disappears if you use make_type_list directly. +template<typename ...T> +using make_type_list_t = typename make_type_list<T...>::type; + + +struct ContainerEndA {}; + +template<typename ...Ts> +struct ContainerA +{ + using type = make_type_list_t<Ts..., ContainerEndA>; +}; + + +struct ContainerEndB {}; + +template<typename ...Ts> +struct ContainerB +{ + using type = make_type_list_t<Ts..., ContainerEndB>; +}; + +template<typename T, typename U> +struct is_same +{ + static const bool value = false; +}; + +template<typename T> +struct is_same<T, T> +{ + static const bool value = true; +}; + +#define SA(X) static_assert((X), #X) + +SA((is_same<ContainerB<>::type, type_list<ContainerEndB>>::value)); +SA((!is_same<ContainerA<>::type, type_list<ContainerEndB>>::value)); +SA((!is_same<ContainerA<>::type, ContainerB<>::type>::value)); diff --git a/gcc/testsuite/g++.dg/cpp0x/variadic162.C b/gcc/testsuite/g++.dg/cpp0x/variadic162.C new file mode 100644 index 00000000000..9e5386deb47 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/variadic162.C @@ -0,0 +1,14 @@ +// PR c++/63405 +// { dg-do compile { target c++11 } } + +template <typename _Tp> _Tp forward(_Tp); +template <typename Args> struct Format { Format(int, Args); }; +template <typename... Args> auto format(Args &&... args) -> Format<Args...> { + return {0, args...}; +} + +template <typename... Args> void msg(Args... args) { + format(forward(args)...); +} + +void some_function() { msg('x'); } diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx11-neg.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx11-neg.C new file mode 100644 index 00000000000..8719577c5cf --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx11-neg.C @@ -0,0 +1,40 @@ +// { dg-do compile { target c++11_only } } +// { dg-options "-pedantic-errors" } + +// These *are* defined in C++14 onwards. + +#ifndef __cpp_binary_literals +# error "__cpp_binary_literals" // { dg-error "error" } +#endif + +#ifndef __cpp_init_captures +# error "__cpp_init_captures" // { dg-error "error" } +#endif + +#ifndef __cpp_generic_lambdas +# error "__cpp_generic_lambdas" // { dg-error "error" } +#endif + +#ifndef __cpp_decltype_auto +# error "__cpp_decltype_auto" // { dg-error "error" } +#endif + +#ifndef __cpp_return_type_deduction +# error "__cpp_return_type_deduction" // { dg-error "error" } +#endif + +#ifndef __cpp_variable_templates +# error "__cpp_variable_templates" // { dg-error "error" } +#endif + +#ifndef __cpp_digit_separators +# error "__cpp_digit_separators" // { dg-error "error" } +#endif + +#ifndef __cpp_attribute_deprecated +# error "__cpp_attribute_deprecated" // { dg-error "error" } +#endif + +#ifndef __cpp_runtime_arrays +# error "__cpp_runtime_arrays" // { dg-error "error" } +#endif diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C new file mode 100644 index 00000000000..606a5cec618 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C @@ -0,0 +1,81 @@ +// { dg-do compile } +// { dg-options "-std=gnu++11" } + +#ifndef __cpp_unicode_characters +# error "__cpp_unicode_characters" +#elif __cpp_unicode_characters != 200704 +# error "__cpp_unicode_characters != 200704" +#endif + +#ifndef __cpp_raw_strings +# error "__cpp_raw_strings" +#elif __cpp_raw_strings != 200710 +# error "__cpp_raw_strings != 200710" +#endif + +#ifndef __cpp_unicode_literals +# error "__cpp_unicode_literals" +#elif __cpp_unicode_literals != 200710 +# error "__cpp_unicode_literals != 200710" +#endif + +#ifndef __cpp_user_defined_literals +# error "__cpp_user_defined_literals" +#elif __cpp_user_defined_literals != 200809 +# error "__cpp_user_defined_literals != 200809" +#endif + +#ifndef __cpp_lambdas +# error "__cpp_lambdas" +#elif __cpp_lambdas != 200907 +# error "__cpp_lambdas != 200907" +#endif + +#ifndef __cpp_constexpr +# error "__cpp_constexpr" +#elif __cpp_constexpr != 200704 +# error "__cpp_constexpr != 200704" +#endif + +#ifndef __cpp_static_assert +# error "__cpp_static_assert" +#elif __cpp_static_assert != 200410 +# error "__cpp_static_assert != 200410" +#endif + +#ifndef __cpp_decltype +# error "__cpp_decltype" +#elif __cpp_decltype != 200707 +# error "__cpp_decltype != 200707" +#endif + +#ifndef __cpp_attributes +# error "__cpp_attributes" +#elif __cpp_attributes != 200809 +# error "__cpp_attributes != 200809" +#endif + +#ifndef __cpp_rvalue_reference +# error "__cpp_rvalue_reference" +#elif __cpp_rvalue_reference != 200610 +# error "__cpp_rvalue_reference != 200610" +#endif + +#ifndef __cpp_variadic_templates +# error "__cpp_variadic_templates" +#elif __cpp_variadic_templates != 200704 +# error "__cpp_variadic_templates != 200704" +#endif + +#ifndef __cpp_alias_templates +# error "__cpp_alias_templates" +#elif __cpp_alias_templates != 200704 +# error "__cpp_alias_templates != 200704" +#endif + +// These C++14 features are allowed in C++11 in non-ANSI modes. +#ifndef __cpp_binary_literals +# error "__cpp_binary_literals" +#elif __cpp_binary_literals != 201304 +# error "__cpp_binary_literals != 201304" +#endif diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C new file mode 100644 index 00000000000..8a05f666064 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C @@ -0,0 +1,231 @@ +// { dg-do compile { target c++1y } } +// { dg-options "-I${srcdir}/g++.dg/cpp1y -I${srcdir}/g++.dg/cpp1y/testinc" } + +// Begin C++11 tests. + +#ifndef __cpp_unicode_characters +# error "__cpp_unicode_characters" +#elif __cpp_unicode_characters != 200704 +# error "__cpp_unicode_characters != 200704" +#endif + +#ifndef __cpp_raw_strings +# error "__cpp_raw_strings" +#elif __cpp_raw_strings != 200710 +# error "__cpp_raw_strings != 200710" +#endif + +#ifndef __cpp_unicode_literals +# error "__cpp_unicode_literals" +#elif __cpp_unicode_literals != 200710 +# error "__cpp_unicode_literals != 200710" +#endif + +#ifndef __cpp_user_defined_literals +# error "__cpp_user_defined_literals" +#elif __cpp_user_defined_literals != 200809 +# error "__cpp_user_defined_literals != 200809" +#endif + +#ifndef __cpp_lambdas +# error "__cpp_lambdas" +#elif __cpp_lambdas != 200907 +# error "__cpp_lambdas != 200907" +#endif + +#ifndef __cpp_constexpr +# error "__cpp_constexpr" +#elif __cpp_constexpr != 200704 +# error "__cpp_constexpr != 200704" +#endif + +#ifndef __cpp_static_assert +# error "__cpp_static_assert" +#elif __cpp_static_assert != 200410 +# error "__cpp_static_assert != 200410" +#endif + +#ifndef __cpp_decltype +# error "__cpp_decltype" +#elif __cpp_decltype != 200707 +# error "__cpp_decltype != 200707" +#endif + +#ifndef __cpp_attributes +# error "__cpp_attributes" +#elif __cpp_attributes != 200809 +# error "__cpp_attributes != 200809" +#endif + +#ifndef __cpp_rvalue_reference +# error "__cpp_rvalue_reference" +#elif __cpp_rvalue_reference != 200610 +# error "__cpp_rvalue_reference != 200610" +#endif + +#ifndef __cpp_variadic_templates +# error "__cpp_variadic_templates" +#elif __cpp_variadic_templates != 200704 +# error "__cpp_variadic_templates != 200704" +#endif + +#ifndef __cpp_alias_templates +# error "__cpp_alias_templates" +#elif __cpp_alias_templates != 200704 +# error "__cpp_alias_templates != 200704" +#endif + +// Begin C++14 tests. + +#ifndef __cpp_binary_literals +# error "__cpp_binary_literals" +#elif __cpp_binary_literals != 201304 +# error "__cpp_binary_literals != 201304" +#endif + +#ifndef __cpp_init_captures +# error "__cpp_init_captures" +#elif __cpp_init_captures != 201304 +# error "__cpp_init_captures != 201304" +#endif + +#ifndef __cpp_generic_lambdas +# error "__cpp_generic_lambdas" +#elif __cpp_generic_lambdas != 201304 +# error "__cpp_generic_lambdas != 201304" +#endif + +// TODO: Change 200704 to 201304 when C++14 constexpr goes in. +#ifndef __cpp_constexpr +# error "__cpp_constexpr" +#elif __cpp_constexpr != 200704 +# error "__cpp_constexpr != 200704" +#endif + +#ifndef __cpp_decltype_auto +# error "__cpp_decltype_auto" +#elif __cpp_decltype_auto != 201304 +# error "__cpp_decltype_auto != 201304" +#endif + +#ifndef __cpp_return_type_deduction +# error "__cpp_return_type_deduction" +#elif __cpp_return_type_deduction != 201304 +# error "__cpp_return_type_deduction != 201304" +#endif + +#ifndef __cpp_runtime_arrays +# error "__cpp_runtime_arrays" +#elif __cpp_runtime_arrays != 201304 +# error "__cpp_runtime_arrays != 201304" +#endif + +// Aggregate initializers not in yet. +#ifdef __cpp_aggregate_nsdmi +# error "__cpp_aggregate_nsdmi" +#endif + +// Variable templates not in yet. +#ifdef __cpp_variable_templates +# error "__cpp_variable_templates" +#endif + +#ifndef __cpp_digit_separators +# error "__cpp_digit_separators" +#elif __cpp_digit_separators != 201309 +# error "__cpp_digit_separators != 201309" +#endif + +#ifndef __cpp_attribute_deprecated +# error "__cpp_attribute_deprecated" +#elif __cpp_attribute_deprecated != 201309 +# error "__cpp_attribute_deprecated != 201309" +#endif + +// Sized deallocation not in yet. +#ifdef __cpp_sized_deallocation +# error "__cpp_sized_deallocation" +#endif + +// Begin include checks. + +// Check for __has_include macro. +#ifndef __has_include +# error "__has_include" +#endif + +// Quoted complex.h should find at least the bracket version (use operator). +#if __has_include__ "complex.h" +#else +# error "complex.h" +#endif + +// Try known bracket header (use operator). +#if __has_include__(<complex>) +#else +# error "<complex>" +#endif + +// Define and use a macro to invoke the operator. +#define sluggo(TXT) __has_include__(TXT) + +#if sluggo(<complex>) +#else +# error "<complex>" +#endif + +#if ! sluggo(<complex>) +# error "<complex>" +#else +#endif + +// Quoted complex.h should find at least the bracket version. +#if __has_include("complex.h") +#else +# error "complex.h" +#endif + +// Try known local quote header. +#if __has_include("complex_literals.h") +#else +# error "\"complex_literals.h\"" +#endif + +// Try nonexistent bracket header. +#if __has_include(<stuff>) +# error "<stuff>" +#else +#endif + +// Try nonexistent quote header. +#if __has_include("phlegm") +# error "\"phlegm\"" +#else +#endif + +// Test __has_include_next. +#if __has_include("phoobhar.h") +# include "phoobhar.h" +#else +# error "__has_include(\"phoobhar.h\")" +#endif + +// Try a macro. +#define COMPLEX_INC "complex.h" +#if __has_include(COMPLEX_INC) +#else +# error COMPLEX_INC +#endif + +// Realistic use of __has_include. +#if __has_include(<array>) +# define STD_ARRAY 1 +# include <array> + template<typename _Tp, size_t _Num> + using array = std::array<_Tp, _Num>; +#elif __has_include(<tr1/array>) +# define TR1_ARRAY 1 +# include <tr1/array> + template<typename _Tp, size_t _Num> + typedef std::tr1::array<_Tp, _Num> array; +#endif diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C new file mode 100644 index 00000000000..b99b57efe0e --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C @@ -0,0 +1,99 @@ +// { dg-do compile { target c++98_only } } +// { dg-options "-ansi" } + +#ifndef __cpp_runtime_arrays +# error "__cpp_runtime_arrays" // { dg-error "error" } +#endif + +#ifndef __cpp_unicode_characters +# error "__cpp_unicode_characters" // { dg-error "error" } +#endif + +#ifndef __cpp_raw_strings +# error "__cpp_raw_strings" // { dg-error "error" } +#endif + +#ifndef __cpp_unicode_literals +# error "__cpp_unicode_literals" // { dg-error "error" } +#endif + +#ifndef __cpp_user_defined_literals +# error "__cpp_user_defined_literals" // { dg-error "error" } +#endif + +#ifndef __cpp_lambdas +# error "__cpp_lambdas" // { dg-error "error" } +#endif + +#ifndef __cpp_constexpr +# error "__cpp_constexpr" // { dg-error "error" } +#endif + +#ifndef __cpp_static_assert +# error "__cpp_static_assert" // { dg-error "error" } +#endif + +#ifndef __cpp_decltype +# error "__cpp_decltype" // { dg-error "error" } +#endif + +#ifndef __cpp_attributes +# error "__cpp_attributes" // { dg-error "error" } +#endif + +#ifndef __cpp_rvalue_reference +# error "__cpp_rvalue_reference" // { dg-error "error" } +#endif + +#ifndef __cpp_variadic_templates +# error "__cpp_variadic_templates" // { dg-error "error" } +#endif + +#ifndef __cpp_alias_templates +# error "__cpp_alias_templates" // { dg-error "error" } +#endif + +// C++14 + +// C++98 gets binary literals. +//#ifndef __cpp_binary_literals +//# error "__cpp_binary_literals" +//#endif + +#ifndef __cpp_init_captures +# error "__cpp_init_captures" // { dg-error "error" } +#endif + +#ifndef __cpp_generic_lambdas +# error "__cpp_generic_lambdas" // { dg-error "error" } +#endif + +#ifndef __cpp_decltype_auto +# error "__cpp_decltype_auto" // { dg-error "error" } +#endif + +#ifndef __cpp_return_type_deduction +# error "__cpp_return_type_deduction" // { dg-error "error" } +#endif + +// Aggregate initializers not in yet. +//#ifdef __cpp_aggregate_nsdmi +//# error "__cpp_aggregate_nsdmi" +//#endif + +#ifndef __cpp_variable_templates +# error "__cpp_variable_templates" // { dg-error "error" } +#endif + +#ifndef __cpp_digit_separators +# error "__cpp_digit_separators" // { dg-error "error" } +#endif + +#ifndef __cpp_attribute_deprecated +# error "__cpp_attribute_deprecated" // { dg-error "error" } +#endif + +// Sized deallocation not in yet. +//#ifdef __cpp_sized_deallocation +//# error "__cpp_sized_deallocation" +//#endif diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx98.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx98.C new file mode 100644 index 00000000000..a0a2b75e30b --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx98.C @@ -0,0 +1,9 @@ +// { dg-do compile { target c++98_only } } +// { dg-options "" } + +// These C++14 features are allowed in C++98 in non-ANSI modes. +#ifndef __cpp_binary_literals +# error "__cpp_binary_literals" +#elif __cpp_binary_literals != 201304 +# error "__cpp_binary_literals != 201304" +#endif diff --git a/gcc/testsuite/g++.dg/cpp1y/paren1.C b/gcc/testsuite/g++.dg/cpp1y/paren1.C new file mode 100644 index 00000000000..809f2510099 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/paren1.C @@ -0,0 +1,31 @@ +// PR c++/63437 +// { dg-do compile { target c++11 } } + +struct X // movable but not copyable +{ + X() = default; + X(X &&) = default; + + X(const X &) = delete; +}; + +X non_parenthesized() +{ + X x; + return x; // works +} + +X parenthesized() +{ + X x; + return (x); // error: use of deleted function 'X::X(const X&)' +} + +template <class T> +T parenthesized_t() +{ + T t; + return (t); +} + +template X parenthesized_t<X>(); diff --git a/gcc/testsuite/g++.dg/cpp1y/phoobhar.h b/gcc/testsuite/g++.dg/cpp1y/phoobhar.h new file mode 100644 index 00000000000..7feec364996 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/phoobhar.h @@ -0,0 +1,16 @@ + +int +phoo(); + +int +bhar(); + +#ifndef __has_include_next +# error "__has_include_next" +#else +# if __has_include_next("phoobhar.h") +# include_next "phoobhar.h" +# else +# error "__has_include_next(\"phoobhar.h\")" +# endif +#endif diff --git a/gcc/testsuite/g++.dg/cpp1y/pr57644.C b/gcc/testsuite/g++.dg/cpp1y/pr57644.C new file mode 100644 index 00000000000..080572168dd --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/pr57644.C @@ -0,0 +1,13 @@ +// { dg-do compile { target c++1y } } + +struct Foo +{ + unsigned i: 32; +}; + +int +main() +{ + Foo f{}; + return f.i; +} diff --git a/gcc/testsuite/g++.dg/cpp1y/testinc/phoobhar.h b/gcc/testsuite/g++.dg/cpp1y/testinc/phoobhar.h new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/testinc/phoobhar.h diff --git a/gcc/testsuite/g++.dg/gomp/pr63249.C b/gcc/testsuite/g++.dg/gomp/pr63249.C new file mode 100644 index 00000000000..80f763a4c5f --- /dev/null +++ b/gcc/testsuite/g++.dg/gomp/pr63249.C @@ -0,0 +1,35 @@ +// PR c++/63249 +// { dg-do compile } +// { dg-options "-Wall -W -fopenmp" } + +template <int N> +int +foo (int *v, int A, int B) // { dg-bogus "set but not used" } +{ + int r = 0; + int a = 2; // { dg-bogus "set but not used" } + int b = 4; // { dg-bogus "set but not used" } +#pragma omp target map(to: v[a:b]) + r |= v[3]; +#pragma omp target map(to: v[A:B]) + r |= v[3]; + return r; +} + +template <typename T> +int +bar (T *v, T A, T B) // { dg-bogus "set but not used" } +{ + T r = 0, a = 2, b = 4; // { dg-bogus "set but not used" } +#pragma omp target map(to: v[a:b]) + r |= v[3]; +#pragma omp target map(to: v[A:B]) + r |= v[3]; + return r; +} + +int +baz (int *v, int A, int B) +{ + return foo<0> (v, A, B) + bar (v, A, B); +} diff --git a/gcc/testsuite/g++.dg/init/const9.C b/gcc/testsuite/g++.dg/init/const9.C index ba1dfd4bc46..d733e953332 100644 --- a/gcc/testsuite/g++.dg/init/const9.C +++ b/gcc/testsuite/g++.dg/init/const9.C @@ -1,5 +1,5 @@ // PR c++/55893 -// { dg-final { scan-assembler-not "rodata" } } +// { dg-final { scan-assembler-not "rodata" { target { ! hppa*-*-* } } } } struct foo { diff --git a/gcc/testsuite/g++.dg/ipa/devirt-28a.C b/gcc/testsuite/g++.dg/ipa/devirt-28a.C new file mode 100644 index 00000000000..65d5fcdf3e2 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/devirt-28a.C @@ -0,0 +1,15 @@ +// PR c++/58678 +// { dg-options "-O3 -flto -shared -fPIC -Wl,--no-undefined" } +// { dg-do link { target { { gld && fpic } && shared } } } + +struct A { + virtual ~A(); +}; +struct B : A { + virtual int m_fn1(); +}; +void fn1(B* b) { + delete b; +} + +int main() {} diff --git a/gcc/testsuite/g++.dg/ipa/devirt-39.C b/gcc/testsuite/g++.dg/ipa/devirt-39.C index fbeea126e19..8cd734d77c0 100644 --- a/gcc/testsuite/g++.dg/ipa/devirt-39.C +++ b/gcc/testsuite/g++.dg/ipa/devirt-39.C @@ -1,5 +1,5 @@ // PR c++/61214 -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2" } */ struct Base { @@ -24,5 +24,4 @@ int main() return 0; } -/* { dg-final { scan-tree-dump-not "OBJ_TYPE_REF" "optimized" } } */ -/* { dg-final { cleanup-tree-dump "optimized" } } */ +/* { dg-final { scan-assembler-not "_ZN3Foo5cloneEv" } } */ diff --git a/gcc/testsuite/g++.dg/ipa/devirt-40.C b/gcc/testsuite/g++.dg/ipa/devirt-40.C new file mode 100644 index 00000000000..9c3bdf5e9df --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/devirt-40.C @@ -0,0 +1,21 @@ +// PR c++/62224 +// { dg-options "-O2" } +// For 4.9, we don't want to devirtualize f and thus create a reference to g. + +struct A +{ + virtual void f () = 0; +}; + +class B : A +{ + virtual void f () { g(); } + void g(); +}; + +void h (A *a) +{ + a->f (); +} + +// { dg-final { scan-assembler-not "_ZN1B1gEv" } } diff --git a/gcc/testsuite/g++.dg/ipa/pr61654.C b/gcc/testsuite/g++.dg/ipa/pr61654.C new file mode 100644 index 00000000000..d07e4586bdb --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr61654.C @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* The bug only presented itself on a 32 bit i386 but in theory it might also + pop up elsewhere and we do not want to put -m32 options to testcase + options. */ + +struct A +{ + virtual int a (int, int = 0) = 0; + void b (); + void c (); + int d; +}; + +struct B : virtual A +{ + int a (int, int); + int e; +}; + +int f; + +void +A::b () +{ + a (0); +} + +void +A::c () +{ + a (f); +} + +int +B::a (int, int) +{ + return e; +} diff --git a/gcc/testsuite/g++.dg/ipa/pr63306.C b/gcc/testsuite/g++.dg/ipa/pr63306.C new file mode 100644 index 00000000000..e22a4c2a0d0 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr63306.C @@ -0,0 +1,14 @@ +// PR c++/63306 +// { dg-do compile { target c++11 } } + +template <typename...> +class A; + +class B +{ + B (const int &, const A<int, int> &); +}; + +B::B (const int &, const A<int, int> &) +{ +} diff --git a/gcc/testsuite/g++.dg/lto/pr62026.C b/gcc/testsuite/g++.dg/lto/pr62026.C new file mode 100644 index 00000000000..63766a85b98 --- /dev/null +++ b/gcc/testsuite/g++.dg/lto/pr62026.C @@ -0,0 +1,22 @@ +// { dg-lto-do link } +// { dg-lto-options {{-flto -O3 -r -nostdlib}} } +class C; +class F { + virtual C m_fn1(); +}; +class C { + public: + virtual int *m_fn3(int); +}; +class G : F, C { + int offsets; + int *m_fn3(int); +}; +C *a; +int *G::m_fn3(int) { + if (offsets) return 0; +} + +void fn1() { + for (;;) a->m_fn3(0); +} diff --git a/gcc/testsuite/g++.dg/opt/devirt4.C b/gcc/testsuite/g++.dg/opt/devirt4.C index 5a24eecbd0a..72f56afcadc 100644 --- a/gcc/testsuite/g++.dg/opt/devirt4.C +++ b/gcc/testsuite/g++.dg/opt/devirt4.C @@ -1,8 +1,7 @@ // PR lto/53808 -// Devirtualization + inlining should produce a non-virtual -// call to ~foo. -// { dg-options "-O -fdevirtualize" } -// { dg-final { scan-assembler "_ZN3fooD2Ev" } } +// Devirtualization should not produce an external ref to ~bar. +// { dg-options "-O2" } +// { dg-final { scan-assembler-not "_ZN3barD0Ev" } } struct foo { virtual ~foo(); diff --git a/gcc/testsuite/g++.dg/opt/devirt5.C b/gcc/testsuite/g++.dg/opt/devirt5.C new file mode 100644 index 00000000000..f839cbeae20 --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/devirt5.C @@ -0,0 +1,19 @@ +// PR c++/61659 +// { dg-options "-O3" } +// { dg-final { scan-assembler-not "_ZN6parserIiE9getOptionEv" } } + +struct generic_parser_base { + virtual void getOption(); + void getExtraOptionNames() { getOption(); } +}; +template <class DataType> struct parser : public generic_parser_base { + virtual void getOption() {} +}; +struct PassNameParser : public parser<int> { + PassNameParser(); +}; +struct list { + PassNameParser Parser; + virtual void getExtraOptionNames() { return Parser.getExtraOptionNames(); } +}; +list PassList; diff --git a/gcc/testsuite/g++.dg/opt/pr62146.C b/gcc/testsuite/g++.dg/opt/pr62146.C new file mode 100644 index 00000000000..dbe41743424 --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/pr62146.C @@ -0,0 +1,51 @@ +/* PR rtl-optimization/62146 */ +/* { dg-do compile } */ +/* { dg-options "-O2 " } */ +class F +{ +public: + virtual ~ F (); +}; +template < class CL > class G:public F +{ + int *member_; +public: + G ( int *b): member_ (0) + { + } +}; + +class D +{ +public: + template < class CL > void RegisterNonTagCallback (int, + void (CL:: + *p3) ()) + { + InternalRegisterNonTag (p3 ? new G < CL > ( 0) : 0); + } void InternalRegisterNonTag (F *); +}; + +void fn1 (); +class C1 +{ + void foo(); + class TokenType + { + public: + void AddToken () + { + } + }; + C1::TokenType bar_t; +}; +D a; +void C1::foo() +{ + if (&bar_t) + fn1 (); + for (int i = 0; i < sizeof 0; ++i) + a.RegisterNonTagCallback (0, &TokenType::AddToken); +} + +/* { dg-final { scan-assembler-not "mov.*_ZN2C19TokenType8AddTokenEv, .\\\(" } } */ diff --git a/gcc/testsuite/g++.dg/pr62079.C b/gcc/testsuite/g++.dg/pr62079.C new file mode 100644 index 00000000000..919c3e5de36 --- /dev/null +++ b/gcc/testsuite/g++.dg/pr62079.C @@ -0,0 +1,78 @@ +// { dg-do compile } +// { dg-options "-std=c++11 -O2 -fnon-call-exceptions" } + +template < typename > class allocator; + +template < class _CharT > struct char_traits; +template < typename _CharT, typename _Traits = char_traits < _CharT >, + typename _Alloc = allocator < _CharT > >class basic_string; +typedef basic_string < char >string; + +template < typename _Tp > class new_allocator +{ + template < typename _Tp1 > struct rebind + { + typedef new_allocator < _Tp1 > other; + }; +}; + +template < typename _Tp > using __allocator_base = new_allocator < _Tp >; +template < typename _Tp > class allocator:public __allocator_base < _Tp > +{ +}; + +template < typename _CharT, typename _Traits, typename _Alloc > + class basic_string +{ +public: + basic_string (const _CharT * __s, const _Alloc & __a = _Alloc ()); + ~basic_string ()noexcept; +}; + +template < typename T > struct add_reference +{ + typedef T & type; +}; + +template < typename ... Values > class tuple; +template <> class tuple <> +{ +}; + +template < typename Head, typename ... Tail > class tuple < Head, Tail ... >:private tuple < + Tail ... + > +{ + typedef tuple < Tail ... >inherited; +public: + template < typename ... VValues > + tuple (const tuple < VValues ... >&other):inherited (other.tail ()), + m_head (other.head ()) + { + } + typename add_reference < const Head >::type head () const + { + return m_head; + } + const inherited & tail () const + { + return *this; + } + Head m_head; +}; + +template < typename T > struct make_tuple_result +{ + typedef T type; +}; + +template < typename ... Values > + tuple < typename make_tuple_result < + Values >::type ... >make_tuple (const Values & ... values); + +int +main () +{ + tuple < int, float, string > t3c = + make_tuple (17, 2.718281828, string ("Fun")); +} diff --git a/gcc/testsuite/g++.dg/template/friend56.C b/gcc/testsuite/g++.dg/template/friend56.C new file mode 100644 index 00000000000..7dd5d486f86 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/friend56.C @@ -0,0 +1,13 @@ +// Make sure we don't mistakenly mark f as DECL_COMDAT. +// { dg-final { scan-assembler "_Z1fv" } } + +void f(); + +template <class T> struct A +{ + friend void f(); +}; + +A<int> a; + +void f() { } diff --git a/gcc/testsuite/g++.dg/template/ptrmem29.C b/gcc/testsuite/g++.dg/template/ptrmem29.C new file mode 100644 index 00000000000..7700c0b9722 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/ptrmem29.C @@ -0,0 +1,10 @@ +// PR c++/62659 + +struct D { + typedef int (D::*cont_func)(); + template <cont_func> struct B; + template <cont_func cont_f> void wait(B<cont_f> ***); + + int done(); + template <bool> void fix() { wait<&D::done>(0); } +}; diff --git a/gcc/testsuite/g++.dg/template/spec38.C b/gcc/testsuite/g++.dg/template/spec38.C new file mode 100644 index 00000000000..6f06f149584 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/spec38.C @@ -0,0 +1,6 @@ +// PR ipa/61659 + +// { dg-final { scan-assembler "_Z1fIiEvPT_" } } + +template <typename T> inline void f (T *); +template <> void f (int *) { } diff --git a/gcc/testsuite/g++.dg/torture/pr62121.C b/gcc/testsuite/g++.dg/torture/pr62121.C new file mode 100644 index 00000000000..de1196a62e1 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr62121.C @@ -0,0 +1,12 @@ +// { dg-do compile } +class A +{ + virtual double operator()(); +}; +class B : A +{ +public: + double operator()(); +}; +extern B a[]; +int b = a[0](); diff --git a/gcc/testsuite/g++.dg/torture/pr62175.C b/gcc/testsuite/g++.dg/torture/pr62175.C new file mode 100644 index 00000000000..bcdea61e1bf --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr62175.C @@ -0,0 +1,36 @@ +// { dg-do compile } +// { dg-additional-options "-ftrapv" } + +struct B { + B(int = 0); +}; +int c; +int *d; +struct G { + G(); + int numProcs_; +}; +int fn1(); +B fn2() { + if (c) + return 0; + return B(); +} + +long &fn3(long &p1, long &p2) { + if (p2 < p1) + return p2; + return p1; +} + +void fn4(long p1) { + long a = fn1(); + fn2(); + int b = fn3(p1, a); + for (int i; i < b; ++i) + d[0] = 0; + for (; a < p1; ++a) + d[a] = 0; +} + +G::G() { fn4(numProcs_ + 1); } diff --git a/gcc/testsuite/g++.dg/ubsan/pr61272.C b/gcc/testsuite/g++.dg/ubsan/pr61272.C new file mode 100644 index 00000000000..064678d37b8 --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr61272.C @@ -0,0 +1,24 @@ +// PR sanitizer/61272 +// { dg-do compile } +// { dg-options "-fsanitize=undefined -std=c++11" } + +namespace std +{ + template < typename _Tp > class allocator; + template < typename _Alloc > struct allocator_traits { + private: + template < typename _Tp > auto construct ( _Alloc & __a, _Tp * __p)-> // { dg-error "is private" } + decltype (_S_construct (__a, __p)) { } + }; + namespace __gnu_cxx + { + template < typename _Alloc > struct __alloc_traits:std::allocator_traits < _Alloc > // { dg-error "within this context" } + { + typedef std::allocator_traits < _Alloc > _Base_type; + using _Base_type::construct; + }; + template < typename _Tp, typename _Alloc > struct _Vector_base { typedef typename __gnu_cxx::__alloc_traits < _Alloc >::template rebind < _Tp >::other _Tp_alloc_type; }; // { dg-error "no class template" } + template < typename _Tp, typename _Alloc = std::allocator < _Tp > >class vector : protected _Vector_base < _Tp, _Alloc > { }; + template < typename NumberT > struct Point2d { }; + typedef Point2d < int >GdsPoint; + class GdsPointList : public vector < GdsPoint > {};}} diff --git a/gcc/testsuite/g++.dg/warn/Wunused-parm-6.C b/gcc/testsuite/g++.dg/warn/Wunused-parm-6.C new file mode 100644 index 00000000000..95fb7e2dbe4 --- /dev/null +++ b/gcc/testsuite/g++.dg/warn/Wunused-parm-6.C @@ -0,0 +1,8 @@ +// PR c++/61465 +// { dg-do compile { target c++11 } } +// { dg-options "-Wunused-but-set-parameter" } + +struct Foo { + Foo(void* x) : y{static_cast<char*>(x)} {} + char* y; +}; diff --git a/gcc/testsuite/gcc.c-torture/compile/pr63282.c b/gcc/testsuite/gcc.c-torture/compile/pr63282.c new file mode 100644 index 00000000000..cb23278d50d --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr63282.c @@ -0,0 +1,13 @@ +/* PR inline-asm/63282 */ + +void bar (void); + +void +foo (void) +{ + asm volatile goto ("" : : : : a, b); +a: + bar (); +b: + return; +} diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-1.c b/gcc/testsuite/gcc.dg/darwin-minversion-1.c index d8a3243bb55..6221d617b2e 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-1.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-1.c @@ -2,7 +2,8 @@ /* { dg-options "-mmacosx-version-min=10.1" } */ /* { dg-do run { target *-*-darwin* } } */ -int main(void) +int +main () { #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 1010 fail me; diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-2.c b/gcc/testsuite/gcc.dg/darwin-minversion-2.c index fd4975a5292..8e18d5273a6 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-2.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-2.c @@ -2,7 +2,8 @@ /* { dg-options "-mmacosx-version-min=10.1 -mmacosx-version-min=10.3" } */ /* { dg-do run { target *-*-darwin* } } */ -int main(void) +int +main () { #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 1030 fail me; diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-3.c b/gcc/testsuite/gcc.dg/darwin-minversion-3.c index d0c5934b449..4fcb9693cd4 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-3.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-3.c @@ -2,7 +2,8 @@ /* { dg-options "-mmacosx-version-min=10.4.10" } */ /* { dg-do compile { target *-*-darwin* } } */ -int main(void) +int +main () { #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 1040 fail me; diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-4.c b/gcc/testsuite/gcc.dg/darwin-minversion-4.c new file mode 100644 index 00000000000..1cb42ebe3e9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/darwin-minversion-4.c @@ -0,0 +1,12 @@ +/* Test that major versions greater than 9 work and have the additional 0. */ +/* { dg-options "-mmacosx-version-min=10.10.0" } */ +/* { dg-do compile { target *-*-darwin* } } */ + +int +main () +{ +#if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ != 101000 + fail me; +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr61053.c b/gcc/testsuite/gcc.dg/pr61053.c index 4fd531974f7..e270420309f 100644 --- a/gcc/testsuite/gcc.dg/pr61053.c +++ b/gcc/testsuite/gcc.dg/pr61053.c @@ -31,17 +31,17 @@ _Alignas (long double) int ild; _Alignas (char) long int lic; /* { dg-error "cannot reduce alignment" } */ _Alignas (short int) long int lis; /* { dg-error "cannot reduce alignment" } */ -_Alignas (int) long int lii; /* { dg-error "cannot reduce alignment" "" { target { ! { ia32 } } } } */ +_Alignas (int) long int lii; /* { dg-error "cannot reduce alignment" "" { target { ! { ilp32 } } } } */ _Alignas (long int) long int lil; _Alignas (long long int) long int lill; -_Alignas (float) long int lif; /* { dg-error "cannot reduce alignment" "" { target { ! { ia32 } } } } */ +_Alignas (float) long int lif; /* { dg-error "cannot reduce alignment" "" { target { ! { ilp32 } } } } */ _Alignas (double) long int lid; _Alignas (long double) long int lild; _Alignas (char) long long int llic; /* { dg-error "cannot reduce alignment" } */ _Alignas (short int) long long int llis; /* { dg-error "cannot reduce alignment" } */ _Alignas (int) long long int llii; /* { dg-error "cannot reduce alignment" "" { target { ! { ia32 } } } } */ -_Alignas (long int) long long int llil; +_Alignas (long int) long long int llil; /* { dg-error "cannot reduce alignment" "" { target { x32 } } } */ _Alignas (long long int) long long int llill; _Alignas (float) long long int llif; /* { dg-error "cannot reduce alignment" "" { target { ! { ia32 } } } } */ _Alignas (double) long long int llid; @@ -59,7 +59,7 @@ _Alignas (long double) float fld; _Alignas (char) double dc; /* { dg-error "cannot reduce alignment" } */ _Alignas (short int) double ds; /* { dg-error "cannot reduce alignment" } */ _Alignas (int) double di; /* { dg-error "cannot reduce alignment" "" { target { ! { ia32 } } } } */ -_Alignas (long int) double dl; +_Alignas (long int) double dl; /* { dg-error "cannot reduce alignment" "" { target { x32 } } } */ _Alignas (long long int) double dll; _Alignas (float) double df; /* { dg-error "cannot reduce alignment" "" { target { ! { ia32 } } } } */ _Alignas (double) double dd; diff --git a/gcc/testsuite/gcc.dg/pr63186.c b/gcc/testsuite/gcc.dg/pr63186.c new file mode 100644 index 00000000000..b3648757c7a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63186.c @@ -0,0 +1,30 @@ +/* { dg-do link } */ +/* { dg-options "-O2" } */ +void *a; +int b, c, d; + +void +bar () +{ + switch (c) + { + case 0: + lab: + __asm__ (""); + return; + default: + break; + } + b = 0; + d = 0; + a = &&lab; +} + +void +foo () +{ + bar (); +} +main() +{ +} diff --git a/gcc/testsuite/gcc.dg/pr63284.c b/gcc/testsuite/gcc.dg/pr63284.c new file mode 100644 index 00000000000..dc7fc28b87e --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63284.c @@ -0,0 +1,42 @@ +/* PR debug/63284 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +int a[10], *b, *d, c, f; +int fn2 (void); +void fn3 (void); +void fn4 (int); + +static int +fn1 (int x) +{ + int e = a[0]; + if (e) + return 1; + if (b) + switch (x) + { + case 1: + if (d) + e = fn2 (); + else + fn3 (); + break; + case 0: + if (d) + { + fn3 (); + if (c) + fn4 (1); + } + else + fn4 (0); + } + return e; +} + +void +fn6 (void) +{ + f = fn1 (0); +} diff --git a/gcc/testsuite/gcc.dg/pr63342.c b/gcc/testsuite/gcc.dg/pr63342.c new file mode 100644 index 00000000000..499d508c13f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63342.c @@ -0,0 +1,26 @@ +/* PR debug/63342 */ +/* { dg-do compile } */ +/* { dg-options "-g -O2" } */ +/* { dg-additional-options "-fpic" { target fpic } } */ + +static __thread double u[9], v[9]; + +void +foo (double **p, double **q) +{ + *p = u; + *q = v; +} + +double +bar (double x) +{ + int i; + double s = 0.0; + for (i = 0; i < 9; i++) + { + double a = x + v[i]; + s += u[i] * a * a; + } + return s; +} diff --git a/gcc/testsuite/gcc.dg/torture/float128-exact-underflow.c b/gcc/testsuite/gcc.dg/torture/float128-exact-underflow.c new file mode 100644 index 00000000000..ea11f26e22d --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/float128-exact-underflow.c @@ -0,0 +1,41 @@ +/* Test that exact underflow in __float128 signals the underflow + exception if trapping is enabled, but does not raise the flag + otherwise. */ + +/* { dg-do run { target i?86-*-*gnu* x86_64-*-*gnu* } } */ +/* { dg-options "-D_GNU_SOURCE" } */ +/* { dg-require-effective-target fenv_exceptions } */ + +#include <fenv.h> +#include <setjmp.h> +#include <signal.h> +#include <stdlib.h> + +volatile sig_atomic_t caught_sigfpe; +sigjmp_buf buf; + +static void +handle_sigfpe (int sig) +{ + caught_sigfpe = 1; + siglongjmp (buf, 1); +} + +int +main (void) +{ + volatile __float128 a = 0x1p-16382q, b = 0x1p-2q; + volatile __float128 r; + r = a * b; + if (fetestexcept (FE_UNDERFLOW)) + abort (); + if (r != 0x1p-16384q) + abort (); + feenableexcept (FE_UNDERFLOW); + signal (SIGFPE, handle_sigfpe); + if (sigsetjmp (buf, 1) == 0) + r = a * b; + if (!caught_sigfpe) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.dg/torture/pr63380-1.c b/gcc/testsuite/gcc.dg/torture/pr63380-1.c new file mode 100644 index 00000000000..29deface81d --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr63380-1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ + +int a = 0, b = 1, c = 0, d = 1, e, f, g, h; +int +main () +{ + e = 1 >> d; + f = ((31 / (1 > e)) || c) / 2; + g = b || a; + h = 31 / g; + if (!h) + __builtin_abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.dg/torture/pr63380-2.c b/gcc/testsuite/gcc.dg/torture/pr63380-2.c new file mode 100644 index 00000000000..f4cbc43eb7d --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr63380-2.c @@ -0,0 +1,10 @@ +/* { dg-do run } */ + +int a = 0, b = 0, c = 0, d, e; +int +main (void) +{ + d = ((20 % (1 != b)) && c) + 2147483647; + e = 20 % (a >= 0); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/vshuf-4.inc b/gcc/testsuite/gcc.dg/torture/vshuf-4.inc index c50fa8e9dd5..d0cb7387ca3 100644 --- a/gcc/testsuite/gcc.dg/torture/vshuf-4.inc +++ b/gcc/testsuite/gcc.dg/torture/vshuf-4.inc @@ -23,7 +23,8 @@ T (19, 3, 2, 1, 0) \ T (20, 0, 4, 1, 5) \ T (21, 2, 6, 3, 7) \ T (22, 1, 2, 3, 0) \ -T (23, 2, 1, 0, 3) +T (23, 2, 1, 0, 3) \ +T (24, 2, 5, 6, 3) #define EXPTESTS \ T (116, 1, 2, 4, 3) \ T (117, 7, 3, 3, 0) \ @@ -31,7 +32,6 @@ T (118, 5, 3, 2, 7) \ T (119, 0, 3, 5, 6) \ T (120, 0, 0, 1, 5) \ T (121, 4, 6, 2, 1) \ -T (122, 2, 5, 6, 3) \ T (123, 4, 6, 3, 2) \ T (124, 4, 7, 5, 6) \ T (125, 0, 4, 2, 4) \ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr61144.c b/gcc/testsuite/gcc.dg/tree-ssa/pr61144.c new file mode 100644 index 00000000000..cd34b144e89 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr61144.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-weak "" } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +static int dummy = 0; +extern int foo __attribute__((__weak__, __alias__("dummy"))); +int bar() { if (foo) return 1; return 0; } +/* { dg-final { scan-tree-dump-not "return 0" "optimized"} } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr59594.c b/gcc/testsuite/gcc.dg/vect/pr59594.c index 6c0b5880ea1..14a86ed2d9b 100644 --- a/gcc/testsuite/gcc.dg/vect/pr59594.c +++ b/gcc/testsuite/gcc.dg/vect/pr59594.c @@ -3,7 +3,7 @@ #include "tree-vect.h" #define N 1024 -int b[N + 1]; +int b[N + 2]; int main () diff --git a/gcc/testsuite/gcc.dg/vect/pr60196-1.c b/gcc/testsuite/gcc.dg/vect/pr60196-1.c new file mode 100644 index 00000000000..10ed4afebdf --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr60196-1.c @@ -0,0 +1,34 @@ +/* PR tree-optimization/63189 */ +/* { dg-additional-options "-fwrapv" } */ +/* { dg-do run } */ + +#include "tree-vect.h" + +__attribute__((noinline, noclone)) static int +bar (const short *a, int len) +{ + int x; + int x1 = 0; + + for (x = 0; x < len; x++) + x1 += x * a[x]; + return x1; +} + +__attribute__((noinline, noclone)) void +foo (void) +{ + short stuff[9] = {1, 1, 1, 1, 1, 1, 1, 1, 1 }; + if (bar (stuff, 9) != 36) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr60196-2.c b/gcc/testsuite/gcc.dg/vect/pr60196-2.c new file mode 100644 index 00000000000..b2059c20cd5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr60196-2.c @@ -0,0 +1,33 @@ +/* PR tree-optimization/63189 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +static const short a[8] = {1, 1, 1, 1, 1, 1, 1, 1 }; +static const unsigned char b[8] = {0, 0, 0, 0, 0, 0, 0, 0 }; + +__attribute__((noinline, noclone)) static int +bar (void) +{ + int sum = 0, i; + for (i = 0; i < 8; ++i) + sum += a[i] * b[i]; + return sum; +} + +__attribute__((noinline, noclone)) void +foo (void) +{ + if (bar () != 0) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr62075.c b/gcc/testsuite/gcc.dg/vect/pr62075.c new file mode 100644 index 00000000000..798490e8752 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr62075.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ + +int a[16][2]; +struct A +{ + int b[16][2]; + int c[16][1]; +}; + +void +foo (struct A *x) +{ + int i; + for (i = 0; i < 16; ++i) + { + x->b[i][0] = a[i][0]; + x->c[i][0] = 0 != a[i][0]; + x->b[i][1] = a[i][1]; + } +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63189.c b/gcc/testsuite/gcc.dg/vect/pr63189.c new file mode 100644 index 00000000000..da6fba4b1b3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63189.c @@ -0,0 +1,26 @@ +/* PR tree-optimization/63189 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +short int d[16] = { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 }; + +__attribute__((noinline, noclone)) void +foo (void) +{ + int j, s = 0; + for (j = 0; j < 8; j++) + s += d[j] * j; + if (s != 7) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63341-1.c b/gcc/testsuite/gcc.dg/vect/pr63341-1.c new file mode 100644 index 00000000000..4aece7bbd24 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63341-1.c @@ -0,0 +1,32 @@ +/* PR tree-optimization/63341 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +typedef union U { unsigned short s; unsigned char c; } __attribute__((packed)) U; +struct S { char e __attribute__((aligned (64))); U s[32]; }; +struct S t = {0, {{1}, {2}, {3}, {4}, {5}, {6}, {7}, {8}, + {9}, {10}, {11}, {12}, {13}, {14}, {15}, {16}, + {17}, {18}, {19}, {20}, {21}, {22}, {23}, {24}, + {25}, {26}, {27}, {28}, {29}, {30}, {31}, {32}}}; +unsigned short d[32] = { 1 }; + +__attribute__((noinline, noclone)) void +foo () +{ + int i; + for (i = 0; i < 32; i++) + d[i] = t.s[i].s; + if (__builtin_memcmp (d, t.s, sizeof d)) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63341-2.c b/gcc/testsuite/gcc.dg/vect/pr63341-2.c new file mode 100644 index 00000000000..4e7d2bb1f5a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63341-2.c @@ -0,0 +1,35 @@ +/* PR tree-optimization/63341 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +typedef union U { unsigned short s; unsigned char c; } __attribute__((packed)) U; +struct S { char e __attribute__((aligned (64))); U s[32]; }; +struct S t = {0, {{0x5010}, {0x5111}, {0x5212}, {0x5313}, {0x5414}, {0x5515}, {0x5616}, {0x5717}, + {0x5818}, {0x5919}, {0x5a1a}, {0x5b1b}, {0x5c1c}, {0x5d1d}, {0x5e1e}, {0x5f1f}, + {0x6020}, {0x6121}, {0x6222}, {0x6323}, {0x6424}, {0x6525}, {0x6626}, {0x6727}, + {0x6828}, {0x6929}, {0x6a2a}, {0x6b2b}, {0x6c2c}, {0x6d2d}, {0x6e2e}, {0x6f2f}}}; +unsigned short d[32] = { 1 }; + +__attribute__((noinline, noclone)) void +foo () +{ + int i; + for (i = 0; i < 32; i++) + d[i] = t.s[i].s + 4; + for (i = 0; i < 32; i++) + if (d[i] != t.s[i].s + 4) + abort (); + else + asm volatile ("" : : : "memory"); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63379.c b/gcc/testsuite/gcc.dg/vect/pr63379.c new file mode 100644 index 00000000000..f6e8fc6a4ce --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63379.c @@ -0,0 +1,43 @@ +/* PR tree-optimization/63379 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +extern void abort (void); + +typedef struct { + int x; + int y; +} Point; + +Point pt_array[25]; + +void __attribute__((noinline,noclone)) +generate_array(void) +{ + unsigned int i; + for (i = 0; i<25; i++) + { + pt_array[i].x = i; + pt_array[i].y = 1000+i; + } +} + +int main() +{ + check_vect (); + generate_array (); + Point min_pt = pt_array[0]; + Point *ptr, *ptr_end; + for (ptr = pt_array+1, ptr_end = pt_array+25; ptr != ptr_end; ++ptr) + { + min_pt.x = (min_pt.x < ptr->x) ? min_pt.x : ptr->x; + min_pt.y = (min_pt.y < ptr->y) ? min_pt.y : ptr->y; + } + + if (min_pt.x != 0 || min_pt.y != 1000) + abort (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr62040.c b/gcc/testsuite/gcc.target/aarch64/pr62040.c new file mode 100644 index 00000000000..cfb4979f885 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr62040.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-g -Os" } */ + +#include "arm_neon.h" + +extern void bar (int32x4_t); + +void +foo () +{ + int32x4x4_t rows; + uint64x2x2_t row01; + + row01.val[0] = vreinterpretq_u64_s32 (rows.val[0]); + row01.val[1] = vreinterpretq_u64_s32 (rows.val[1]); + uint64x1_t row3l = vget_low_u64 (row01.val[0]); + row01.val[0] = vcombine_u64 (vget_low_u64 (row01.val[1]), row3l); + int32x4_t xxx = vreinterpretq_s32_u64 (row01.val[0]); + int32x4_t out = vtrn1q_s32 (xxx, xxx); + bar (out); +} diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c index 782f6d194ca..d1980bc191a 100644 --- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c +++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c @@ -195,20 +195,20 @@ test_vcltzd_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "aarch64_get_lanev16qi" 2 } } */ -int8x1_t +int8_t test_vdupb_lane_s8 (int8x16_t a) { - int8x1_t res; + int8_t res; force_simd (a); res = vdupb_laneq_s8 (a, 2); force_simd (res); return res; } -uint8x1_t +uint8_t test_vdupb_lane_u8 (uint8x16_t a) { - uint8x1_t res; + uint8_t res; force_simd (a); res = vdupb_laneq_u8 (a, 2); force_simd (res); @@ -217,20 +217,20 @@ test_vdupb_lane_u8 (uint8x16_t a) /* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */ -int16x1_t +int16_t test_vduph_lane_s16 (int16x8_t a) { - int16x1_t res; + int16_t res; force_simd (a); res = vduph_laneq_s16 (a, 2); force_simd (res); return res; } -uint16x1_t +uint16_t test_vduph_lane_u16 (uint16x8_t a) { - uint16x1_t res; + uint16_t res; force_simd (a); res = vduph_laneq_u16 (a, 2); force_simd (res); @@ -239,20 +239,20 @@ test_vduph_lane_u16 (uint16x8_t a) /* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */ -int32x1_t +int32_t test_vdups_lane_s32 (int32x4_t a) { - int32x1_t res; + int32_t res; force_simd (a); res = vdups_laneq_s32 (a, 2); force_simd (res); return res; } -uint32x1_t +uint32_t test_vdups_lane_u32 (uint32x4_t a) { - uint32x1_t res; + uint32_t res; force_simd (a); res = vdups_laneq_u32 (a, 2); force_simd (res); @@ -322,24 +322,24 @@ test_vqaddd_u64 (uint64x1_t a, uint64x1_t b) /* { dg-final { scan-assembler-times "\\tuqadd\\ts\[0-9\]+" 1 } } */ -uint32x1_t -test_vqadds_u32 (uint32x1_t a, uint32x1_t b) +uint32_t +test_vqadds_u32 (uint32_t a, uint32_t b) { return vqadds_u32 (a, b); } /* { dg-final { scan-assembler-times "\\tuqadd\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vqaddh_u16 (uint16x1_t a, uint16x1_t b) +uint16_t +test_vqaddh_u16 (uint16_t a, uint16_t b) { return vqaddh_u16 (a, b); } /* { dg-final { scan-assembler-times "\\tuqadd\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vqaddb_u8 (uint8x1_t a, uint8x1_t b) +uint8_t +test_vqaddb_u8 (uint8_t a, uint8_t b) { return vqaddb_u8 (a, b); } @@ -354,40 +354,40 @@ test_vqaddd_s64 (int64x1_t a, int64x1_t b) /* { dg-final { scan-assembler-times "\\tsqadd\\ts\[0-9\]+, s\[0-9\]+" 1 } } */ -int32x1_t -test_vqadds_s32 (int32x1_t a, int32x1_t b) +int32_t +test_vqadds_s32 (int32_t a, int32_t b) { return vqadds_s32 (a, b); } /* { dg-final { scan-assembler-times "\\tsqadd\\th\[0-9\]+, h\[0-9\]+" 1 } } */ -int16x1_t -test_vqaddh_s16 (int16x1_t a, int16x1_t b) +int16_t +test_vqaddh_s16 (int16_t a, int16_t b) { return vqaddh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsqadd\\tb\[0-9\]+, b\[0-9\]+" 1 } } */ -int8x1_t -test_vqaddb_s8 (int8x1_t a, int8x1_t b) +int8_t +test_vqaddb_s8 (int8_t a, int8_t b) { return vqaddb_s8 (a, b); } /* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -int32x1_t -test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c) +int32_t +test_vqdmlalh_s16 (int32_t a, int16_t b, int16_t c) { return vqdmlalh_s16 (a, b, c); } /* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ -int32x1_t -test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) +int32_t +test_vqdmlalh_lane_s16 (int32_t a, int16_t b, int16x4_t c) { return vqdmlalh_lane_s16 (a, b, c, 3); } @@ -395,7 +395,7 @@ test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) /* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ int64x1_t -test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c) +test_vqdmlals_s32 (int64x1_t a, int32_t b, int32_t c) { return vqdmlals_s32 (a, b, c); } @@ -403,23 +403,23 @@ test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c) /* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ int64x1_t -test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) +test_vqdmlals_lane_s32 (int64x1_t a, int32_t b, int32x2_t c) { return vqdmlals_lane_s32 (a, b, c, 1); } /* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -int32x1_t -test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c) +int32_t +test_vqdmlslh_s16 (int32_t a, int16_t b, int16_t c) { return vqdmlslh_s16 (a, b, c); } /* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ -int32x1_t -test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) +int32_t +test_vqdmlslh_lane_s16 (int32_t a, int16_t b, int16x4_t c) { return vqdmlslh_lane_s16 (a, b, c, 3); } @@ -427,7 +427,7 @@ test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) /* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ int64x1_t -test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c) +test_vqdmlsls_s32 (int64x1_t a, int32_t b, int32_t c) { return vqdmlsls_s32 (a, b, c); } @@ -435,55 +435,55 @@ test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c) /* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ int64x1_t -test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) +test_vqdmlsls_lane_s32 (int64x1_t a, int32_t b, int32x2_t c) { return vqdmlsls_lane_s32 (a, b, c, 1); } /* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -int16x1_t -test_vqdmulhh_s16 (int16x1_t a, int16x1_t b) +int16_t +test_vqdmulhh_s16 (int16_t a, int16_t b) { return vqdmulhh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */ -int16x1_t -test_vqdmulhh_lane_s16 (int16x1_t a, int16x4_t b) +int16_t +test_vqdmulhh_lane_s16 (int16_t a, int16x4_t b) { return vqdmulhh_lane_s16 (a, b, 3); } /* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -int32x1_t -test_vqdmulhs_s32 (int32x1_t a, int32x1_t b) +int32_t +test_vqdmulhs_s32 (int32_t a, int32_t b) { return vqdmulhs_s32 (a, b); } /* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */ -int32x1_t -test_vqdmulhs_lane_s32 (int32x1_t a, int32x2_t b) +int32_t +test_vqdmulhs_lane_s32 (int32_t a, int32x2_t b) { return vqdmulhs_lane_s32 (a, b, 1); } /* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -int32x1_t -test_vqdmullh_s16 (int16x1_t a, int16x1_t b) +int32_t +test_vqdmullh_s16 (int16_t a, int16_t b) { return vqdmullh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ -int32x1_t -test_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b) +int32_t +test_vqdmullh_lane_s16 (int16_t a, int16x4_t b) { return vqdmullh_lane_s16 (a, b, 3); } @@ -491,7 +491,7 @@ test_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b) /* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ int64x1_t -test_vqdmulls_s32 (int32x1_t a, int32x1_t b) +test_vqdmulls_s32 (int32_t a, int32_t b) { return vqdmulls_s32 (a, b); } @@ -499,63 +499,63 @@ test_vqdmulls_s32 (int32x1_t a, int32x1_t b) /* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ int64x1_t -test_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b) +test_vqdmulls_lane_s32 (int32_t a, int32x2_t b) { return vqdmulls_lane_s32 (a, b, 1); } /* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -int16x1_t -test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b) +int16_t +test_vqrdmulhh_s16 (int16_t a, int16_t b) { return vqrdmulhh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */ -int16x1_t -test_vqrdmulhh_lane_s16 (int16x1_t a, int16x4_t b) +int16_t +test_vqrdmulhh_lane_s16 (int16_t a, int16x4_t b) { return vqrdmulhh_lane_s16 (a, b, 3); } /* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -int32x1_t -test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b) +int32_t +test_vqrdmulhs_s32 (int32_t a, int32_t b) { return vqrdmulhs_s32 (a, b); } /* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */ -int32x1_t -test_vqrdmulhs_lane_s32 (int32x1_t a, int32x2_t b) +int32_t +test_vqrdmulhs_lane_s32 (int32_t a, int32x2_t b) { return vqrdmulhs_lane_s32 (a, b, 1); } /* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vuqaddb_s8 (int8x1_t a, int8x1_t b) +int8_t +test_vuqaddb_s8 (int8_t a, int8_t b) { return vuqaddb_s8 (a, b); } /* { dg-final { scan-assembler-times "\\tsuqadd\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vuqaddh_s16 (int16x1_t a, int8x1_t b) +int16_t +test_vuqaddh_s16 (int16_t a, int8_t b) { return vuqaddh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsuqadd\\ts\[0-9\]+" 1 } } */ -int32x1_t -test_vuqadds_s32 (int32x1_t a, int8x1_t b) +int32_t +test_vuqadds_s32 (int32_t a, int8_t b) { return vuqadds_s32 (a, b); } @@ -563,31 +563,31 @@ test_vuqadds_s32 (int32x1_t a, int8x1_t b) /* { dg-final { scan-assembler-times "\\tsuqadd\\td\[0-9\]+" 1 } } */ int64x1_t -test_vuqaddd_s64 (int64x1_t a, int8x1_t b) +test_vuqaddd_s64 (int64x1_t a, int8_t b) { return vuqaddd_s64 (a, b); } /* { dg-final { scan-assembler-times "\\tusqadd\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vsqaddb_u8 (uint8x1_t a, int8x1_t b) +uint8_t +test_vsqaddb_u8 (uint8_t a, int8_t b) { return vsqaddb_u8 (a, b); } /* { dg-final { scan-assembler-times "\\tusqadd\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vsqaddh_u16 (uint16x1_t a, int8x1_t b) +uint16_t +test_vsqaddh_u16 (uint16_t a, int8_t b) { return vsqaddh_u16 (a, b); } /* { dg-final { scan-assembler-times "\\tusqadd\\ts\[0-9\]+" 1 } } */ -uint32x1_t -test_vsqadds_u32 (uint32x1_t a, int8x1_t b) +uint32_t +test_vsqadds_u32 (uint32_t a, int8_t b) { return vsqadds_u32 (a, b); } @@ -595,78 +595,78 @@ test_vsqadds_u32 (uint32x1_t a, int8x1_t b) /* { dg-final { scan-assembler-times "\\tusqadd\\td\[0-9\]+" 1 } } */ uint64x1_t -test_vsqaddd_u64 (uint64x1_t a, int8x1_t b) +test_vsqaddd_u64 (uint64x1_t a, int8_t b) { return vsqaddd_u64 (a, b); } /* { dg-final { scan-assembler-times "\\tsqabs\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqabsb_s8 (int8x1_t a) +int8_t +test_vqabsb_s8 (int8_t a) { return vqabsb_s8 (a); } /* { dg-final { scan-assembler-times "\\tsqabs\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqabsh_s16 (int16x1_t a) +int16_t +test_vqabsh_s16 (int16_t a) { return vqabsh_s16 (a); } /* { dg-final { scan-assembler-times "\\tsqabs\\ts\[0-9\]+" 1 } } */ -int32x1_t -test_vqabss_s32 (int32x1_t a) +int32_t +test_vqabss_s32 (int32_t a) { return vqabss_s32 (a); } /* { dg-final { scan-assembler-times "\\tsqneg\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqnegb_s8 (int8x1_t a) +int8_t +test_vqnegb_s8 (int8_t a) { return vqnegb_s8 (a); } /* { dg-final { scan-assembler-times "\\tsqneg\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqnegh_s16 (int16x1_t a) +int16_t +test_vqnegh_s16 (int16_t a) { return vqnegh_s16 (a); } /* { dg-final { scan-assembler-times "\\tsqneg\\ts\[0-9\]+" 1 } } */ -int32x1_t -test_vqnegs_s32 (int32x1_t a) +int32_t +test_vqnegs_s32 (int32_t a) { return vqnegs_s32 (a); } /* { dg-final { scan-assembler-times "\\tsqxtun\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqmovunh_s16 (int16x1_t a) +int8_t +test_vqmovunh_s16 (int16_t a) { return vqmovunh_s16 (a); } /* { dg-final { scan-assembler-times "\\tsqxtun\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqmovuns_s32 (int32x1_t a) +int16_t +test_vqmovuns_s32 (int32_t a) { return vqmovuns_s32 (a); } /* { dg-final { scan-assembler-times "\\tsqxtun\\ts\[0-9\]+" 1 } } */ -int32x1_t +int32_t test_vqmovund_s64 (int64x1_t a) { return vqmovund_s64 (a); @@ -674,23 +674,23 @@ test_vqmovund_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tsqxtn\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqmovnh_s16 (int16x1_t a) +int8_t +test_vqmovnh_s16 (int16_t a) { return vqmovnh_s16 (a); } /* { dg-final { scan-assembler-times "\\tsqxtn\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqmovns_s32 (int32x1_t a) +int16_t +test_vqmovns_s32 (int32_t a) { return vqmovns_s32 (a); } /* { dg-final { scan-assembler-times "\\tsqxtn\\ts\[0-9\]+" 1 } } */ -int32x1_t +int32_t test_vqmovnd_s64 (int64x1_t a) { return vqmovnd_s64 (a); @@ -698,23 +698,23 @@ test_vqmovnd_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tuqxtn\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vqmovnh_u16 (uint16x1_t a) +uint8_t +test_vqmovnh_u16 (uint16_t a) { return vqmovnh_u16 (a); } /* { dg-final { scan-assembler-times "\\tuqxtn\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vqmovns_u32 (uint32x1_t a) +uint16_t +test_vqmovns_u32 (uint32_t a) { return vqmovns_u32 (a); } /* { dg-final { scan-assembler-times "\\tuqxtn\\ts\[0-9\]+" 1 } } */ -uint32x1_t +uint32_t test_vqmovnd_u64 (uint64x1_t a) { return vqmovnd_u64 (a); @@ -753,24 +753,24 @@ test_vqsubd_u64 (uint64x1_t a, uint64x1_t b) /* { dg-final { scan-assembler-times "\\tuqsub\\ts\[0-9\]+" 1 } } */ -uint32x1_t -test_vqsubs_u32 (uint32x1_t a, uint32x1_t b) +uint32_t +test_vqsubs_u32 (uint32_t a, uint32_t b) { return vqsubs_u32 (a, b); } /* { dg-final { scan-assembler-times "\\tuqsub\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vqsubh_u16 (uint16x1_t a, uint16x1_t b) +uint16_t +test_vqsubh_u16 (uint16_t a, uint16_t b) { return vqsubh_u16 (a, b); } /* { dg-final { scan-assembler-times "\\tuqsub\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vqsubb_u8 (uint8x1_t a, uint8x1_t b) +uint8_t +test_vqsubb_u8 (uint8_t a, uint8_t b) { return vqsubb_u8 (a, b); } @@ -785,24 +785,24 @@ test_vqsubd_s64 (int64x1_t a, int64x1_t b) /* { dg-final { scan-assembler-times "\\tsqsub\\ts\[0-9\]+" 1 } } */ -int32x1_t -test_vqsubs_s32 (int32x1_t a, int32x1_t b) +int32_t +test_vqsubs_s32 (int32_t a, int32_t b) { return vqsubs_s32 (a, b); } /* { dg-final { scan-assembler-times "\\tsqsub\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqsubh_s16 (int16x1_t a, int16x1_t b) +int16_t +test_vqsubh_s16 (int16_t a, int16_t b) { return vqsubh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsqsub\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqsubb_s8 (int8x1_t a, int8x1_t b) +int8_t +test_vqsubb_s8 (int8_t a, int8_t b) { return vqsubb_s8 (a, b); } @@ -908,24 +908,24 @@ test_vrsrad_n_u64 (uint64x1_t a, uint64x1_t b) /* { dg-final { scan-assembler-times "\\tsqrshl\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqrshlb_s8 (int8x1_t a, int8x1_t b) +int8_t +test_vqrshlb_s8 (int8_t a, int8_t b) { return vqrshlb_s8 (a, b); } /* { dg-final { scan-assembler-times "\\tsqrshl\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqrshlh_s16 (int16x1_t a, int16x1_t b) +int16_t +test_vqrshlh_s16 (int16_t a, int16_t b) { return vqrshlh_s16 (a, b); } /* { dg-final { scan-assembler-times "\\tsqrshl\\ts\[0-9\]+" 1 } } */ -int32x1_t -test_vqrshls_s32 (int32x1_t a, int32x1_t b) +int32_t +test_vqrshls_s32 (int32_t a, int32_t b) { return vqrshls_s32 (a, b); } @@ -940,24 +940,24 @@ test_vqrshld_s64 (int64x1_t a, int64x1_t b) /* { dg-final { scan-assembler-times "\\tuqrshl\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vqrshlb_u8 (uint8x1_t a, uint8x1_t b) +uint8_t +test_vqrshlb_u8 (uint8_t a, uint8_t b) { return vqrshlb_u8 (a, b); } /* { dg-final { scan-assembler-times "\\tuqrshl\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vqrshlh_u16 (uint16x1_t a, uint16x1_t b) +uint16_t +test_vqrshlh_u16 (uint16_t a, uint16_t b) { return vqrshlh_u16 (a, b); } /* { dg-final { scan-assembler-times "\\tuqrshl\\ts\[0-9\]+" 1 } } */ -uint32x1_t -test_vqrshls_u32 (uint32x1_t a, uint32x1_t b) +uint32_t +test_vqrshls_u32 (uint32_t a, uint32_t b) { return vqrshls_u32 (a, b); } @@ -972,24 +972,24 @@ test_vqrshld_u64 (uint64x1_t a, uint64x1_t b) /* { dg-final { scan-assembler-times "\\tsqshlu\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqshlub_n_s8 (int8x1_t a) +int8_t +test_vqshlub_n_s8 (int8_t a) { return vqshlub_n_s8 (a, 3); } /* { dg-final { scan-assembler-times "\\tsqshlu\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqshluh_n_s16 (int16x1_t a) +int16_t +test_vqshluh_n_s16 (int16_t a) { return vqshluh_n_s16 (a, 4); } /* { dg-final { scan-assembler-times "\\tsqshlu\\ts\[0-9\]+" 1 } } */ -int32x1_t -test_vqshlus_n_s32 (int32x1_t a) +int32_t +test_vqshlus_n_s32 (int32_t a) { return vqshlus_n_s32 (a, 5); } @@ -1004,42 +1004,42 @@ test_vqshlud_n_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tsqshl\\tb\[0-9\]+" 2 } } */ -int8x1_t -test_vqshlb_s8 (int8x1_t a, int8x1_t b) +int8_t +test_vqshlb_s8 (int8_t a, int8_t b) { return vqshlb_s8 (a, b); } -int8x1_t -test_vqshlb_n_s8 (int8x1_t a) +int8_t +test_vqshlb_n_s8 (int8_t a) { return vqshlb_n_s8 (a, 2); } /* { dg-final { scan-assembler-times "\\tsqshl\\th\[0-9\]+" 2 } } */ -int16x1_t -test_vqshlh_s16 (int16x1_t a, int16x1_t b) +int16_t +test_vqshlh_s16 (int16_t a, int16_t b) { return vqshlh_s16 (a, b); } -int16x1_t -test_vqshlh_n_s16 (int16x1_t a) +int16_t +test_vqshlh_n_s16 (int16_t a) { return vqshlh_n_s16 (a, 3); } /* { dg-final { scan-assembler-times "\\tsqshl\\ts\[0-9\]+" 2 } } */ -int32x1_t -test_vqshls_s32 (int32x1_t a, int32x1_t b) +int32_t +test_vqshls_s32 (int32_t a, int32_t b) { return vqshls_s32 (a, b); } -int32x1_t -test_vqshls_n_s32 (int32x1_t a) +int32_t +test_vqshls_n_s32 (int32_t a) { return vqshls_n_s32 (a, 4); } @@ -1060,42 +1060,42 @@ test_vqshld_n_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tuqshl\\tb\[0-9\]+" 2 } } */ -uint8x1_t -test_vqshlb_u8 (uint8x1_t a, uint8x1_t b) +uint8_t +test_vqshlb_u8 (uint8_t a, uint8_t b) { return vqshlb_u8 (a, b); } -uint8x1_t -test_vqshlb_n_u8 (uint8x1_t a) +uint8_t +test_vqshlb_n_u8 (uint8_t a) { return vqshlb_n_u8 (a, 2); } /* { dg-final { scan-assembler-times "\\tuqshl\\th\[0-9\]+" 2 } } */ -uint16x1_t -test_vqshlh_u16 (uint16x1_t a, uint16x1_t b) +uint16_t +test_vqshlh_u16 (uint16_t a, uint16_t b) { return vqshlh_u16 (a, b); } -uint16x1_t -test_vqshlh_n_u16 (uint16x1_t a) +uint16_t +test_vqshlh_n_u16 (uint16_t a) { return vqshlh_n_u16 (a, 3); } /* { dg-final { scan-assembler-times "\\tuqshl\\ts\[0-9\]+" 2 } } */ -uint32x1_t -test_vqshls_u32 (uint32x1_t a, uint32x1_t b) +uint32_t +test_vqshls_u32 (uint32_t a, uint32_t b) { return vqshls_u32 (a, b); } -uint32x1_t -test_vqshls_n_u32 (uint32x1_t a) +uint32_t +test_vqshls_n_u32 (uint32_t a) { return vqshls_n_u32 (a, 4); } @@ -1116,23 +1116,23 @@ test_vqshld_n_u64 (uint64x1_t a) /* { dg-final { scan-assembler-times "\\tsqshrun\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqshrunh_n_s16 (int16x1_t a) +int8_t +test_vqshrunh_n_s16 (int16_t a) { return vqshrunh_n_s16 (a, 2); } /* { dg-final { scan-assembler-times "\\tsqshrun\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqshruns_n_s32 (int32x1_t a) +int16_t +test_vqshruns_n_s32 (int32_t a) { return vqshruns_n_s32 (a, 3); } /* { dg-final { scan-assembler-times "\\tsqshrun\\ts\[0-9\]+" 1 } } */ -int32x1_t +int32_t test_vqshrund_n_s64 (int64x1_t a) { return vqshrund_n_s64 (a, 4); @@ -1140,23 +1140,23 @@ test_vqshrund_n_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tsqrshrun\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqrshrunh_n_s16 (int16x1_t a) +int8_t +test_vqrshrunh_n_s16 (int16_t a) { return vqrshrunh_n_s16 (a, 2); } /* { dg-final { scan-assembler-times "\\tsqrshrun\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqrshruns_n_s32 (int32x1_t a) +int16_t +test_vqrshruns_n_s32 (int32_t a) { return vqrshruns_n_s32 (a, 3); } /* { dg-final { scan-assembler-times "\\tsqrshrun\\ts\[0-9\]+" 1 } } */ -int32x1_t +int32_t test_vqrshrund_n_s64 (int64x1_t a) { return vqrshrund_n_s64 (a, 4); @@ -1164,23 +1164,23 @@ test_vqrshrund_n_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tsqshrn\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqshrnh_n_s16 (int16x1_t a) +int8_t +test_vqshrnh_n_s16 (int16_t a) { return vqshrnh_n_s16 (a, 2); } /* { dg-final { scan-assembler-times "\\tsqshrn\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqshrns_n_s32 (int32x1_t a) +int16_t +test_vqshrns_n_s32 (int32_t a) { return vqshrns_n_s32 (a, 3); } /* { dg-final { scan-assembler-times "\\tsqshrn\\ts\[0-9\]+" 1 } } */ -int32x1_t +int32_t test_vqshrnd_n_s64 (int64x1_t a) { return vqshrnd_n_s64 (a, 4); @@ -1188,23 +1188,23 @@ test_vqshrnd_n_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tuqshrn\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vqshrnh_n_u16 (uint16x1_t a) +uint8_t +test_vqshrnh_n_u16 (uint16_t a) { return vqshrnh_n_u16 (a, 2); } /* { dg-final { scan-assembler-times "\\tuqshrn\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vqshrns_n_u32 (uint32x1_t a) +uint16_t +test_vqshrns_n_u32 (uint32_t a) { return vqshrns_n_u32 (a, 3); } /* { dg-final { scan-assembler-times "\\tuqshrn\\ts\[0-9\]+" 1 } } */ -uint32x1_t +uint32_t test_vqshrnd_n_u64 (uint64x1_t a) { return vqshrnd_n_u64 (a, 4); @@ -1212,23 +1212,23 @@ test_vqshrnd_n_u64 (uint64x1_t a) /* { dg-final { scan-assembler-times "\\tsqrshrn\\tb\[0-9\]+" 1 } } */ -int8x1_t -test_vqrshrnh_n_s16 (int16x1_t a) +int8_t +test_vqrshrnh_n_s16 (int16_t a) { return vqrshrnh_n_s16 (a, 2); } /* { dg-final { scan-assembler-times "\\tsqrshrn\\th\[0-9\]+" 1 } } */ -int16x1_t -test_vqrshrns_n_s32 (int32x1_t a) +int16_t +test_vqrshrns_n_s32 (int32_t a) { return vqrshrns_n_s32 (a, 3); } /* { dg-final { scan-assembler-times "\\tsqrshrn\\ts\[0-9\]+" 1 } } */ -int32x1_t +int32_t test_vqrshrnd_n_s64 (int64x1_t a) { return vqrshrnd_n_s64 (a, 4); @@ -1236,23 +1236,23 @@ test_vqrshrnd_n_s64 (int64x1_t a) /* { dg-final { scan-assembler-times "\\tuqrshrn\\tb\[0-9\]+" 1 } } */ -uint8x1_t -test_vqrshrnh_n_u16 (uint16x1_t a) +uint8_t +test_vqrshrnh_n_u16 (uint16_t a) { return vqrshrnh_n_u16 (a, 2); } /* { dg-final { scan-assembler-times "\\tuqrshrn\\th\[0-9\]+" 1 } } */ -uint16x1_t -test_vqrshrns_n_u32 (uint32x1_t a) +uint16_t +test_vqrshrns_n_u32 (uint32_t a) { return vqrshrns_n_u32 (a, 3); } /* { dg-final { scan-assembler-times "\\tuqrshrn\\ts\[0-9\]+" 1 } } */ -uint32x1_t +uint32_t test_vqrshrnd_n_u64 (uint64x1_t a) { return vqrshrnd_n_u64 (a, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c b/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c index 83f5af5960f..9ca041cb813 100644 --- a/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c @@ -5,8 +5,8 @@ #include "arm_neon.h" -int32x1_t -t_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) +int32_t +t_vqdmlalh_lane_s16 (int32_t a, int16_t b, int16x4_t c) { return vqdmlalh_lane_s16 (a, b, c, 0); } diff --git a/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c index ef94e95d971..40e4c9ff4aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c @@ -6,7 +6,7 @@ #include "arm_neon.h" int64x1_t -t_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) +t_vqdmlals_lane_s32 (int64x1_t a, int32_t b, int32x2_t c) { return vqdmlals_lane_s32 (a, b, c, 0); } diff --git a/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c b/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c index 056dfbb11f0..b3bbc951cef 100644 --- a/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c @@ -5,8 +5,8 @@ #include "arm_neon.h" -int32x1_t -t_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) +int32_t +t_vqdmlslh_lane_s16 (int32_t a, int16_t b, int16x4_t c) { return vqdmlslh_lane_s16 (a, b, c, 0); } diff --git a/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c index 9e351bc360f..5bd643a240d 100644 --- a/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c @@ -6,7 +6,7 @@ #include "arm_neon.h" int64x1_t -t_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) +t_vqdmlsls_lane_s32 (int64x1_t a, int32_t b, int32x2_t c) { return vqdmlsls_lane_s32 (a, b, c, 0); } diff --git a/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c b/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c index fd271e0b3a8..c3761dfd090 100644 --- a/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c @@ -5,8 +5,8 @@ #include "arm_neon.h" -int32x1_t -t_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b) +int32_t +t_vqdmullh_lane_s16 (int16_t a, int16x4_t b) { return vqdmullh_lane_s16 (a, b, 0); } diff --git a/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c index 11033337537..6ed8e3a0b8a 100644 --- a/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c @@ -6,7 +6,7 @@ #include "arm_neon.h" int64x1_t -t_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b) +t_vqdmulls_lane_s32 (int32_t a, int32x2_t b) { return vqdmulls_lane_s32 (a, b, 0); } diff --git a/gcc/testsuite/gcc.target/i386/pr63285.c b/gcc/testsuite/gcc.target/i386/pr63285.c new file mode 100644 index 00000000000..e4df8fb9238 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr63285.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +struct S { int a; }; +struct T { int b, c; } a; +long b; +int c, d; +void bar (int, int); +void baz (void *, int); + +void +foo (struct S *x, int y, int z, void *f, int *p, struct T *e) +{ + while (x) + { + baz (f, &d > p); + if (z & 1) + bar (f > (void *) &f, z); + } + if (c) + { + asm ("" : "+m" (a) : "i" (0)); + y--; + } + if (e->b == e->c) + c = y; + y--; +} diff --git a/gcc/testsuite/gcc.target/i386/pr63495.c b/gcc/testsuite/gcc.target/i386/pr63495.c new file mode 100644 index 00000000000..7f02f37d8ce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr63495.c @@ -0,0 +1,6 @@ +/* PR c/63495 */ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-options "-std=gnu11" } */ + +struct __attribute__ ((aligned (8))) S { char c; }; +_Static_assert (_Alignof (struct S) >= 8, "wrong alignment"); diff --git a/gcc/testsuite/gcc.target/powerpc/pr63335.c b/gcc/testsuite/gcc.target/powerpc/pr63335.c new file mode 100644 index 00000000000..931a8b6e99e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr63335.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc64*-*-* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ + +#include <altivec.h> + +void abort (void); + +vector double vec = (vector double) {99.0, 99.0}; + +int main() { + + int actual = vec_all_nge(vec, vec); + if ( actual != 0) + abort(); + + actual = vec_all_nle(vec, vec); + if ( actual != 0) + abort(); + + actual = vec_any_nge(vec, vec); + if ( actual != 0) + abort(); + + actual = vec_any_nle(vec, vec); + if ( actual != 0) + abort(); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c index e1f0ca8e887..c4e76e6ac0e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c @@ -7,10 +7,4 @@ #include <altivec.h> -#if __LITTLE_ENDIAN__ -#define OFFSET 1 -#else -#define OFFSET 0 -#endif - -double get_value (vector double *p) { return vec_extract (*p, OFFSET); } +double get_value (vector double *p) { return vec_extract (*p, 0); } diff --git a/gcc/testsuite/gfortran.dg/gomp/pr59488-1.f90 b/gcc/testsuite/gfortran.dg/gomp/pr59488-1.f90 new file mode 100644 index 00000000000..9db17dd2769 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr59488-1.f90 @@ -0,0 +1,13 @@ +! PR fortran/59488 +! { dg-do compile } +! { dg-options "-fopenmp" } + + implicit none + integer, parameter :: p(2) = (/ 11, 12 /) + integer :: r + + !$omp parallel do default(none) + do r = 1, 2 + print *, p(r) + end do +end diff --git a/gcc/testsuite/gfortran.dg/gomp/pr59488-2.f90 b/gcc/testsuite/gfortran.dg/gomp/pr59488-2.f90 new file mode 100644 index 00000000000..38f157b81ad --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr59488-2.f90 @@ -0,0 +1,16 @@ +! PR fortran/59488 +! { dg-do compile } +! { dg-options "-fopenmp" } + + implicit none + type t + integer :: s1, s2, s3 + end type + integer :: r + type(t), parameter :: u = t(1, 2, 3) + + !$omp parallel do default(none) + do r = 1, 2 + print *, u + end do +end diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 30b35c8137d..7c011de7db9 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -845,6 +845,19 @@ proc check_effective_target_fpic { } { return 0 } +# Return 1 if -shared is supported, as in no warnings or errors +# emitted, 0 otherwise. + +proc check_effective_target_shared { } { + # Note that M68K has a multilib that supports -fpic but not + # -fPIC, so we need to check both. We test with a program that + # requires GOT references. + return [check_no_compiler_messages shared executable { + extern int foo (void); extern int bar; + int baz (void) { return foo () + bar; } + } "-shared -fpic"] +} + # Return 1 if -pie, -fpie and -fPIE are supported, 0 otherwise. proc check_effective_target_pie { } { diff --git a/gcc/tree-cfgcleanup.c b/gcc/tree-cfgcleanup.c index 51b764f816a..439f273cd50 100644 --- a/gcc/tree-cfgcleanup.c +++ b/gcc/tree-cfgcleanup.c @@ -565,7 +565,20 @@ fixup_noreturn_call (gimple stmt) /* First split basic block if stmt is not last. */ if (stmt != gsi_stmt (gsi_last_bb (bb))) - split_block (bb, stmt); + { + if (stmt == gsi_stmt (gsi_last_nondebug_bb (bb))) + { + /* Don't split if there are only debug stmts + after stmt, that can result in -fcompare-debug + failures. Remove the debug stmts instead, + they should be all unreachable anyway. */ + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + for (gsi_next (&gsi); !gsi_end_p (gsi); ) + gsi_remove (&gsi, true); + } + else + split_block (bb, stmt); + } changed |= remove_fallthru_edge (bb->succs); diff --git a/gcc/tree-nrv.c b/gcc/tree-nrv.c index b443388a2a9..028ac9af7c2 100644 --- a/gcc/tree-nrv.c +++ b/gcc/tree-nrv.c @@ -187,8 +187,7 @@ tree_nrv (void) same type and alignment as the function's result. */ if (TREE_CODE (found) != VAR_DECL || TREE_THIS_VOLATILE (found) - || DECL_CONTEXT (found) != current_function_decl - || TREE_STATIC (found) + || !auto_var_in_fn_p (found, current_function_decl) || TREE_ADDRESSABLE (found) || DECL_ALIGN (found) > DECL_ALIGN (result) || !useless_type_conversion_p (result_type, diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c index ffef13d16ff..13f6c4a8e63 100644 --- a/gcc/tree-sra.c +++ b/gcc/tree-sra.c @@ -1092,6 +1092,11 @@ build_access_from_expr_1 (tree expr, gimple stmt, bool write) "component."); return NULL; } + if (TREE_THIS_VOLATILE (expr)) + { + disqualify_base_of_expr (expr, "part of a volatile reference."); + return NULL; + } switch (TREE_CODE (expr)) { diff --git a/gcc/tree-ssa-loop-niter.c b/gcc/tree-ssa-loop-niter.c index 7628363cc62..897b8f51895 100644 --- a/gcc/tree-ssa-loop-niter.c +++ b/gcc/tree-ssa-loop-niter.c @@ -1636,6 +1636,9 @@ expand_simple_operations (tree expr) case PLUS_EXPR: case MINUS_EXPR: + if (TYPE_OVERFLOW_TRAPS (TREE_TYPE (expr))) + return expr; + /* Fallthru. */ case POINTER_PLUS_EXPR: /* And increments and decrements by a constant are simple. */ e1 = gimple_assign_rhs2 (stmt); diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index 09e9b242c6b..1aa96a6be4b 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -312,9 +312,9 @@ stmt_local_def (gimple stmt) tree val; def_operand_p def_p; - if (gimple_has_side_effects (stmt) - || stmt_could_throw_p (stmt) - || gimple_vdef (stmt) != NULL_TREE) + if (gimple_vdef (stmt) != NULL_TREE + || gimple_has_side_effects (stmt) + || gimple_could_trap_p_1 (stmt, false, false)) return false; def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF); diff --git a/gcc/tree-vect-data-refs.c b/gcc/tree-vect-data-refs.c index 6622bd84df1..a1096fdfcc1 100644 --- a/gcc/tree-vect-data-refs.c +++ b/gcc/tree-vect-data-refs.c @@ -3841,6 +3841,9 @@ vect_get_new_vect_var (tree type, enum vect_var_kind var_kind, const char *name) is as follows: if LOOP=i_loop: &in (relative to i_loop) if LOOP=j_loop: &in+i*2B (relative to j_loop) + BYTE_OFFSET: Optional, defaulted to NULL. If supplied, it is added to the + initial address. Unlike OFFSET, which is number of elements to + be added, BYTE_OFFSET is measured in bytes. Output: 1. Return an SSA_NAME whose value is the address of the memory location of @@ -3854,7 +3857,8 @@ tree vect_create_addr_base_for_vector_ref (gimple stmt, gimple_seq *new_stmt_list, tree offset, - struct loop *loop) + struct loop *loop, + tree byte_offset) { stmt_vec_info stmt_info = vinfo_for_stmt (stmt); struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info); @@ -3907,6 +3911,12 @@ vect_create_addr_base_for_vector_ref (gimple stmt, base_offset = fold_build2 (PLUS_EXPR, sizetype, base_offset, offset); } + if (byte_offset) + { + byte_offset = fold_convert (sizetype, byte_offset); + base_offset = fold_build2 (PLUS_EXPR, sizetype, + base_offset, byte_offset); + } /* base + base_offset */ if (loop_vinfo) @@ -3964,6 +3974,10 @@ vect_create_addr_base_for_vector_ref (gimple stmt, 5. BSI: location where the new stmts are to be placed if there is no loop 6. ONLY_INIT: indicate if ap is to be updated in the loop, or remain pointing to the initial address. + 7. BYTE_OFFSET (optional, defaults to NULL): a byte offset to be added + to the initial address accessed by the data-ref in STMT. This is + similar to OFFSET, but OFFSET is counted in elements, while BYTE_OFFSET + in bytes. Output: 1. Declare a new ptr to vector_type, and have it point to the base of the @@ -3977,6 +3991,8 @@ vect_create_addr_base_for_vector_ref (gimple stmt, initial_address = &a[init]; if OFFSET is supplied: initial_address = &a[init + OFFSET]; + if BYTE_OFFSET is supplied: + initial_address = &a[init] + BYTE_OFFSET; Return the initial_address in INITIAL_ADDRESS. @@ -3994,7 +4010,7 @@ tree vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop, tree offset, tree *initial_address, gimple_stmt_iterator *gsi, gimple *ptr_incr, - bool only_init, bool *inv_p) + bool only_init, bool *inv_p, tree byte_offset) { const char *base_name; stmt_vec_info stmt_info = vinfo_for_stmt (stmt); @@ -4137,10 +4153,10 @@ vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop, /* (2) Calculate the initial address of the aggregate-pointer, and set the aggregate-pointer to point to it before the loop. */ - /* Create: (&(base[init_val+offset]) in the loop preheader. */ + /* Create: (&(base[init_val+offset]+byte_offset) in the loop preheader. */ new_temp = vect_create_addr_base_for_vector_ref (stmt, &new_stmt_list, - offset, loop); + offset, loop, byte_offset); if (new_stmt_list) { if (pe) diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index 0ab267f7d8e..59842291a99 100644 --- a/gcc/tree-vect-slp.c +++ b/gcc/tree-vect-slp.c @@ -1793,7 +1793,10 @@ vect_detect_hybrid_slp_stmts (slp_tree node) && (stmt_vinfo = vinfo_for_stmt (use_stmt)) && !STMT_SLP_TYPE (stmt_vinfo) && (STMT_VINFO_RELEVANT (stmt_vinfo) - || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_vinfo))) + || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_vinfo)) + || (STMT_VINFO_IN_PATTERN_P (stmt_vinfo) + && STMT_VINFO_RELATED_STMT (stmt_vinfo) + && !STMT_SLP_TYPE (vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_vinfo))))) && !(gimple_code (use_stmt) == GIMPLE_PHI && STMT_VINFO_DEF_TYPE (stmt_vinfo) == vect_reduction_def)) @@ -2392,13 +2395,21 @@ vect_get_constant_vectors (tree op, slp_tree slp_node, neutral_op = build_int_cst (TREE_TYPE (op), -1); break; - case MAX_EXPR: - case MIN_EXPR: - def_stmt = SSA_NAME_DEF_STMT (op); - loop = (gimple_bb (stmt))->loop_father; - neutral_op = PHI_ARG_DEF_FROM_EDGE (def_stmt, - loop_preheader_edge (loop)); - break; + /* For MIN/MAX we don't have an easy neutral operand but + the initial values can be used fine here. Only for + a reduction chain we have to force a neutral element. */ + case MAX_EXPR: + case MIN_EXPR: + if (!GROUP_FIRST_ELEMENT (stmt_vinfo)) + neutral_op = NULL; + else + { + def_stmt = SSA_NAME_DEF_STMT (op); + loop = (gimple_bb (stmt))->loop_father; + neutral_op = PHI_ARG_DEF_FROM_EDGE (def_stmt, + loop_preheader_edge (loop)); + } + break; default: neutral_op = NULL; diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c index 1a51d6d7b57..eadfdfa7f15 100644 --- a/gcc/tree-vect-stmts.c +++ b/gcc/tree-vect-stmts.c @@ -5600,6 +5600,7 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt, int i, j, group_size, group_gap; tree msq = NULL_TREE, lsq; tree offset = NULL_TREE; + tree byte_offset = NULL_TREE; tree realignment_token = NULL_TREE; gimple phi = NULL; vec<tree> dr_chain = vNULL; @@ -6261,7 +6262,8 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt, if (alignment_support_scheme == dr_explicit_realign_optimized) { phi = SSA_NAME_DEF_STMT (msq); - offset = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1); + byte_offset = size_binop (MINUS_EXPR, TYPE_SIZE_UNIT (vectype), + size_one_node); } } else @@ -6302,7 +6304,8 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt, dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, at_loop, offset, &dummy, gsi, &ptr_incr, - simd_lane_access_p, &inv_p); + simd_lane_access_p, &inv_p, + byte_offset); } else if (dataref_offset) dataref_offset = int_const_binop (PLUS_EXPR, dataref_offset, diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index 5567bd9522d..b32ec46333f 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -1061,7 +1061,8 @@ extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *, unsigned *); extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree, tree *, gimple_stmt_iterator *, - gimple *, bool, bool *); + gimple *, bool, bool *, + tree = NULL_TREE); extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree); extern tree vect_create_destination_var (tree, tree); extern bool vect_grouped_store_supported (tree, unsigned HOST_WIDE_INT); @@ -1078,7 +1079,8 @@ extern void vect_transform_grouped_load (gimple, vec<tree> , int, extern void vect_record_grouped_load_vectors (gimple, vec<tree> ); extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *); extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *, - tree, struct loop *); + tree, struct loop *, + tree = NULL_TREE); /* In tree-vect-loop.c. */ /* FORNOW: Used in tree-parloops.c. */ diff --git a/gcc/ubsan.c b/gcc/ubsan.c index ac40c85f56b..dc70099cccd 100644 --- a/gcc/ubsan.c +++ b/gcc/ubsan.c @@ -528,9 +528,9 @@ ubsan_instrument_unreachable (location_t loc) bool is_ubsan_builtin_p (tree t) { - gcc_checking_assert (TREE_CODE (t) == FUNCTION_DECL); - return strncmp (IDENTIFIER_POINTER (DECL_NAME (t)), - "__builtin___ubsan_", 18) == 0; + return TREE_CODE (t) == FUNCTION_DECL + && strncmp (IDENTIFIER_POINTER (DECL_NAME (t)), + "__builtin___ubsan_", 18) == 0; } /* Expand UBSAN_NULL internal call. */ diff --git a/gcc/varpool.c b/gcc/varpool.c index dc869e2512d..8cf68c62343 100644 --- a/gcc/varpool.c +++ b/gcc/varpool.c @@ -329,8 +329,16 @@ ctor_for_folding (tree decl) /* Variables declared 'const' without an initializer have zero as the initializer if they may not be - overridden at link or run time. */ - if (!DECL_INITIAL (real_decl) + overridden at link or run time. + + It is actually requirement for C++ compiler to optimize const variables + consistently. As a GNU extension, do not enfore this rule for user defined + weak variables, so we support interposition on: + static const int dummy = 0; + extern const int foo __attribute__((__weak__, __alias__("dummy"))); + */ + if ((!DECL_INITIAL (real_decl) + || (DECL_WEAK (decl) && !DECL_COMDAT (decl))) && (DECL_EXTERNAL (decl) || decl_replaceable_p (decl))) return error_mark_node; |