diff options
| author | Aldy Hernandez <aldyh@redhat.com> | 2011-11-08 03:20:30 +0000 |
|---|---|---|
| committer | Aldy Hernandez <aldyh@redhat.com> | 2011-11-08 03:20:30 +0000 |
| commit | 47180e1668b0766d1e473fed8d9385c0e765285d (patch) | |
| tree | 1eb48ad31d05a9ce117bedc17115de96dffa2f0b /libgcc/config/arm/t-elf | |
| parent | 80b9b1c40004ddf7dd74248b642d489384f37ace (diff) | |
| parent | eb6a1d75b768b663579adeb2a50828cf679b6f12 (diff) | |
* Merge from mainline rev 181122.transactional-memory
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/transactional-memory@181148 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libgcc/config/arm/t-elf')
| -rw-r--r-- | libgcc/config/arm/t-elf | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/libgcc/config/arm/t-elf b/libgcc/config/arm/t-elf new file mode 100644 index 00000000000..d9e8064e4de --- /dev/null +++ b/libgcc/config/arm/t-elf @@ -0,0 +1,18 @@ +# For most CPUs we have an assembly soft-float implementations. +# However this is not true for ARMv6M. Here we want to use the soft-fp C +# implementation. The soft-fp code is only build for ARMv6M. This pulls +# in the asm implementation for other CPUs. +LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func \ + _call_via_rX _interwork_call_via_rX \ + _lshrdi3 _ashrdi3 _ashldi3 \ + _arm_negdf2 _arm_addsubdf3 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ + _arm_fixdfsi _arm_fixunsdfsi \ + _arm_truncdfsf2 _arm_negsf2 _arm_addsubsf3 _arm_muldivsf3 \ + _arm_cmpsf2 _arm_unordsf2 _arm_fixsfsi _arm_fixunssfsi \ + _arm_floatdidf _arm_floatdisf _arm_floatundidf _arm_floatundisf \ + _clzsi2 _clzdi2 + +# Currently there is a bug somewhere in GCC's alias analysis +# or scheduling code that is breaking _fpmul_parts in fp-bit.c. +# Disabling function inlining is a workaround for this problem. +HOST_LIBGCC2_CFLAGS += -fno-inline |