diff options
55 files changed, 684 insertions, 86 deletions
diff --git a/gcc/ChangeLog.arm b/gcc/ChangeLog.arm new file mode 100644 index 00000000000..ba7bd6be633 --- /dev/null +++ b/gcc/ChangeLog.arm @@ -0,0 +1,170 @@ +2018-03-15 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/t-rmprofile: Add mapping from -mcpu=cortex-r52 to + -march=armv7. + +2018-03-15 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/t-rmprofile: Add mapping from -mcpu=cortex-m33+nodsp to + -march=armv8-m.main. + +2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-cpus.in (cortex-m33+nodsp): New CPU. + * config/arm/arm-cpu-cdata.h: Regenerate. + * config/arm/arm-cpu-data.h: Likewise. + * config/arm/arm-cpu.h: Likewise. + * config/arm/arm-tables.opt: Likewise. + * config/arm/arm-tune.md: Likewise. + * config/arm/arm.c (arm_file_start): Special case + * -mcpu=cortex-m33+nodsp to emit .arch armv8-m.main instead. + * doc/invoke.texi: Document cortex-m33+nodsp as a valid value for -mcpu + and -mtune. + +2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/t-rmprofile: Map Armv8-R and Armv8-R with CRC extension to + Armv7 multilibs. + +2017-11-23 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Cherry-pick from GCC 7 + 2017-11-09 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm.c (output_return_instruction): Add comments to + indicate requirement for cmse_nonsecure_entry return to account + for the size of clearing instruction output here. + (thumb_exit): Likewise. + * config/arm/thumb2.md (thumb2_cmse_entry_return): Fix length for + return in hardfloat mode. + +2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-cpus.in (cortex-r52): Add new entry. + (armv8-r): Set ARM Cortex-R52 as default CPU. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-tune.md: Regenerate. + * config/arm/arm-cpu-cdata.h: Regenerate. + * config/arm/arm-cpu-data.h: Regenerate. + * config/arm/arm-cpu.h: Regenerate. + * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM + Cortex-R52. + * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp + extension for -mcpu=cortex-r52. + +2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator. + (ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32. + * config/arm/arm-cpus.in (fp-armv8): Define it as FP_ARMv8 only. + * config/arm/arm-cpu-data.h: Regenerate. + * config/arm/arm.h (TARGET_FPU_ARMV8): Delete. + (TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than + TARGET_FPU_ARMV8. + * config/arm/arm.c (arm_rtx_costs_internal): Replace checks against + TARGET_FPU_ARMV8 by checks against TARGET_VFP5. + * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define + first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather + than TARGET_FPU_ARMV8. + * config/arm/arm-c.c (arm_cpu_builtins): Likewise for + __ARM_FEATURE_NUMERIC_MAXMIN macro definition. + * config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than + TARGET_FPU_ARMV8. + * config/arm/neon.md (neon_vrint): Likewise. + (neon_vcvt): Likewise. + (neon_<fmaxmin_op><mode>): Likewise. + (<fmaxmin><mode>3): Likewise. + * config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise. + * config/arm/predicates.md (arm_cond_move_operator): Check against + TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing. + +2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-07-06 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-cpus.in (armv8-r): Add new entry. + (armv8-r+crc): Likewise. + * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-cpu-cdata.h: Regenerate. + * config/arm/arm-cpu-data.h: Regenerate. + * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R + enumerator. + * doc/invoke.texi: Mention -march=armv8-r and its crc extension. + +2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-07-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM + Cortex-R7 and Cortex-R8 processors. + +2017-07-10 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/t-rmprofile: Remove multilibs for fpv5-sp-d16 and map it to + fpv4-sp-d16. + +2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-06-20 Prakhar Bahuguna <prakhar.bahuguna@arm.com> + + * config/arm/arm-c.c (arm_cpu_builtins): New block to define + __ARM_FEATURE_COPROC according to support. + +2017-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-05-03 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/iterators.md (CCSI): New mode iterator. + (arch): New mode attribute. + * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Rename into ... + (atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): This and ... + (atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): This. Use CCSI + code iterator for success result mode. + * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use + the corresponding new insn generators. + +2017-05-31 Prakhar Bahuguna <prakhar.bahuguna@arm.com> + + Backport from mainline + 2017-05-04 Prakhar Bahuguna <prakhar.bahuguna@arm.com> + Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com> + + * config/arm/arm.md (movsi): Add TARGET_32BIT in addition to the + TARGET_HAVE_MOVT conditional. + (movt splitter): Likewise. + * config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2 + to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check. + (const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else + block for Thumb-1 with MOVT. + (thumb2_legitimate_address_p): Move code block ... + (can_avoid_literal_pool_for_label_p): ... into this new function. + (thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and + literal pool. + (thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT + * doc/invoke.texi (-mpure-code): Change "ARMv7-M targets" for + "M-profile targets with the MOVT instruction". + +2017-05-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-05-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * configure.ac (--enable-mingw-wildcard): Add new configurable feature. + * configure: Regenerate. + * config.in: Regenerate. + * config/i386/driver-mingw32.c: new file. + * config/i386/x-mingw32: Add rule to build driver-mingw32.o. + * config.host: Link driver-mingw32.o on MinGW host. + * doc/install.texi: Document new --enable-mingw-wildcard configure + option. diff --git a/gcc/config.host b/gcc/config.host index 6b28f3033ef..5e2db5327e3 100644 --- a/gcc/config.host +++ b/gcc/config.host @@ -239,6 +239,7 @@ case ${host} in host_xmake_file="${host_xmake_file} i386/x-mingw32" host_exeext=.exe out_host_hook_obj=host-mingw32.o + host_extra_gcc_objs="${host_extra_gcc_objs} driver-mingw32.o" host_lto_plugin_soname=liblto_plugin-0.dll ;; x86_64-*-mingw*) @@ -247,6 +248,7 @@ case ${host} in host_xmake_file="${host_xmake_file} i386/x-mingw32" host_exeext=.exe out_host_hook_obj=host-mingw32.o + host_extra_gcc_objs="${host_extra_gcc_objs} driver-mingw32.o" host_lto_plugin_soname=liblto_plugin-0.dll ;; i[34567]86-*-darwin* | x86_64-*-darwin*) diff --git a/gcc/config.in b/gcc/config.in index eca3fd810fb..e3e66ffb7bc 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -2019,6 +2019,12 @@ #endif +/* Value to set mingw's _dowildcard to. */ +#ifndef USED_FOR_TARGET +#undef MINGW_DOWILDCARD +#endif + + /* Define if host mkdir takes a single argument. */ #ifndef USED_FOR_TARGET #undef MKDIR_TAKES_ONE_ARG diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index d3b67184362..1c9bda62f49 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -3100,7 +3100,7 @@ arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in) NULL_TREE is returned if no such builtin is available. */ #undef ARM_CHECK_BUILTIN_MODE #define ARM_CHECK_BUILTIN_MODE(C) \ - (TARGET_FPU_ARMV8 \ + (TARGET_VFP5 \ && flag_unsafe_math_optimizations \ && ARM_CHECK_BUILTIN_MODE_1 (C)) diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 3abe7d1f1f5..9178937b6d9 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -96,7 +96,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) || TARGET_ARM_ARCH_ISA_THUMB >=2)); def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN", - TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8); + TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_VFP5); def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD); @@ -200,6 +200,22 @@ arm_cpu_builtins (struct cpp_reader* pfile) def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV); def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified); + + if (TARGET_32BIT && arm_arch4 && !(arm_arch8 && arm_arch_notm)) + { + int coproc_level = 0x1; + + if (arm_arch5) + coproc_level |= 0x2; + if (arm_arch5e) + coproc_level |= 0x4; + if (arm_arch6) + coproc_level |= 0x8; + + builtin_define_with_int_value ("__ARM_FEATURE_COPROC", coproc_level); + } + else + cpp_undef (pfile, "__ARM_FEATURE_COPROC"); } void diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index b00d83302f6..f5e34c830ca 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -789,6 +789,20 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { + "cortex-m33+nodsp", + { + ISA_ARMv8m_main, + isa_nobit + }, + }, + { + "cortex-r52", + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + }, + { "armv2", { ISA_ARMv2,isa_bit_mode26, @@ -1027,6 +1041,20 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { + "armv8-r", + { + ISA_ARMv8r, + isa_nobit + }, + }, + { + "armv8-r+crc", + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + }, + { "iwmmxt", { ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 78421adb9e5..30902ecabc6 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -1220,6 +1220,28 @@ static const struct processors all_cores[] = }, &arm_v7m_tune }, + { + "cortex-m33+nodsp", + TARGET_CPU_cortexm33nodsp, + (TF_LDSCHED), + "8M_MAIN", BASE_ARCH_8M_MAIN, + { + ISA_ARMv8m_main, + isa_nobit + }, + &arm_v7m_tune + }, + { + "cortex-r52", + TARGET_CPU_cortexr52, + (TF_LDSCHED), + "8R", BASE_ARCH_8R, + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + &arm_cortex_tune + }, {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL} }; @@ -1566,6 +1588,26 @@ static const struct processors all_architectures[] = NULL }, { + "armv8-r", TARGET_CPU_cortexr52, + (TF_CO_PROC), + "8R", BASE_ARCH_8R, + { + ISA_ARMv8r, + isa_nobit + }, + NULL + }, + { + "armv8-r+crc", TARGET_CPU_cortexr4, + (TF_CO_PROC), + "8R", BASE_ARCH_8R, + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + NULL + }, + { "iwmmxt", TARGET_CPU_iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), "5TE", BASE_ARCH_5TE, @@ -1712,7 +1754,7 @@ const struct arm_fpu_desc all_fpus[] = { "fp-armv8", { - ISA_FP_ARMv8,ISA_FP_D32, + ISA_FP_ARMv8, isa_nobit } }, diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h index cc0cb0017eb..22566495fdf 100644 --- a/gcc/config/arm/arm-cpu.h +++ b/gcc/config/arm/arm-cpu.h @@ -130,6 +130,8 @@ enum processor_type TARGET_CPU_cortexa73cortexa53, TARGET_CPU_cortexm23, TARGET_CPU_cortexm33, + TARGET_CPU_cortexm33nodsp, + TARGET_CPU_cortexr52, TARGET_CPU_arm_none }; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 1100f3a5411..7368a067db9 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -287,6 +287,20 @@ begin arch armv8-m.main+dsp isa ARMv8m_main bit_ARMv7em end arch armv8-m.main+dsp +begin arch armv8-r + tune for cortex-r52 + tune flags CO_PROC + base 8R + isa ARMv8r +end arch armv8-r + +begin arch armv8-r+crc + tune for cortex-r4 + tune flags CO_PROC + base 8R + isa ARMv8r bit_crc32 +end arch armv8-r+crc + begin arch iwmmxt tune for iwmmxt tune flags LDSCHED STRONG XSCALE @@ -1076,6 +1090,21 @@ begin cpu cortex-m33 costs v7m end cpu cortex-m33 +begin cpu cortex-m33+nodsp + cname cortexm33nodsp + tune flags LDSCHED + architecture armv8-m.main + costs v7m +end cpu cortex-m33+nodsp + +# V8 R-profile implementations. +begin cpu cortex-r52 + cname cortexr52 + tune flags LDSCHED + architecture armv8-r+crc + costs cortex +end cpu cortex-r52 + # FPU entries # format: # begin fpu <name> @@ -1151,7 +1180,7 @@ begin fpu fpv5-d16 end fpu fpv5-d16 begin fpu fp-armv8 - isa FP_ARMv8 FP_D32 + isa FP_ARMv8 end fpu fp-armv8 begin fpu neon-fp-armv8 diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 7d1e23be0a2..59d893084b2 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -59,7 +59,6 @@ enum isa_feature isa_bit_VFPv4, /* Vector floating point v4. */ isa_bit_FPv5, /* Floating point v5. */ isa_bit_lpae, /* ARMv7-A LPAE. */ - isa_bit_FP_ARMv8, /* ARMv8 floating-point extension. */ isa_bit_neon, /* Advanced SIMD instructions. */ isa_bit_fp16conv, /* Conversions to/from fp16 (VFPv3 extension). */ isa_bit_fp_dbl, /* Double precision operations supported. */ @@ -126,11 +125,12 @@ enum isa_feature #define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse +#define ISA_ARMv8r ISA_ARMv8a /* List of all FPU bits to strip out if -mfpu is used to override the default. isa_bit_fp16 is deliberately missing from this list. */ #define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, \ - isa_bit_FPv5, isa_bit_FP_ARMv8, isa_bit_neon, isa_bit_fp16conv, \ + isa_bit_FPv5, isa_bit_neon, isa_bit_fp16conv, \ isa_bit_fp_dbl, isa_bit_fp_d32, isa_bit_crypto /* Useful combinations. */ @@ -138,10 +138,10 @@ enum isa_feature #define ISA_VFPv3 ISA_VFPv2, isa_bit_VFPv3 #define ISA_VFPv4 ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv #define ISA_FPv5 ISA_VFPv4, isa_bit_FPv5 -#define ISA_FP_ARMv8 ISA_FPv5, isa_bit_FP_ARMv8 #define ISA_FP_DBL isa_bit_fp_dbl #define ISA_FP_D32 ISA_FP_DBL, isa_bit_fp_d32 +#define ISA_FP_ARMv8 ISA_FPv5, ISA_FP_D32 #define ISA_NEON ISA_FP_D32, isa_bit_neon #define ISA_CRYPTO ISA_NEON, isa_bit_crypto diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index cb45e097c90..a46bc3c7f8b 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -348,6 +348,12 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) EnumValue Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) +EnumValue +Enum(processor_type) String(cortex-m33+nodsp) Value( TARGET_CPU_cortexm33nodsp) + +EnumValue +Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): @@ -455,10 +461,16 @@ EnumValue Enum(arm_arch) String(armv8-m.main+dsp) Value(33) EnumValue -Enum(arm_arch) String(iwmmxt) Value(34) +Enum(arm_arch) String(armv8-r) Value(34) + +EnumValue +Enum(arm_arch) String(armv8-r+crc) Value(35) + +EnumValue +Enum(arm_arch) String(iwmmxt) Value(36) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(35) +Enum(arm_arch) String(iwmmxt2) Value(37) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 6252d42d4d8..542b7972d21 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -56,5 +56,6 @@ cortexa53,cortexa57,cortexa72, cortexa73,exynosm1,xgene1, cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, - cortexa73cortexa53,cortexm23,cortexm33" + cortexa73cortexa53,cortexm23,cortexm33, + cortexm33nodsp,cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 886bcfa98b9..74b9d07a195 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2811,16 +2811,16 @@ arm_option_check_internal (struct gcc_options *opts) flag_pic = 0; } - /* We only support -mslow-flash-data on armv7-m targets. */ - if (target_slow_flash_data - && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em) - || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON))) - error ("-mslow-flash-data only supports non-pic code on armv7-m targets"); - - /* We only support pure-code on Thumb-2 M-profile targets. */ - if (target_pure_code - && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON)) - error ("-mpure-code only supports non-pic code on armv7-m targets"); + /* We only support -mpure-code and -mslow-flash-data on M-profile targets + with MOVT. */ + if ((target_pure_code || target_slow_flash_data) + && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON)) + { + const char *flag = (target_pure_code ? "-mpure-code" : + "-mslow-flash-data"); + error ("%s only supports non-pic code on M-profile targets with the " + "MOVT instruction", flag); + } } @@ -4055,7 +4055,7 @@ const_ok_for_arm (HOST_WIDE_INT i) || (i & ~0xfc000003) == 0)) return TRUE; } - else + else if (TARGET_THUMB2) { HOST_WIDE_INT v; @@ -4071,6 +4071,14 @@ const_ok_for_arm (HOST_WIDE_INT i) if (i == v) return TRUE; } + else if (TARGET_HAVE_MOVT) + { + /* Thumb-1 Targets with MOVT. */ + if (i > 0xffff) + return FALSE; + else + return TRUE; + } return FALSE; } @@ -7714,6 +7722,32 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer, return 0; } +/* Return true if we can avoid creating a constant pool entry for x. */ +static bool +can_avoid_literal_pool_for_label_p (rtx x) +{ + /* Normally we can assign constant values to target registers without + the help of constant pool. But there are cases we have to use constant + pool like: + 1) assign a label to register. + 2) sign-extend a 8bit value to 32bit and then assign to register. + + Constant pool access in format: + (set (reg r0) (mem (symbol_ref (".LC0")))) + will cause the use of literal pool (later in function arm_reorg). + So here we mark such format as an invalid format, then the compiler + will adjust it into: + (set (reg r0) (symbol_ref (".LC0"))) + (set (reg r0) (mem (reg r0))). + No extra register is required, and (mem (reg r0)) won't cause the use + of literal pools. */ + if (arm_disable_literal_pool && GET_CODE (x) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (x)) + return 1; + return 0; +} + + /* Return nonzero if X is a valid Thumb-2 address operand. */ static int thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p) @@ -7777,23 +7811,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p) && thumb2_legitimate_index_p (mode, xop0, strict_p))); } - /* Normally we can assign constant values to target registers without - the help of constant pool. But there are cases we have to use constant - pool like: - 1) assign a label to register. - 2) sign-extend a 8bit value to 32bit and then assign to register. - - Constant pool access in format: - (set (reg r0) (mem (symbol_ref (".LC0")))) - will cause the use of literal pool (later in function arm_reorg). - So here we mark such format as an invalid format, then the compiler - will adjust it into: - (set (reg r0) (symbol_ref (".LC0"))) - (set (reg r0) (mem (reg r0))). - No extra register is required, and (mem (reg r0)) won't cause the use - of literal pools. */ - else if (arm_disable_literal_pool && code == SYMBOL_REF - && CONSTANT_POOL_ADDRESS_P (x)) + else if (can_avoid_literal_pool_for_label_p (x)) return 0; else if (GET_MODE_CLASS (mode) != MODE_FLOAT @@ -8072,6 +8090,9 @@ thumb1_index_register_rtx_p (rtx x, int strict_p) int thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p) { + if (TARGET_HAVE_MOVT && can_avoid_literal_pool_for_label_p (x)) + return 0; + /* ??? Not clear if this is right. Experiment. */ if (GET_MODE_SIZE (mode) < 4 && !(reload_in_progress || reload_completed) @@ -8693,6 +8714,7 @@ thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) return (CONST_INT_P (x) || CONST_DOUBLE_P (x) || CONSTANT_ADDRESS_P (x) + || (TARGET_HAVE_MOVT && GET_CODE (x) == SYMBOL_REF) || flag_pic); } @@ -10684,7 +10706,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, { if (speed_p) *cost += extra_cost->fp[mode == DFmode].widen; - if (!TARGET_FPU_ARMV8 + if (!TARGET_VFP5 && GET_MODE (XEXP (x, 0)) == HFmode) { /* Pre v8, widening HF->DF is a two-step process, first @@ -10778,7 +10800,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, return true; } else if (GET_MODE_CLASS (mode) == MODE_FLOAT - && TARGET_FPU_ARMV8) + && TARGET_VFP5) { if (speed_p) *cost += extra_cost->fp[mode == DFmode].roundint; @@ -26146,6 +26168,8 @@ arm_file_start (void) else if (strncmp (arm_active_target.core_name, "generic", 7) == 0) asm_fprintf (asm_out_file, "\t.arch %s\n", arm_active_target.core_name + 8); + else if (strcmp (arm_active_target.core_name, "cortex-m33+nodsp") == 0) + asm_fprintf (asm_out_file, "\t.arch armv8-m.main\n"); else { const char* truncated_name @@ -28266,17 +28290,32 @@ arm_expand_compare_and_swap (rtx operands[]) gcc_unreachable (); } - switch (mode) + if (TARGET_THUMB1) { - case QImode: gen = gen_atomic_compare_and_swapqi_1; break; - case HImode: gen = gen_atomic_compare_and_swaphi_1; break; - case SImode: gen = gen_atomic_compare_and_swapsi_1; break; - case DImode: gen = gen_atomic_compare_and_swapdi_1; break; - default: - gcc_unreachable (); + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swapt1qi_1; break; + case HImode: gen = gen_atomic_compare_and_swapt1hi_1; break; + case SImode: gen = gen_atomic_compare_and_swapt1si_1; break; + case DImode: gen = gen_atomic_compare_and_swapt1di_1; break; + default: + gcc_unreachable (); + } + } + else + { + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swap32qi_1; break; + case HImode: gen = gen_atomic_compare_and_swap32hi_1; break; + case SImode: gen = gen_atomic_compare_and_swap32si_1; break; + case DImode: gen = gen_atomic_compare_and_swap32di_1; break; + default: + gcc_unreachable (); + } } - bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CCmode, CC_REGNUM); + bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CC_Zmode, CC_REGNUM); emit_insn (gen (bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f)); if (mode == QImode || mode == HImode) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 68a6fa56c7c..b98ec1c4490 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -191,10 +191,6 @@ extern tree arm_fp16_type_node; /* FPU supports fused-multiply-add operations. */ #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4)) -/* FPU is ARMv8 compatible. */ -#define TARGET_FPU_ARMV8 \ - (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8)) - /* FPU supports Crypto extensions. */ #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) @@ -211,7 +207,7 @@ extern tree arm_fp16_type_node; /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */ #define TARGET_VFP_FP16INST \ - (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst) + (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) @@ -379,7 +375,8 @@ enum base_architecture BASE_ARCH_7EM = 7, BASE_ARCH_8A = 8, BASE_ARCH_8M_BASE = 8, - BASE_ARCH_8M_MAIN = 8 + BASE_ARCH_8M_MAIN = 8, + BASE_ARCH_8R = 8 }; /* The major revision number of the ARM Architecture implemented by the target. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ad5f3874bc7..05251cfd598 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5966,7 +5966,7 @@ { rtx base, offset, tmp; - if (TARGET_32BIT) + if (TARGET_32BIT || TARGET_HAVE_MOVT) { /* Everything except mem = const or mem = mem can be done easily. */ if (MEM_P (operands[0])) @@ -5990,7 +5990,7 @@ } } } - else /* TARGET_THUMB1... */ + else /* Target doesn't have MOVT... */ { if (can_create_pseudo_p ()) { @@ -6090,7 +6090,7 @@ (define_split [(set (match_operand:SI 0 "arm_general_register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] - "TARGET_32BIT + "(TARGET_32BIT || TARGET_HAVE_MOVT) && (!(const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1]))))" [(clobber (const_int 0))] @@ -7876,7 +7876,7 @@ "<F_constraint>") (match_operand:SDF 4 "s_register_operand" "<F_constraint>")))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" + "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" "* { enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]); diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index b034f13fda6..00f8128e691 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -54,6 +54,9 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xd09", "armv8-a+crc", "cortex-a73"}, {"0xc14", "armv7-r", "cortex-r4"}, {"0xc15", "armv7-r", "cortex-r5"}, + {"0xc17", "armv7-r", "cortex-r7"}, + {"0xc18", "armv7-r", "cortex-r8"}, + {"0xd13", "armv8-r+crc", "cortex-r52"}, {"0xc20", "armv6-m", "cortex-m0"}, {"0xc21", "armv6-m", "cortex-m1"}, {"0xc23", "armv7-m", "cortex-m3"}, diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index dbf7c4ec019..26dbef98439 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -45,6 +45,9 @@ ;; A list of the 32bit and 64bit integer modes (define_mode_iterator SIDI [SI DI]) +;; A list of atomic compare and swap success return modes +(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) + ;; A list of modes which the VFP unit can handle (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) @@ -415,6 +418,10 @@ ;; Mode attributes ;;---------------------------------------------------------------------------- +;; Determine name of atomic compare and swap from success result mode. This +;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. +(define_mode_attr arch [(CC_Z "32") (SI "t1")]) + ;; Determine element size suffix from vector mode. (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 5ddef4956f5..b0844265839 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -714,7 +714,7 @@ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")] NEON_VRINT))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "vrint<nvrint_variant>%?.f32\\t%<V_reg>0, %<V_reg>1" [(set_attr "type" "neon_fp_round_<V_elem_ch><q>")] ) @@ -724,7 +724,7 @@ (FIXUORS:<V_cmp_result> (unspec:VCVTF [(match_operand:VCVTF 1 "register_operand" "w")] NEON_VCVT)))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "vcvt<nvrint_variant>.<su>32.f32\\t%<V_reg>0, %<V_reg>1" [(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>") (set_attr "predicable" "no")] @@ -2853,7 +2853,7 @@ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") (match_operand:VCVTF 2 "s_register_operand" "w")] VMAXMINFNM))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_minmax_s<q>")] ) @@ -2864,7 +2864,7 @@ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") (match_operand:VCVTF 2 "s_register_operand" "w")] VMAXMINFNM))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_minmax_s<q>")] ) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index afb5d6339a8..3e25cd16b29 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -350,9 +350,9 @@ (define_special_predicate "arm_cond_move_operator" (if_then_else (match_test "arm_restrict_it") - (and (match_test "TARGET_FPU_ARMV8") - (match_operand 0 "arm_vsel_comparison_operator")) - (match_operand 0 "expandable_comparison_operator"))) + (and (match_test "TARGET_VFP5") + (match_operand 0 "arm_vsel_comparison_operator")) + (match_operand 0 "expandable_comparison_operator"))) (define_special_predicate "noov_comparison_operator" (match_code "lt,ge,eq,ne")) diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 1f91b7364d5..b4b4f2e6815 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -191,9 +191,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap<mode>_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (zero_extend:SI (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory @@ -223,9 +223,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap<mode>_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2) diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index 625ccbca193..055a06ee8f1 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -74,8 +74,6 @@ MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=soft MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=hard MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=softfp MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=hard # ARMv8-M Mainline MULTILIB_REQUIRED += mthumb/march=armv8-m.main @@ -104,11 +102,13 @@ MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m4 MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m7 MULTILIB_MATCHES += march?armv8-m.base=mcpu?cortex-m23 MULTILIB_MATCHES += march?armv8-m.main=mcpu?cortex-m33 +MULTILIB_MATCHES += march?armv8-m.main=mcpu?cortex-m33+nodsp MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f MULTILIB_MATCHES += march?armv7=mcpu?cortex-r5 MULTILIB_MATCHES += march?armv7=mcpu?cortex-r7 MULTILIB_MATCHES += march?armv7=mcpu?cortex-r8 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-r52 MULTILIB_MATCHES += march?armv7=mcpu?marvell-pj4 MULTILIB_MATCHES += march?armv7=mcpu?generic-armv7-a MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 @@ -137,6 +137,8 @@ MULTILIB_MATCHES += march?armv7=mcpu?xgene1 MULTILIB_MATCHES += march?armv6s-m=march?armv6-m MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp MULTILIB_MATCHES += march?armv7=march?armv7-r +MULTILIB_MATCHES += march?armv7=march?armv8-r +MULTILIB_MATCHES += march?armv7=march?armv8-r+crc ifeq (,$(HAS_APROFILE)) MULTILIB_MATCHES += march?armv7=march?armv7-a MULTILIB_MATCHES += march?armv7=march?armv7ve @@ -164,8 +166,8 @@ MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?crypto-neon-fp-armv8 endif -# We map all requests for ARMv7-R or ARMv7-A in ARM mode to Thumb mode and -# any FPU to VFPv3-d16 if possible. +# We map all requests for ARMv7-R, ARMv7-A and ARMv8-R in ARM mode to Thumb +# mode and any FPU to VFPv3-d16 if possible. MULTILIB_REUSE += mthumb/march.armv7=march.armv7 MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard @@ -173,3 +175,7 @@ MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=ma MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.fpv5-d16/mfloat-abi.hard MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.hard + +# Map ARMv7E-M FPV5-SP-D16 to FPV4-SP-D16 +MULTILIB_REUSE += mthumb/march.armv7e-m/mfpu.fpv4-sp-d16/mfloat-abi.softfp=mthumb/march.armv7e-m/mfpu.fpv5-sp-d16/mfloat-abi.softfp +MULTILIB_REUSE += mthumb/march.armv7e-m/mfpu.fpv4-sp-d16/mfloat-abi.hard=mthumb/march.armv7e-m/mfpu.fpv5-sp-d16/mfloat-abi.hard diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 9f06c3da952..1de58b847aa 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -2000,7 +2000,7 @@ (FIXUORS:SI (unspec:SDF [(match_operand:SDF 1 "register_operand" "<F_constraint>")] VCVT)))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" + "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1" [(set_attr "predicable" "no") (set_attr "conds" "unconditional") diff --git a/gcc/config/i386/driver-mingw32.c b/gcc/config/i386/driver-mingw32.c new file mode 100644 index 00000000000..b70363ad26a --- /dev/null +++ b/gcc/config/i386/driver-mingw32.c @@ -0,0 +1,26 @@ +/* Host OS specific configuration for the gcc driver. + Copyright (C) 2017 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" + +/* When defined, force the use (if non null) or not (otherwise) of CLI + globbing. */ +#ifdef MINGW_DOWILDCARD +int _dowildcard = MINGW_DOWILDCARD; +#endif diff --git a/gcc/config/i386/x-mingw32 b/gcc/config/i386/x-mingw32 index 6a2d5a50694..85f2793e5e9 100644 --- a/gcc/config/i386/x-mingw32 +++ b/gcc/config/i386/x-mingw32 @@ -29,3 +29,6 @@ host-mingw32.o : $(srcdir)/config/i386/host-mingw32.c $(CONFIG_H) $(SYSTEM_H) \ coretypes.h hosthooks.h hosthooks-def.h toplev.h $(DIAGNOSTIC_H) $(HOOKS_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/i386/host-mingw32.c + +driver-mingw32.o : $(srcdir)/config/i386/driver-mingw32.c $(CONFIG_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< diff --git a/gcc/configure b/gcc/configure index 0fdf2b2f44c..fabebba5078 100755 --- a/gcc/configure +++ b/gcc/configure @@ -921,6 +921,7 @@ with_libiconv_prefix enable_sjlj_exceptions with_gcc_major_version_only enable_secureplt +enable_mingw_wildcard enable_leading_mingw64_underscores enable_cld enable_frame_pointer @@ -1633,6 +1634,8 @@ Optional Features: --enable-sjlj-exceptions arrange to use setjmp/longjmp exception handling --enable-secureplt enable -msecure-plt by default for PowerPC + --enable-mingw-wildcard Set whether to expand wildcard on command-line. + Default to platform configuration --enable-leading-mingw64-underscores enable leading underscores on 64 bit mingw targets --enable-cld enable -mcld by default for 32bit x86 @@ -11963,6 +11966,21 @@ if test "${enable_secureplt+set}" = set; then : fi +# Check whether --enable-mingw-wildcard was given. +if test "${enable_mingw_wildcard+set}" = set; then : + enableval=$enable_mingw_wildcard; +else + enable_mingw_wildcard=platform +fi + +if test x"$enable_mingw_wildcard" != xplatform ; then : + +cat >>confdefs.h <<_ACEOF +#define MINGW_DOWILDCARD $(test x"$enable_mingw_wildcard" = xno; echo $?) +_ACEOF + +fi + # Check whether --enable-leading-mingw64-underscores was given. if test "${enable_leading_mingw64_underscores+set}" = set; then : enableval=$enable_leading_mingw64_underscores; @@ -18433,7 +18451,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 18436 "configure" +#line 18454 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -18539,7 +18557,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 18542 "configure" +#line 18560 "configure" #include "confdefs.h" #if HAVE_DLFCN_H diff --git a/gcc/configure.ac b/gcc/configure.ac index eec1b0efaca..50749c3a5a1 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -1811,6 +1811,16 @@ AC_ARG_ENABLE(secureplt, [enable -msecure-plt by default for PowerPC])], [], []) +AC_ARG_ENABLE(mingw-wildcard, +[AS_HELP_STRING([--enable-mingw-wildcard], + [Set whether to expand wildcard on command-line. + Default to platform configuration])], +[],[enable_mingw_wildcard=platform]) +AS_IF([test x"$enable_mingw_wildcard" != xplatform ], + [AC_DEFINE_UNQUOTED(MINGW_DOWILDCARD, + $(test x"$enable_mingw_wildcard" = xno; echo $?), + [Value to set mingw's _dowildcard to.])]) + AC_ARG_ENABLE(leading-mingw64-underscores, AS_HELP_STRING([--enable-leading-mingw64-underscores], [enable leading underscores on 64 bit mingw targets]), diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 639298c85d4..109be3bd7a5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15069,7 +15069,8 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m}, @samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a}, @samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main}, -@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}. +@samp{armv8-m.main+dsp}, @samp{armv8-r}, @samp{armv8-r+crc}, @samp{iwmmxt}, +@samp{iwmmxt2}. Architecture revisions older than @samp{armv4t} are deprecated. @@ -15131,7 +15132,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m33}, +@samp{cortex-r52}, +@samp{cortex-m33},@samp{cortex-m33+nodsp} @samp{cortex-m23}, @samp{cortex-m7}, @samp{cortex-m4}, @@ -15449,7 +15451,8 @@ by default. Do not allow constant data to be placed in code sections. Additionally, when compiling for ELF object format give all text sections the ELF processor-specific section attribute @code{SHF_ARM_PURECODE}. This option -is only available when generating non-pic code for ARMv7-M targets. +is only available when generating non-pic code for M-profile targets with the +MOVT instruction. @item -mcmse @opindex mcmse diff --git a/gcc/lto/ChangeLog.arm b/gcc/lto/ChangeLog.arm new file mode 100644 index 00000000000..92947e4a1ce --- /dev/null +++ b/gcc/lto/ChangeLog.arm @@ -0,0 +1,11 @@ +2017-11-28 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-06-15 Jan Hubicka <hubicka@ucw.cz> + Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR lto/69866 + * lto-partition.c (add_symbol_to_partition_1): Allow alias of external + symbol to be added. + * lto-symtab.c (lto_symtab_merge_symbols): Drop useless definitions + that resolved externally. diff --git a/gcc/lto/lto-partition.c b/gcc/lto/lto-partition.c index a624dfa8847..f291960c050 100644 --- a/gcc/lto/lto-partition.c +++ b/gcc/lto/lto-partition.c @@ -132,7 +132,7 @@ add_symbol_to_partition_1 (ltrans_partition part, symtab_node *node) /* Be sure that we never try to duplicate partitioned symbol or add external symbol. */ - gcc_assert (c != SYMBOL_EXTERNAL + gcc_assert ((c != SYMBOL_EXTERNAL || node->alias) && (c == SYMBOL_DUPLICATE || !symbol_partitioned_p (node))); part->symbols++; diff --git a/gcc/lto/lto-symtab.c b/gcc/lto/lto-symtab.c index 65eb2b58c72..01cc0b7602e 100644 --- a/gcc/lto/lto-symtab.c +++ b/gcc/lto/lto-symtab.c @@ -998,6 +998,42 @@ lto_symtab_merge_symbols (void) if (tgt) node->resolve_alias (tgt, true); } + /* If the symbol was preempted outside IR, see if we want to get rid + of the definition. */ + if (node->analyzed + && !DECL_EXTERNAL (node->decl) + && (node->resolution == LDPR_PREEMPTED_REG + || node->resolution == LDPR_RESOLVED_IR + || node->resolution == LDPR_RESOLVED_EXEC + || node->resolution == LDPR_RESOLVED_DYN)) + { + DECL_EXTERNAL (node->decl) = 1; + /* If alias to local symbol was preempted by external definition, + we know it is not pointing to the local symbol. Remove it. */ + if (node->alias + && !node->weakref + && !node->transparent_alias + && node->get_alias_target ()->binds_to_current_def_p ()) + { + node->alias = false; + node->remove_all_references (); + node->definition = false; + node->analyzed = false; + node->cpp_implicit_alias = false; + } + else if (!node->alias + && node->definition + && node->get_availability () <= AVAIL_INTERPOSABLE) + { + if ((cnode = dyn_cast <cgraph_node *> (node)) != NULL) + cnode->reset (); + else + { + node->analyzed = node->definition = false; + node->remove_all_references (); + } + } + } if (!(cnode = dyn_cast <cgraph_node *> (node)) || !cnode->clone_of diff --git a/gcc/testsuite/ChangeLog.arm b/gcc/testsuite/ChangeLog.arm new file mode 100644 index 00000000000..2ccc7273940 --- /dev/null +++ b/gcc/testsuite/ChangeLog.arm @@ -0,0 +1,50 @@ +2017-11-28 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-06-15 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR lto/69866 + * gcc.dg/lto/pr69866_0.c: New test. + * gcc.dg/lto/pr69866_1.c: Likewise. + +2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-07-06 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * lib/target-supports.exp: Generate + check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r + and check_effective_target_arm_arch_v8r_multilib. + +2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-06-20 Prakhar Bahuguna <prakhar.bahuguna@arm.com> + + * gcc.target/arm/acle/cdp.c: Add feature macro bitmap test. + * gcc.target/arm/acle/cdp2.c: Likewise. + * gcc.target/arm/acle/ldc.c: Likewise. + * gcc.target/arm/acle/ldc2.c: Likewise. + * gcc.target/arm/acle/ldc2l.c: Likewise. + * gcc.target/arm/acle/ldcl.c: Likewise. + * gcc.target/arm/acle/mcr.c: Likewise. + * gcc.target/arm/acle/mcr2.c: Likewise. + * gcc.target/arm/acle/mcrr.c: Likewise. + * gcc.target/arm/acle/mcrr2.c: Likewise. + * gcc.target/arm/acle/mrc.c: Likewise. + * gcc.target/arm/acle/mrc2.c: Likewise. + * gcc.target/arm/acle/mrrc.c: Likewise. + * gcc.target/arm/acle/mrrc2.c: Likewise. + * gcc.target/arm/acle/stc.c: Likewise. + * gcc.target/arm/acle/stc2.c: Likewise. + * gcc.target/arm/acle/stc2l.c: Likewise. + * gcc.target/arm/acle/stcl.c: Likewise. + +2017-05-31 Prakhar Bahuguna <prakhar.bahuguna@arm.com> + + Backport from mainline + 2017-05-04 Prakhar Bahuguna <prakhar.bahuguna@arm.com> + Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com> + + * gcc.target/arm/pure-code/pure-code.exp: Add conditional for + check_effective_target_arm_thumb1_movt_ok. diff --git a/gcc/testsuite/gcc.dg/lto/pr69866_0.c b/gcc/testsuite/gcc.dg/lto/pr69866_0.c new file mode 100644 index 00000000000..f49ef8d4c1d --- /dev/null +++ b/gcc/testsuite/gcc.dg/lto/pr69866_0.c @@ -0,0 +1,13 @@ +/* { dg-lto-do link } */ + +int _umh(int i) +{ + return i+1; +} + +int weaks(int i) __attribute__((weak, alias("_umh"))); + +int main() +{ + return weaks(10); +} diff --git a/gcc/testsuite/gcc.dg/lto/pr69866_1.c b/gcc/testsuite/gcc.dg/lto/pr69866_1.c new file mode 100644 index 00000000000..3a14f850eef --- /dev/null +++ b/gcc/testsuite/gcc.dg/lto/pr69866_1.c @@ -0,0 +1,6 @@ +/* { dg-options { -fno-lto } } */ + +int weaks(int i) +{ + return i+1; +} diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp.c b/gcc/testsuite/gcc.target/arm/acle/cdp.c index 28b218e7cfc..cebd8c4024e 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cdp.c +++ b/gcc/testsuite/gcc.target/arm/acle/cdp.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_cdp (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp2.c b/gcc/testsuite/gcc.target/arm/acle/cdp2.c index 00bcd502b56..945d435d2fb 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cdp2.c +++ b/gcc/testsuite/gcc.target/arm/acle/cdp2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_cdp2 (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc.c b/gcc/testsuite/gcc.target/arm/acle/ldc.c index f45f25d8c97..cd57343208f 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2.c b/gcc/testsuite/gcc.target/arm/acle/ldc2.c index 433bf8a1204..d7691e30d76 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c index 88c8aa44765..9ee63afa055 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/ldcl.c b/gcc/testsuite/gcc.target/arm/acle/ldcl.c index 72a97f1d7b7..a6bfd9011dc 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldcl.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldcl.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr.c b/gcc/testsuite/gcc.target/arm/acle/mcr.c index 93f977a2bdb..7095dcbc3ad 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcr.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcr (uint32_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr2.c b/gcc/testsuite/gcc.target/arm/acle/mcr2.c index 5b60d10ff25..2a4b0ce4559 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcr2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcr2 (uint32_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c index dcc223c713d..bcfbe1a4855 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc3_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x4) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcrr (uint64_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c index 10f2014d447..afd07e67f21 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc4_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x8) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcrr2 (uint64_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc.c b/gcc/testsuite/gcc.target/arm/acle/mrc.c index 34ca6a1638c..809b6c9c265 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint32_t test_mrc (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrc2.c index 3b72a402224..4c06ea39b37 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint32_t test_mrc2 (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c index 28c3b8ea6b5..802de083d5c 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc3_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x4) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint64_t test_mrrc (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c index 5b7aab06222..adf39563e29 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc4_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x8) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint64_t test_mrrc2 (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/stc.c b/gcc/testsuite/gcc.target/arm/acle/stc.c index 7c6e04fe0fe..2714f65787e 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2.c b/gcc/testsuite/gcc.target/arm/acle/stc2.c index 1578f7b1136..0a84652e0f0 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2l.c b/gcc/testsuite/gcc.target/arm/acle/stc2l.c index 7adbd60d48a..2453d04ad72 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc2l.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc2l.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/stcl.c b/gcc/testsuite/gcc.target/arm/acle/stcl.c index 2fd5edd02d7..affdaa27982 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stcl.c +++ b/gcc/testsuite/gcc.target/arm/acle/stcl.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp index 6a5dc552bf3..a5109231926 100644 --- a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp +++ b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp @@ -26,8 +26,9 @@ if ![info exists DEFAULT_CFLAGS] then { } # The -mpure-code option is only available for M-profile targets that support -# thumb2. -if {[check_effective_target_arm_thumb2_ok] +# the MOVT instruction. +if {([check_effective_target_arm_thumb2_ok] + || [check_effective_target_arm_thumb1_movt_ok]) && [check_effective_target_arm_cortex_m]} then { # Initialize `dg'. dg-init diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f08535d43e1..c2a593d5ac0 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3826,7 +3826,8 @@ foreach { armfunc armflag armdef } { v8_1a "-march=armv8.1a" __ARM_ARCH_8A__ v8_2a "-march=armv8.2a" __ARM_ARCH_8A__ v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft" __ARM_ARCH_8M_BASE__ - v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } { + v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ + v8r "-march=armv8-r" __ARM_ARCH_8R__ } { eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] { proc check_effective_target_arm_arch_FUNC_ok { } { if { [ string match "*-marm*" "FLAG" ] && diff --git a/libgcc/ChangeLog.arm b/libgcc/ChangeLog.arm new file mode 100644 index 00000000000..1bdbf014b4e --- /dev/null +++ b/libgcc/ChangeLog.arm @@ -0,0 +1,6 @@ +2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2017-07-06 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 89ebebcd68a..8d8c3cead5f 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #endif #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) + || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) # define __ARM_ARCH__ 8 #endif |