diff options
Diffstat (limited to 'gcc/config/arm/sync.md')
| -rw-r--r-- | gcc/config/arm/sync.md | 94 |
1 files changed, 62 insertions, 32 deletions
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 17eab93d55c..e2ab50441f5 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -66,10 +66,10 @@ (set_attr "predicable" "no")]) (define_insn "atomic_load<mode>" - [(set (match_operand:QHSI 0 "register_operand" "=r") + [(set (match_operand:QHSI 0 "register_operand" "=r,r,l") (unspec_volatile:QHSI - [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q") - (match_operand:SI 2 "const_int_operand")] ;; model + [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q,Q,Q") + (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model VUNSPEC_LDA))] "TARGET_HAVE_LDACQ" { @@ -77,16 +77,22 @@ if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda<sync_sfx>%?\\t%0, %1\"; + { + if (TARGET_THUMB1) + return \"lda<sync_sfx>\\t%0, %1\"; + else + return \"lda<sync_sfx>%?\\t%0, %1\"; + } } - [(set_attr "predicable" "yes") + [(set_attr "arch" "32,v8mb,any") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" - [(set (match_operand:QHSI 0 "memory_operand" "=Q") + [(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q") (unspec_volatile:QHSI - [(match_operand:QHSI 1 "general_operand" "r") - (match_operand:SI 2 "const_int_operand")] ;; model + [(match_operand:QHSI 1 "general_operand" "r,r,l") + (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model VUNSPEC_STL))] "TARGET_HAVE_LDACQ" { @@ -94,9 +100,15 @@ if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>%?\t%1, %0\"; + { + if (TARGET_THUMB1) + return \"stl<sync_sfx>\t%1, %0\"; + else + return \"stl<sync_sfx>%?\t%1, %0\"; + } } - [(set_attr "predicable" "yes") + [(set_attr "arch" "32,v8mb,any") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) ;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets @@ -383,45 +395,57 @@ }) (define_insn "arm_load_exclusive<mode>" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (zero_extend:SI (unspec_volatile:NARROW - [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")] + [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")] VUNSPEC_LL)))] "TARGET_HAVE_LDREXBH" - "ldrex<sync_sfx>%?\t%0, %C1" - [(set_attr "predicable" "yes") + "@ + ldrex<sync_sfx>%?\t%0, %C1 + ldrex<sync_sfx>\t%0, %C1" + [(set_attr "arch" "32,v8mb") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_acquire_exclusive<mode>" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (zero_extend:SI (unspec_volatile:NARROW - [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")] + [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")] VUNSPEC_LAX)))] "TARGET_HAVE_LDACQ" - "ldaex<sync_sfx>%?\\t%0, %C1" - [(set_attr "predicable" "yes") + "@ + ldaex<sync_sfx>%?\\t%0, %C1 + ldaex<sync_sfx>\\t%0, %C1" + [(set_attr "arch" "32,v8mb") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_exclusivesi" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (unspec_volatile:SI - [(match_operand:SI 1 "mem_noofs_operand" "Ua")] + [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")] VUNSPEC_LL))] "TARGET_HAVE_LDREX" - "ldrex%?\t%0, %C1" - [(set_attr "predicable" "yes") + "@ + ldrex%?\t%0, %C1 + ldrex\t%0, %C1" + [(set_attr "arch" "32,v8mb") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_acquire_exclusivesi" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (unspec_volatile:SI - [(match_operand:SI 1 "mem_noofs_operand" "Ua")] + [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")] VUNSPEC_LAX))] "TARGET_HAVE_LDACQ" - "ldaex%?\t%0, %C1" - [(set_attr "predicable" "yes") + "@ + ldaex%?\t%0, %C1 + ldaex\t%0, %C1" + [(set_attr "arch" "32,v8mb") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_exclusivedi" @@ -464,7 +488,10 @@ operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); return "strexd%?\t%0, %2, %3, %C1"; } - return "strex<sync_sfx>%?\t%0, %2, %C1"; + if (TARGET_THUMB1) + return "strex<sync_sfx>\t%0, %2, %C1"; + else + return "strex<sync_sfx>%?\t%0, %2, %C1"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) @@ -488,13 +515,16 @@ (set_attr "predicable_short_it" "no")]) (define_insn "arm_store_release_exclusive<mode>" - [(set (match_operand:SI 0 "s_register_operand" "=&r") + [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX)) - (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua") + (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua,Ua") (unspec_volatile:QHSI - [(match_operand:QHSI 2 "s_register_operand" "r")] + [(match_operand:QHSI 2 "s_register_operand" "r,r")] VUNSPEC_SLX))] "TARGET_HAVE_LDACQ" - "stlex<sync_sfx>%?\t%0, %2, %C1" - [(set_attr "predicable" "yes") + "@ + stlex<sync_sfx>%?\t%0, %2, %C1 + stlex<sync_sfx>\t%0, %2, %C1" + [(set_attr "arch" "32,v8mb") + (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) |