diff options
Diffstat (limited to 'gcc/config/i386/i386.c')
| -rw-r--r-- | gcc/config/i386/i386.c | 99 |
1 files changed, 78 insertions, 21 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index bbf28efa6dd..d8aca59f54c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -518,7 +518,7 @@ struct processor_costs pentium4_cost = { in SImode and DImode */ {2, 2}, /* cost of storing MMX registers in SImode and DImode */ - 12, /* cost of moving SSE register */ + 4, /* cost of moving SSE register */ {12, 12, 12}, /* cost of loading SSE registers in SImode, DImode and TImode */ {2, 2, 8}, /* cost of storing SSE registers @@ -587,6 +587,58 @@ struct processor_costs nocona_cost = { COSTS_N_INSNS (44), /* cost of FSQRT instruction. */ }; +static const +struct processor_costs woodcrest_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (10), /* cost of starting multiply for QI */ + COSTS_N_INSNS (10), /* HI */ + COSTS_N_INSNS (10), /* SI */ + COSTS_N_INSNS (10), /* DI */ + COSTS_N_INSNS (10)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (66), /* HI */ + COSTS_N_INSNS (66), /* SI */ + COSTS_N_INSNS (66), /* DI */ + COSTS_N_INSNS (66)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 6, /* MOVE_RATIO */ + 3, /* cost for loading QImode using movzbl */ + {3, 3, 3}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {2, 2, 2}, /* cost of storing integer registers */ + 1, /* cost of reg,reg fld/fst */ + {3, 3, 6}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {2, 2, 4}, /* cost of loading integer registers */ + 6, /* cost of moving MMX register */ + {3, 3}, /* cost of loading MMX registers + in SImode and DImode */ + {2, 2}, /* cost of storing MMX registers + in SImode and DImode */ + 1, /* cost of moving SSE register */ + {3, 3, 6}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {2, 2, 4}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 1, /* MMX or SSE register to integer */ + 32, /* size of prefetch block */ + 6, /* number of parallel prefetches */ + 2, /* Branch cost */ + COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (5), /* cost of FMUL instruction. */ + COSTS_N_INSNS (40), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (40), /* cost of FSQRT instruction. */ +}; + /* Generic64 should produce code tuned for Nocona and K8. */ static const struct processor_costs generic64_cost = { @@ -712,12 +764,13 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_K8 (1<<PROCESSOR_K8) #define m_ATHLON_K8 (m_K8 | m_ATHLON) #define m_NOCONA (1<<PROCESSOR_NOCONA) +#define m_WOODCREST (1<<PROCESSOR_WOODCREST) #define m_GENERIC32 (1<<PROCESSOR_GENERIC32) #define m_GENERIC64 (1<<PROCESSOR_GENERIC64) #define m_GENERIC (m_GENERIC32 | m_GENERIC64) /* Generic instruction choice should be common subset of supported CPUs - (PPro/PENT4/NOCONA/Athlon/K8). */ + (PPro/PENT4/NOCONA/WOODCREST/Athlon/K8). */ /* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for Generic64 seems like good code size tradeoff. We can't enable it for 32bit @@ -725,20 +778,20 @@ const struct processor_costs *ix86_cost = &pentium_cost; const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8 | m_GENERIC64; const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; const int x86_zero_extend_with_and = m_486 | m_PENT; -const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */; +const int x86_movx = m_ATHLON_K8 | m_PPRO | m_WOODCREST | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */; const int x86_double_with_add = ~m_386; const int x86_use_bit_test = m_386; -const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC; -const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA; +const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_WOODCREST | m_ATHLON_K8 | m_K6 | m_GENERIC; +const int x86_cmove = m_PPRO | m_WOODCREST | m_ATHLON_K8 | m_PENT4 | m_NOCONA; const int x86_fisttp = m_NOCONA; const int x86_3dnow_a = m_ATHLON_K8; -const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_deep_branch = m_PPRO | m_WOODCREST | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; /* Branch hints were put in P4 based on simulation result. But after P4 was made, no performance benefit was observed with branch hints. It also increases the code size. As the result, icc never generates branch hints. */ const int x86_branch_hints = 0; -const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */ +const int x86_use_sahf = m_PPRO | m_WOODCREST | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */ /* We probably ought to watch for partial register stalls on Generic32 compilation setting as well. However in current implementation the partial register stalls are not eliminated very well - they can @@ -749,7 +802,7 @@ const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_G to leave it off for generic32 for now. */ const int x86_partial_reg_stall = m_PPRO; const int x86_use_himode_fiop = m_386 | m_486 | m_K6; -const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC); +const int x86_use_simode_fiop = ~(m_PPRO | m_WOODCREST | m_ATHLON_K8 | m_PENT | m_GENERIC); const int x86_use_mov0 = m_K6; const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC); const int x86_read_modify_write = ~m_PENT; @@ -765,18 +818,18 @@ const int x86_promote_qi_regs = 0; if our scheme for avoiding partial stalls was more effective. */ const int x86_himode_math = ~(m_PPRO); const int x86_promote_hi_regs = m_PPRO; -const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC; -const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_WOODCREST | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_WOODCREST | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC; const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC; -const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC; -const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC); +const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_WOODCREST | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_WOODCREST | m_GENERIC); const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; -const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC; -const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC; -const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC; +const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_WOODCREST | m_GENERIC; +const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_WOODCREST | m_GENERIC; +const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_WOODCREST | m_GENERIC; const int x86_shift1 = ~m_486; -const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_WOODCREST | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; /* In Generic model we have an conflict here in between PPro/Pentium4 based chips that thread 128bit SSE registers as single units versus K8 based chips that divide SSE registers to two 64bit halves. @@ -786,26 +839,26 @@ const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PEN this option on P4 brings over 20% SPECfp regression, while enabling it on K8 brings roughly 2.4% regression that can be partly masked by careful scheduling of moves. */ -const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC; +const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_WOODCREST | m_GENERIC; /* Set for machines where the type and dependencies are resolved on SSE register parts instead of whole registers, so we may maintain just lower part of scalar values in proper format leaving the upper part undefined. */ const int x86_sse_split_regs = m_ATHLON_K8; const int x86_sse_typeless_stores = m_ATHLON_K8; -const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA; +const int x86_sse_load0_by_pxor = m_PPRO | m_WOODCREST | m_PENT4 | m_NOCONA; const int x86_use_ffreep = m_ATHLON_K8; -const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6; +const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_WOODCREST | m_K6; const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC); /* ??? Allowing interunit moves makes it all too easy for the compiler to put integer data in xmm registers. Which results in pretty abysmal code. */ const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */; -const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32; +const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_WOODCREST | m_GENERIC32; /* Some CPU cores are not able to predict more than 4 branch instructions in the 16 byte window. */ -const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_four_jump_limit = m_PPRO | m_WOODCREST | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT | m_GENERIC; const int x86_use_bt = m_ATHLON_K8; /* Compare and exchange was added for 80486. */ @@ -1448,6 +1501,7 @@ override_options (void) {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0}, {&k8_cost, 0, 0, 16, 7, 16, 7, 16}, {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}, + {&woodcrest_cost, 0, 0, 16, 15, 16, 7, 16}, {&generic32_cost, 0, 0, 16, 7, 16, 7, 16}, {&generic64_cost, 0, 0, 16, 7, 16, 7, 16} }; @@ -1494,6 +1548,9 @@ override_options (void) | PTA_MMX | PTA_PREFETCH_SSE}, {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT | PTA_MMX | PTA_PREFETCH_SSE}, + {"woodcrest", PROCESSOR_WOODCREST, PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_64BIT | PTA_MMX + | PTA_PREFETCH_SSE}, {"k6", PROCESSOR_K6, PTA_MMX}, {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW}, {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW}, |