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-rw-r--r--gcc/config/i386/i386.md396
1 files changed, 179 insertions, 217 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 920b9dde8a1..a76c7802e49 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -58,6 +58,7 @@
(UNSPEC_DTPOFF 6)
(UNSPEC_GOTNTPOFF 7)
(UNSPEC_INDNTPOFF 8)
+ (UNSPEC_PLTOFF 9)
; Prologue support
(UNSPEC_STACK_ALLOC 11)
@@ -65,36 +66,38 @@
(UNSPEC_SSE_PROLOGUE_SAVE 13)
(UNSPEC_REG_SAVE 14)
(UNSPEC_DEF_CFA 15)
+ (UNSPEC_SET_RIP 16)
+ (UNSPEC_SET_GOT_OFFSET 17)
; TLS support
- (UNSPEC_TP 16)
- (UNSPEC_TLS_GD 17)
- (UNSPEC_TLS_LD_BASE 18)
- (UNSPEC_TLSDESC 19)
+ (UNSPEC_TP 18)
+ (UNSPEC_TLS_GD 19)
+ (UNSPEC_TLS_LD_BASE 20)
+ (UNSPEC_TLSDESC 21)
; Other random patterns
- (UNSPEC_SCAS 20)
- (UNSPEC_FNSTSW 21)
- (UNSPEC_SAHF 22)
- (UNSPEC_FSTCW 23)
- (UNSPEC_ADD_CARRY 24)
- (UNSPEC_FLDCW 25)
- (UNSPEC_REP 26)
- (UNSPEC_EH_RETURN 27)
- (UNSPEC_LD_MPIC 28) ; load_macho_picbase
- (UNSPEC_TRUNC_NOOP 29)
+ (UNSPEC_SCAS 30)
+ (UNSPEC_FNSTSW 31)
+ (UNSPEC_SAHF 32)
+ (UNSPEC_FSTCW 33)
+ (UNSPEC_ADD_CARRY 34)
+ (UNSPEC_FLDCW 35)
+ (UNSPEC_REP 36)
+ (UNSPEC_EH_RETURN 37)
+ (UNSPEC_LD_MPIC 38) ; load_macho_picbase
+ (UNSPEC_TRUNC_NOOP 39)
; For SSE/MMX support:
- (UNSPEC_FIX_NOTRUNC 30)
- (UNSPEC_MASKMOV 31)
- (UNSPEC_MOVMSK 32)
- (UNSPEC_MOVNT 33)
- (UNSPEC_MOVU 34)
- (UNSPEC_RCP 35)
- (UNSPEC_RSQRT 36)
- (UNSPEC_SFENCE 37)
- (UNSPEC_NOP 38) ; prevents combiner cleverness
- (UNSPEC_PFRCP 39)
+ (UNSPEC_FIX_NOTRUNC 40)
+ (UNSPEC_MASKMOV 41)
+ (UNSPEC_MOVMSK 42)
+ (UNSPEC_MOVNT 43)
+ (UNSPEC_MOVU 44)
+ (UNSPEC_RCP 45)
+ (UNSPEC_RSQRT 46)
+ (UNSPEC_SFENCE 47)
+ (UNSPEC_NOP 48) ; prevents combiner cleverness
+ (UNSPEC_PFRCP 49)
(UNSPEC_PFRCPIT1 40)
(UNSPEC_PFRCPIT2 41)
(UNSPEC_PFRSQRT 42)
@@ -141,6 +144,8 @@
(UNSPEC_FPREM1_F 90)
(UNSPEC_FPREM1_U 91)
+ (UNSPEC_C2_FLAG 95)
+
; SSP patterns
(UNSPEC_SP_SET 100)
(UNSPEC_SP_TEST 101)
@@ -980,9 +985,10 @@
(define_insn "x86_sahf_1"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
- "!TARGET_64BIT"
- "sahf"
+ (unspec:CC [(match_operand:HI 0 "register_operand" "a")]
+ UNSPEC_SAHF))]
+ "TARGET_SAHF"
+ "* return HAVE_AS_IX86_SAHF ? \"sahf\" : \".byte\t0x9e\";"
[(set_attr "length" "1")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
@@ -1176,7 +1182,7 @@
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& operands[1] == constm1_rtx
- && (TARGET_PENTIUM || optimize_size)"
+ && (TARGET_MOVE_M1_VIA_OR || optimize_size)"
{
operands[1] = constm1_rtx;
return "or{l}\t{%1, %0|%0, %1}";
@@ -1968,7 +1974,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const_int_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
+ "TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size)
&& reload_completed
&& operands[1] == constm1_rtx"
{
@@ -2022,9 +2028,9 @@
(define_insn "*movdi_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=r,r ,r,m ,!m,*y,*y,?r ,m ,?*Ym,*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym")
+ "=r,r ,r,m ,!m,*y,*y,?r ,m ,?*Ym,?*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym")
(match_operand:DI 1 "general_operand"
- "Z ,rem,i,re,n ,C ,*y,*Ym,*y,r ,m ,C ,*x,*Yi,*x,r ,m ,*Ym,*x"))]
+ "Z ,rem,i,re,n ,C ,*y,*Ym,*y,r ,m ,C ,*x,*Yi,*x,r ,m ,*Ym,*x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (get_attr_type (insn))
@@ -2266,6 +2272,22 @@
[(const_int 0)]
"ix86_split_long_move (operands); DONE;")
+;; This expands to what emit_move_complex would generate if we didn't
+;; have a movti pattern. Having this avoids problems with reload on
+;; 32-bit targets when SSE is present, but doesn't seem to be harmful
+;; to have around all the time.
+(define_expand "movcdi"
+ [(set (match_operand:CDI 0 "nonimmediate_operand" "")
+ (match_operand:CDI 1 "general_operand" ""))]
+ ""
+{
+ if (push_operand (operands[0], CDImode))
+ emit_move_complex_push (CDImode, operands[0], operands[1]);
+ else
+ emit_move_complex_parts (operands[0], operands[1]);
+ DONE;
+})
+
(define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "general_operand" ""))]
@@ -2326,9 +2348,9 @@
(define_insn "*movsf_1"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=f,m,f,r ,m ,x,x,x ,m,*y,m ,*y,Yi,r ,*Ym,r ")
+ "=f,m,f,r ,m ,x,x,x ,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
(match_operand:SF 1 "general_operand"
- "fm,f,G,rmF,Fr,C,x,xm,x,m ,*y,*y,r ,Yi,r ,*Ym"))]
+ "fm,f,G,rmF,Fr,C,x,xm,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
@@ -3401,9 +3423,9 @@
})
(define_insn "zero_extendsidi2_32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,*y,?*Yi,*Y2")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Y2")
(zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
+ (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"@
@@ -3418,9 +3440,9 @@
(set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")])
(define_insn "zero_extendsidi2_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,*y,?*Yi,*Y2")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Y2")
(zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
+ (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
"TARGET_64BIT"
"@
mov\t{%k1, %k0|%k0, %k1}
@@ -4374,90 +4396,54 @@
;; Without these patterns, we'll try the unsigned SI conversion which
;; is complex for SSE, rather than the signed SI conversion, which isn't.
-(define_expand "fixuns_truncsfhi2"
+(define_expand "fixuns_trunc<mode>hi2"
[(set (match_dup 2)
- (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))
+ (fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "")))
(set (match_operand:HI 0 "nonimmediate_operand" "")
(subreg:HI (match_dup 2) 0))]
- "TARGET_SSE_MATH"
- "operands[2] = gen_reg_rtx (SImode);")
-
-(define_expand "fixuns_truncdfhi2"
- [(set (match_dup 2)
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))
- (set (match_operand:HI 0 "nonimmediate_operand" "")
- (subreg:HI (match_dup 2) 0))]
- "TARGET_SSE_MATH && TARGET_SSE2"
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"operands[2] = gen_reg_rtx (SImode);")
;; When SSE is available, it is always faster to use it!
-(define_insn "fix_truncsfdi_sse"
+(define_insn "fix_trunc<mode>di_sse"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
- "TARGET_64BIT && TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "cvttss2si{q}\t{%1, %0|%0, %1}"
+ (fix:DI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,xm")))]
+ "TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
+ && (!TARGET_FISTTP || TARGET_SSE_MATH)"
+ "cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
- (set_attr "mode" "SF")
- (set_attr "athlon_decode" "double,vector")
- (set_attr "amdfam10_decode" "double,double")])
-
-(define_insn "fix_truncdfdi_sse"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (fix:DI (match_operand:DF 1 "nonimmediate_operand" "x,xm")))]
- "TARGET_64BIT && TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "cvttsd2si{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,vector")
- (set_attr "amdfam10_decode" "double,double")])
-
-(define_insn "fix_truncsfsi_sse"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
- "TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "cvttss2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
+ (set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
-(define_insn "fix_truncdfsi_sse"
+(define_insn "fix_trunc<mode>si_sse"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "x,xm")))]
- "TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "cvttsd2si\t{%1, %0|%0, %1}"
+ (fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,xm")))]
+ "SSE_FLOAT_MODE_P (<MODE>mode)
+ && (!TARGET_FISTTP || TARGET_SSE_MATH)"
+ "cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
+ (set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns.
(define_peephole2
- [(set (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "memory_operand" ""))
- (set (match_operand:SSEMODEI24 2 "register_operand" "")
- (fix:SSEMODEI24 (match_dup 0)))]
- "!TARGET_K8
- && peep2_reg_dead_p (2, operands[0])"
- [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
- "")
-
-(define_peephole2
- [(set (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "memory_operand" ""))
+ [(set (match_operand:SSEMODEF 0 "register_operand" "")
+ (match_operand:SSEMODEF 1 "memory_operand" ""))
(set (match_operand:SSEMODEI24 2 "register_operand" "")
(fix:SSEMODEI24 (match_dup 0)))]
- "!TARGET_K8
+ "TARGET_SHORTEN_X87_SSE
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
"")
;; Avoid vector decoded forms of the instruction.
(define_peephole2
- [(match_scratch:DF 2 "Y")
+ [(match_scratch:DF 2 "Y2")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
- "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
+ "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
@@ -4466,7 +4452,7 @@
[(match_scratch:SF 2 "x")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
- "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
+ "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
@@ -14334,7 +14320,9 @@
rtx op0, op1;
enum rtx_code code;
- if (TARGET_64BIT)
+ /* We can't use @GOTOFF for text labels on VxWorks;
+ see gotoff_operand. */
+ if (TARGET_64BIT || TARGET_VXWORKS_RTP)
{
code = PLUS;
op0 = operands[0];
@@ -14529,7 +14517,8 @@
(define_insn "*call_1_rex64"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT
+ && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
{
if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
@@ -14537,6 +14526,13 @@
}
[(set_attr "type" "call")])
+(define_insn "*call_1_rex64_large"
+ [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rm"))
+ (match_operand 1 "" ""))]
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "call\t%A0"
+ [(set_attr "type" "call")])
+
(define_insn "*sibcall_1_rex64"
[(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
(match_operand 1 "" ""))]
@@ -14753,6 +14749,22 @@
[(set_attr "type" "lea")
(set_attr "length" "6")])
+(define_insn "set_rip_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
+ "TARGET_64BIT"
+ "lea{q}\t%l1(%%rip), %0"
+ [(set_attr "type" "lea")
+ (set_attr "length" "6")])
+
+(define_insn "set_got_offset_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
+ "TARGET_64BIT"
+ "movabs{q}\t$_GLOBAL_OFFSET_TABLE_-%l1, %0"
+ [(set_attr "type" "imov")
+ (set_attr "length" "11")])
+
(define_expand "epilogue"
[(const_int 1)]
""
@@ -16269,7 +16281,8 @@
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FPREM_U))
(set (reg:CCFP FPSR_REG)
- (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
+ (unspec:CCFP [(match_dup 2) (match_dup 3)]
+ UNSPEC_C2_FLAG))]
"TARGET_USE_FANCY_MATH_387"
"fprem"
[(set_attr "type" "fpspc")
@@ -16288,6 +16301,7 @@
emit_insn (gen_fpremxf4_i387 (operands[1], operands[2],
operands[1], operands[2]));
ix86_emit_fp_unordered_jump (label);
+ LABEL_NUSES (label) = 1;
emit_move_insn (operands[0], operands[1]);
DONE;
@@ -16310,6 +16324,7 @@
emit_label (label);
emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
+ LABEL_NUSES (label) = 1;
/* Truncate the result properly for strict SSE math. */
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
@@ -16330,7 +16345,8 @@
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FPREM1_U))
(set (reg:CCFP FPSR_REG)
- (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
+ (unspec:CCFP [(match_dup 2) (match_dup 3)]
+ UNSPEC_C2_FLAG))]
"TARGET_USE_FANCY_MATH_387"
"fprem1"
[(set_attr "type" "fpspc")
@@ -16349,6 +16365,7 @@
emit_insn (gen_fprem1xf4_i387 (operands[1], operands[2],
operands[1], operands[2]));
ix86_emit_fp_unordered_jump (label);
+ LABEL_NUSES (label) = 1;
emit_move_insn (operands[0], operands[1]);
DONE;
@@ -16372,6 +16389,7 @@
emit_insn (gen_fprem1xf4_i387 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
+ LABEL_NUSES (label) = 1;
/* Truncate the result properly for strict SSE math. */
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
@@ -17264,54 +17282,28 @@
})
-(define_insn "frndintxf2"
+(define_insn "rintxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT))]
+ UNSPEC_FRNDINT))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"frndint"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
-(define_expand "rintdf2"
- [(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:DF 1 "register_operand" ""))]
+(define_expand "rint<mode>2"
+ [(use (match_operand:SSEMODEF 0 "register_operand" ""))
+ (use (match_operand:SSEMODEF 1 "register_operand" ""))]
"(TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations)
- || (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
&& !optimize_size)"
{
- if (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && !optimize_size)
- ix86_expand_rint (operand0, operand1);
- else
- {
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
-
- emit_insn (gen_extenddfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2 (op0, op1));
-
- emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
- }
- DONE;
-})
-
-(define_expand "rintsf2"
- [(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:SF 1 "register_operand" ""))]
- "(TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations)
- || (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && !optimize_size)"
-{
- if (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
+ if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
&& !optimize_size)
ix86_expand_rint (operand0, operand1);
@@ -17320,43 +17312,22 @@
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- emit_insn (gen_extendsfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2 (op0, op1));
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_rintxf2 (op0, op1));
- emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
}
DONE;
})
-(define_expand "rintxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- emit_insn (gen_frndintxf2 (operands[0], operands[1]));
- DONE;
-})
-
-(define_expand "roundsf2"
- [(match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "nonimmediate_operand" "")]
- "SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
- && !flag_trapping_math && !flag_rounding_math
- && !optimize_size"
-{
- ix86_expand_round (operand0, operand1);
- DONE;
-})
-
-(define_expand "rounddf2"
- [(match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "nonimmediate_operand" "")]
- "SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
+(define_expand "round<mode>2"
+ [(match_operand:SSEMODEF 0 "register_operand" "")
+ (match_operand:SSEMODEF 1 "nonimmediate_operand" "")]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math && !flag_rounding_math
&& !optimize_size"
{
- if (TARGET_64BIT)
+ if ((<MODE>mode != DFmode) || TARGET_64BIT)
ix86_expand_round (operand0, operand1);
else
ix86_expand_rounddf_32 (operand0, operand1);
@@ -17366,7 +17337,7 @@
(define_insn_and_split "*fistdi2_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
(unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
- UNSPEC_FIST))]
+ UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
&& !(reload_completed || reload_in_progress)"
"#"
@@ -17389,7 +17360,7 @@
(define_insn "fistdi2"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_scratch:XF 2 "=&1f"))]
"TARGET_USE_FANCY_MATH_387"
"* return output_fix_trunc (insn, operands, 0);"
@@ -17399,7 +17370,7 @@
(define_insn "fistdi2_with_temp"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
(unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_operand:DI 2 "memory_operand" "=m,m"))
(clobber (match_scratch:XF 3 "=&1f,&1f"))]
"TARGET_USE_FANCY_MATH_387"
@@ -17410,7 +17381,7 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(unspec:DI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_operand:DI 2 "memory_operand" ""))
(clobber (match_scratch 3 ""))]
"reload_completed"
@@ -17422,7 +17393,7 @@
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(unspec:DI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_operand:DI 2 "memory_operand" ""))
(clobber (match_scratch 3 ""))]
"reload_completed"
@@ -17433,7 +17404,7 @@
(define_insn_and_split "*fist<mode>2_1"
[(set (match_operand:X87MODEI12 0 "register_operand" "=r")
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST))]
+ UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
&& !(reload_completed || reload_in_progress)"
"#"
@@ -17451,7 +17422,7 @@
(define_insn "fist<mode>2"
[(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST))]
+ UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387"
"* return output_fix_trunc (insn, operands, 0);"
[(set_attr "type" "fpspc")
@@ -17460,7 +17431,7 @@
(define_insn "fist<mode>2_with_temp"
[(set (match_operand:X87MODEI12 0 "register_operand" "=r")
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_operand:X87MODEI12 2 "memory_operand" "=m"))]
"TARGET_USE_FANCY_MATH_387"
"#"
@@ -17470,60 +17441,42 @@
(define_split
[(set (match_operand:X87MODEI12 0 "register_operand" "")
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
"reload_completed"
- [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)]
- UNSPEC_FIST))
+ [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))
(set (match_dup 0) (match_dup 2))]
"")
(define_split
[(set (match_operand:X87MODEI12 0 "memory_operand" "")
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST))
+ UNSPEC_FIST))
(clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
"reload_completed"
- [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
- UNSPEC_FIST))]
+ [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))]
"")
(define_expand "lrintxf<mode>2"
[(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
(unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST))]
+ UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387"
"")
-(define_expand "lrint<mode>di2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (unspec:DI [(match_operand:SSEMODEF 1 "register_operand" "")]
- UNSPEC_FIX_NOTRUNC))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT"
- "")
-
-(define_expand "lrint<mode>si2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (unspec:SI [(match_operand:SSEMODEF 1 "register_operand" "")]
- UNSPEC_FIX_NOTRUNC))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+(define_expand "lrint<SSEMODEF:mode><SSEMODEI24:mode>2"
+ [(set (match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
+ (unspec:SSEMODEI24 [(match_operand:SSEMODEF 1 "register_operand" "")]
+ UNSPEC_FIX_NOTRUNC))]
+ "SSE_FLOAT_MODE_P (<SSEMODEF:MODE>mode) && TARGET_SSE_MATH
+ && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)"
"")
-(define_expand "lround<mode>di2"
- [(match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:SSEMODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
- && !flag_trapping_math && !flag_rounding_math
- && !optimize_size"
-{
- ix86_expand_lround (operand0, operand1);
- DONE;
-})
-
-(define_expand "lround<mode>si2"
- [(match_operand:SI 0 "nonimmediate_operand" "")
+(define_expand "lround<SSEMODEF:mode><SSEMODEI24:mode>2"
+ [(match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
(match_operand:SSEMODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
+ "SSE_FLOAT_MODE_P (<SSEMODEF:MODE>mode) && TARGET_SSE_MATH
+ && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)
&& !flag_trapping_math && !flag_rounding_math
&& !optimize_size"
{
@@ -20071,10 +20024,10 @@
(not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
"!optimize_size
&& peep2_regno_dead_p (0, FLAGS_REG)
- && ((TARGET_PENTIUM
+ && ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], SImode)))
- || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
+ || (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], SImode)))"
[(parallel [(set (match_dup 0)
(xor:SI (match_dup 1) (const_int -1)))
(clobber (reg:CC FLAGS_REG))])]
@@ -20085,10 +20038,10 @@
(not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
"!optimize_size
&& peep2_regno_dead_p (0, FLAGS_REG)
- && ((TARGET_PENTIUM
+ && ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], HImode)))
- || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
+ || (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], HImode)))"
[(parallel [(set (match_dup 0)
(xor:HI (match_dup 1) (const_int -1)))
(clobber (reg:CC FLAGS_REG))])]
@@ -20099,10 +20052,10 @@
(not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
"!optimize_size
&& peep2_regno_dead_p (0, FLAGS_REG)
- && ((TARGET_PENTIUM
+ && ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], QImode)))
- || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
+ || (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], QImode)))"
[(parallel [(set (match_dup 0)
(xor:QI (match_dup 1) (const_int -1)))
(clobber (reg:CC FLAGS_REG))])]
@@ -20284,7 +20237,7 @@
"(GET_MODE (operands[0]) == HImode
|| GET_MODE (operands[0]) == SImode
|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
- && (optimize_size || TARGET_PENTIUM)
+ && (optimize_size || TARGET_MOVE_M1_VIA_OR)
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int -1))
(clobber (reg:CC FLAGS_REG))])]
@@ -20688,7 +20641,7 @@
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+ "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
@@ -20701,7 +20654,7 @@
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+ "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
@@ -20715,7 +20668,7 @@
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
- "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+ "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
@@ -20732,7 +20685,7 @@
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:DI 3 "r")]
- "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+ "TARGET_SLOW_IMUL_IMM8 && !optimize_size
&& satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
@@ -20748,7 +20701,7 @@
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SI 3 "r")]
- "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+ "TARGET_SLOW_IMUL_IMM8 && !optimize_size
&& satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
@@ -20764,7 +20717,7 @@
(match_operand:HI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:HI 3 "r")]
- "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size"
+ "TARGET_SLOW_IMUL_IMM8 && !optimize_size"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
@@ -20925,7 +20878,8 @@
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
(match_operand:DI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT
+ && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
{
if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
@@ -20933,6 +20887,14 @@
}
[(set_attr "type" "callv")])
+(define_insn "*call_value_1_rex64_large"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rm"))
+ (match_operand:DI 2 "" "")))]
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "call\t%A1"
+ [(set_attr "type" "callv")])
+
(define_insn "*sibcall_value_1_rex64"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 21:42:18 +0000