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Diffstat (limited to 'gcc/config/i386/i386.md')
-rw-r--r--gcc/config/i386/i386.md218
1 files changed, 135 insertions, 83 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a62fd2fcf38..36a0497818e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1733,8 +1733,13 @@
(set_attr "mode" "SI")
(set_attr "length_immediate" "1")])
+; The first alternative is used only to compute proper length of instruction.
+; Reload's algorithm does not take into account the cost of spill instructions
+; needed to free register in given class, so avoid it from choosing the first
+; alternative when eax is not available.
+
(define_insn "*movsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
(match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
{
@@ -1843,8 +1848,13 @@
[(set_attr "type" "push")
(set_attr "mode" "QI")])
+; The first alternative is used only to compute proper length of instruction.
+; Reload's algorithm does not take into account the cost of spill instructions
+; needed to free register in given class, so avoid it from choosing the first
+; alternative when eax is not available.
+
(define_insn "*movhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
(match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
{
@@ -2004,7 +2014,7 @@
;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushqi2_rex64"
[(set (match_operand:QI 0 "push_operand" "=X")
- (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
+ (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
"TARGET_64BIT"
"push{q}\t%q1"
[(set_attr "type" "push")
@@ -2545,17 +2555,16 @@
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsdi_1_rex64"
- [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
- (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
+ [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
+ (match_operand:DI 1 "nonmemory_operand" "a,er"))]
"TARGET_64BIT"
"@
movabs{q}\t{%1, %P0|%P0, %1}
- mov{q}\t{%1, %a0|%a0, %1}
- movabs{q}\t{%1, %a0|%a0, %1}"
+ mov{q}\t{%1, %a0|%a0, %1}"
[(set_attr "type" "imov")
- (set_attr "modrm" "0,*,*")
- (set_attr "length_address" "8,0,0")
- (set_attr "length_immediate" "0,*,*")
+ (set_attr "modrm" "0,*")
+ (set_attr "length_address" "8,0")
+ (set_attr "length_immediate" "0,*")
(set_attr "memory" "store")
(set_attr "mode" "DI")])
@@ -2754,7 +2763,10 @@
case 4:
return "mov{l}\t{%1, %0|%0, %1}";
case 5:
- return "pxor\t%0, %0";
+ if (TARGET_SSE2)
+ return "pxor\t%0, %0";
+ else
+ return "xorps\t%0, %0";
case 6:
if (TARGET_PARTIAL_REG_DEPENDENCY)
return "movaps\t{%1, %0|%0, %1}";
@@ -5136,7 +5148,7 @@
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
- ""
+ "TARGET_80387 || TARGET_SSE2"
"")
(define_insn "*floatsidf2_i387"
@@ -5299,7 +5311,7 @@
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "roiF,riF")))
(clobber (reg:CC 17))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
"#")
(define_split
@@ -6928,7 +6940,7 @@
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "general_operand" "roiF,riF")))
(clobber (reg:CC 17))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
"#")
(define_split
@@ -10938,7 +10950,7 @@
[(set (reg 17)
(compare
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashift:SI (match_dup 1) (match_dup 2)))]
@@ -10977,7 +10989,7 @@
[(set (reg 17)
(compare
(ashift:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
@@ -11102,7 +11114,7 @@
[(set (reg 17)
(compare
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashift:HI (match_dup 1) (match_dup 2)))]
@@ -11266,7 +11278,7 @@
[(set (reg 17)
(compare
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashift:QI (match_dup 1) (match_dup 2)))]
@@ -11616,7 +11628,7 @@
[(set (reg 17)
(compare
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
@@ -11630,7 +11642,7 @@
[(set (reg 17)
(compare
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
@@ -11702,7 +11714,7 @@
[(set (reg 17)
(compare
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_dup 1) (match_dup 2)))]
@@ -11755,7 +11767,7 @@
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_operand" "I"))
(const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
+ (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
@@ -11774,9 +11786,9 @@
[(set (reg 17)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
+ (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
@@ -12007,7 +12019,7 @@
[(set (reg 17)
(compare
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
@@ -12021,7 +12033,7 @@
[(set (reg 17)
(compare
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
@@ -12093,7 +12105,7 @@
[(set (reg 17)
(compare
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_dup 1) (match_dup 2)))]
@@ -12165,7 +12177,7 @@
[(set (reg 17)
(compare
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "const_int_1_31_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(lshiftrt:QI (match_dup 1) (match_dup 2)))]
@@ -13681,7 +13693,7 @@
simply pretend the untyped call returns a complex long double
value. */
- emit_call_insn (TARGET_80387
+ emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387
? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
operands[0], const0_rtx,
GEN_INT (SSE_REGPARM_MAX - 1))
@@ -13803,6 +13815,7 @@
{
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[1]));
+ return "pop{l}\t%0";
}
RET;
}
@@ -14709,7 +14722,7 @@
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))]
- "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
+ "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
@@ -14729,7 +14742,7 @@
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))]
- "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
+ "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
@@ -14776,7 +14789,7 @@
(define_insn "sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
- "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
+ "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
@@ -15896,8 +15909,8 @@
"TARGET_64BIT && TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- cmov%C1\t{%2, %0|%0, %2}
- cmov%c1\t{%3, %0|%0, %3}"
+ cmov%O2%C1\t{%2, %0|%0, %2}
+ cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
(set_attr "mode" "DI")])
@@ -15938,8 +15951,8 @@
"TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- cmov%C1\t{%2, %0|%0, %2}
- cmov%c1\t{%3, %0|%0, %3}"
+ cmov%O2%C1\t{%2, %0|%0, %2}
+ cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
(set_attr "mode" "SI")])
@@ -15960,8 +15973,8 @@
"TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- cmov%C1\t{%2, %0|%0, %2}
- cmov%c1\t{%3, %0|%0, %3}"
+ cmov%O2%C1\t{%2, %0|%0, %2}
+ cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
(set_attr "mode" "HI")])
@@ -15984,8 +15997,8 @@
"@
fcmov%F1\t{%2, %0|%0, %2}
fcmov%f1\t{%3, %0|%0, %3}
- cmov%C1\t{%2, %0|%0, %2}
- cmov%c1\t{%3, %0|%0, %3}"
+ cmov%O2%C1\t{%2, %0|%0, %2}
+ cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov,fcmov,icmov,icmov")
(set_attr "mode" "SF,SF,SI,SI")])
@@ -16024,8 +16037,8 @@
"@
fcmov%F1\t{%2, %0|%0, %2}
fcmov%f1\t{%3, %0|%0, %3}
- cmov%C1\t{%2, %0|%0, %2}
- cmov%c1\t{%3, %0|%0, %3}"
+ cmov%O2%C1\t{%2, %0|%0, %2}
+ cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov,fcmov,icmov,icmov")
(set_attr "mode" "DF")])
@@ -16563,12 +16576,12 @@
"#")
(define_insn "sse_movdfcc"
- [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
+ [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
(if_then_else:DF (match_operator 1 "sse_comparison_operator"
- [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
- (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
- (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
- (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
+ [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
+ (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
+ (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
+ (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
(clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
(clobber (reg:CC 17))]
"TARGET_SSE2
@@ -16578,11 +16591,11 @@
"#")
(define_insn "sse_movdfcc_eq"
- [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
- (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
- (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
- (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
- (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
+ [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
+ (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
+ (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
+ (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
+ (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
(clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
(clobber (reg:CC 17))]
"TARGET_SSE
@@ -16634,6 +16647,10 @@
(set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
(subreg:TI (match_dup 7) 0)))]
{
+ /* If op2 == op3, op3 will be clobbered before it is used.
+ This should be optimized out though. */
+ if (operands_match_p (operands[2], operands[3]))
+ abort ();
PUT_MODE (operands[1], GET_MODE (operands[0]));
if (operands_match_p (operands[0], operands[4]))
operands[6] = operands[4], operands[7] = operands[2];
@@ -16645,7 +16662,7 @@
;; Do not brother with the integer/floating point case, since these are
;; bot considerably slower, unlike in the generic case.
(define_insn "*sse_movsfcc_const0_1"
- [(set (match_operand:SF 0 "register_operand" "=x")
+ [(set (match_operand:SF 0 "register_operand" "=&x")
(if_then_else:SF (match_operator 1 "sse_comparison_operator"
[(match_operand:SF 4 "register_operand" "0")
(match_operand:SF 5 "nonimmediate_operand" "xm")])
@@ -16655,7 +16672,7 @@
"#")
(define_insn "*sse_movsfcc_const0_2"
- [(set (match_operand:SF 0 "register_operand" "=x")
+ [(set (match_operand:SF 0 "register_operand" "=&x")
(if_then_else:SF (match_operator 1 "sse_comparison_operator"
[(match_operand:SF 4 "register_operand" "0")
(match_operand:SF 5 "nonimmediate_operand" "xm")])
@@ -16665,7 +16682,7 @@
"#")
(define_insn "*sse_movsfcc_const0_3"
- [(set (match_operand:SF 0 "register_operand" "=x")
+ [(set (match_operand:SF 0 "register_operand" "=&x")
(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
[(match_operand:SF 4 "nonimmediate_operand" "xm")
(match_operand:SF 5 "register_operand" "0")])
@@ -16675,7 +16692,7 @@
"#")
(define_insn "*sse_movsfcc_const0_4"
- [(set (match_operand:SF 0 "register_operand" "=x")
+ [(set (match_operand:SF 0 "register_operand" "=&x")
(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
[(match_operand:SF 4 "nonimmediate_operand" "xm")
(match_operand:SF 5 "register_operand" "0")])
@@ -16685,42 +16702,42 @@
"#")
(define_insn "*sse_movdfcc_const0_1"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (if_then_else:SF (match_operator 1 "sse_comparison_operator"
- [(match_operand:SF 4 "register_operand" "0")
- (match_operand:SF 5 "nonimmediate_operand" "xm")])
- (match_operand:SF 2 "register_operand" "x")
- (match_operand:SF 3 "const0_operand" "X")))]
+ [(set (match_operand:DF 0 "register_operand" "=&Y")
+ (if_then_else:DF (match_operator 1 "sse_comparison_operator"
+ [(match_operand:DF 4 "register_operand" "0")
+ (match_operand:DF 5 "nonimmediate_operand" "Ym")])
+ (match_operand:DF 2 "register_operand" "Y")
+ (match_operand:DF 3 "const0_operand" "X")))]
"TARGET_SSE2"
"#")
(define_insn "*sse_movdfcc_const0_2"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (if_then_else:SF (match_operator 1 "sse_comparison_operator"
- [(match_operand:SF 4 "register_operand" "0")
- (match_operand:SF 5 "nonimmediate_operand" "xm")])
- (match_operand:SF 2 "const0_operand" "X")
- (match_operand:SF 3 "register_operand" "x")))]
+ [(set (match_operand:DF 0 "register_operand" "=&Y")
+ (if_then_else:DF (match_operator 1 "sse_comparison_operator"
+ [(match_operand:DF 4 "register_operand" "0")
+ (match_operand:DF 5 "nonimmediate_operand" "Ym")])
+ (match_operand:DF 2 "const0_operand" "X")
+ (match_operand:DF 3 "register_operand" "Y")))]
"TARGET_SSE2"
"#")
(define_insn "*sse_movdfcc_const0_3"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
- [(match_operand:SF 4 "nonimmediate_operand" "xm")
- (match_operand:SF 5 "register_operand" "0")])
- (match_operand:SF 2 "register_operand" "x")
- (match_operand:SF 3 "const0_operand" "X")))]
+ [(set (match_operand:DF 0 "register_operand" "=&Y")
+ (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
+ [(match_operand:DF 4 "nonimmediate_operand" "Ym")
+ (match_operand:DF 5 "register_operand" "0")])
+ (match_operand:DF 2 "register_operand" "Y")
+ (match_operand:DF 3 "const0_operand" "X")))]
"TARGET_SSE2"
"#")
(define_insn "*sse_movdfcc_const0_4"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
- [(match_operand:SF 4 "nonimmediate_operand" "xm")
- (match_operand:SF 5 "register_operand" "0")])
- (match_operand:SF 2 "const0_operand" "X")
- (match_operand:SF 3 "register_operand" "x")))]
+ [(set (match_operand:DF 0 "register_operand" "=&Y")
+ (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
+ [(match_operand:DF 4 "nonimmediate_operand" "Ym")
+ (match_operand:DF 5 "register_operand" "0")])
+ (match_operand:DF 2 "const0_operand" "X")
+ (match_operand:DF 3 "register_operand" "Y")))]
"TARGET_SSE2"
"#")
@@ -19766,7 +19783,7 @@
[(set_attr "type" "mmx")])
(define_expand "prefetch"
- [(prefetch (match_operand:SI 0 "address_operand" "")
+ [(prefetch (match_operand 0 "address_operand" "")
(match_operand:SI 1 "const_int_operand" "")
(match_operand:SI 2 "const_int_operand" ""))]
"TARGET_PREFETCH_SSE || TARGET_3DNOW"
@@ -19778,6 +19795,8 @@
abort ();
if (locality < 0 || locality > 3)
abort ();
+ if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
+ abort ();
/* Use 3dNOW prefetch in case we are asking for write prefetch not
suported by SSE counterpart or the SSE prefetch is not available
@@ -19793,7 +19812,26 @@
[(prefetch (match_operand:SI 0 "address_operand" "p")
(const_int 0)
(match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_PREFETCH_SSE"
+ "TARGET_PREFETCH_SSE && !TARGET_64BIT"
+{
+ static const char * const patterns[4] = {
+ "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
+ };
+
+ int locality = INTVAL (operands[1]);
+ if (locality < 0 || locality > 3)
+ abort ();
+
+ return patterns[locality];
+}
+ [(set_attr "type" "sse")
+ (set_attr "memory" "none")])
+
+(define_insn "*prefetch_sse_rex"
+ [(prefetch (match_operand:DI 0 "address_operand" "p")
+ (const_int 0)
+ (match_operand:SI 1 "const_int_operand" ""))]
+ "TARGET_PREFETCH_SSE && TARGET_64BIT"
{
static const char * const patterns[4] = {
"prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
@@ -19811,7 +19849,21 @@
[(prefetch (match_operand:SI 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n")
(const_int 3))]
- "TARGET_3DNOW"
+ "TARGET_3DNOW && !TARGET_64BIT"
+{
+ if (INTVAL (operands[1]) == 0)
+ return "prefetch\t%a0";
+ else
+ return "prefetchw\t%a0";
+}
+ [(set_attr "type" "mmx")
+ (set_attr "memory" "none")])
+
+(define_insn "*prefetch_3dnow_rex"
+ [(prefetch (match_operand:DI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (const_int 3))]
+ "TARGET_3DNOW && TARGET_64BIT"
{
if (INTVAL (operands[1]) == 0)
return "prefetch\t%a0";
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 22:30:41 +0000