diff options
Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index cb5dd10abc2..ef06b4596ab 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -163,6 +163,11 @@ (define_attr "empty" "no,yes" (const_string "no")) +;; True iff this insn must be the first insn of an instruction group. +;; This is true for the alloc instruction, and will also be true of others +;; when we have full intrinsics support. + +(define_attr "first_insn" "no,yes" (const_string "no")) ;; DFA descriptions of ia64 processors used for insn scheduling and ;; bundling. @@ -2694,7 +2699,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) (use (const_int 1))])) @@ -2751,7 +2756,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 10) @@ -3177,7 +3182,7 @@ [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 6) (const_int 0)) (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) (use (const_int 1))])) @@ -3257,7 +3262,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 10) @@ -3842,7 +3847,7 @@ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 7) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 8) @@ -3920,7 +3925,7 @@ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 6) @@ -5703,7 +5708,8 @@ "" "alloc %0 = ar.pfs, %1, %2, %3, %4" [(set_attr "itanium_class" "syst_m0") - (set_attr "predicable" "no")]) + (set_attr "predicable" "no") + (set_attr "first_insn" "yes")]) ;; Modifies ar.unat (define_expand "gr_spill" |