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Diffstat (limited to 'gcc/config/ia64/ia64.md')
-rw-r--r--gcc/config/ia64/ia64.md150
1 files changed, 26 insertions, 124 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 77b0894e24d..cf746f52b68 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -82,15 +82,12 @@
(UNSPEC_VECT_EXTR 31)
(UNSPEC_LDA 40)
(UNSPEC_LDS 41)
- (UNSPEC_LDS_A 42)
- (UNSPEC_LDSA 43)
- (UNSPEC_LDCCLR 44)
- (UNSPEC_LDCNC 45)
- (UNSPEC_CHKACLR 46)
- (UNSPEC_CHKANC 47)
- (UNSPEC_CHKS 48)
- (UNSPEC_FR_RECIP_APPROX_RES 49)
- (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50)
+ (UNSPEC_LDSA 42)
+ (UNSPEC_LDCCLR 43)
+ (UNSPEC_CHKACLR 45)
+ (UNSPEC_CHKS 47)
+ (UNSPEC_FR_RECIP_APPROX_RES 48)
+ (UNSPEC_FR_SQRT_RECIP_APPROX_RES 49)
])
(define_constants
@@ -188,10 +185,6 @@
(define_attr "control_speculative" "no,yes" (const_string "no"))
(define_attr "check_load" "no,yes" (const_string "no"))
-
-(define_attr "speculable1" "no,yes" (const_string "no"))
-
-(define_attr "speculable2" "no,yes" (const_string "no"))
;; DFA descriptions of ia64 processors used for insn scheduling and
;; bundling.
@@ -241,9 +234,7 @@
ld1%O1 %0 = %1%P1
st1%Q0 %0 = %1%P0
mov %0 = %1"
- [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")])
+ [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
(define_split
[(set (match_operand:BI 0 "register_operand" "")
@@ -282,7 +273,7 @@
operands[1] = op1;
})
-(define_insn "movqi_internal"
+(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
(match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -294,9 +285,7 @@
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
- [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, no, yes,no,no, no, no")])
+ [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
@@ -309,7 +298,7 @@
operands[1] = op1;
})
-(define_insn "movhi_internal"
+(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
(match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -321,9 +310,7 @@
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
- [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, no, yes,no,no, no, no")])
+ [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
@@ -336,7 +323,7 @@
operands[1] = op1;
})
-(define_insn "movsi_internal"
+(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
(match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -353,9 +340,7 @@
mov %0 = %1
mov %0 = %r1"
;; frar_m, toar_m ??? why not frar_i and toar_i
- [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")])
+ [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
@@ -368,7 +353,7 @@
operands[1] = op1;
})
-(define_insn "movdi_internal"
+(define_insn "*movdi_internal"
[(set (match_operand:DI 0 "destination_operand"
"=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
(match_operand:DI 1 "move_operand"
@@ -402,9 +387,7 @@
return alt[which_alternative];
}
- [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")])
+ [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
(define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
(define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
@@ -489,26 +472,6 @@
(XF "ldfe.c.clr %0 = %1%P1")
(TI "ldfp8.c.clr %X0 = %1%P1")])
-(define_mode_attr output_c_nc [
- (BI "ld1.c.nc%O1 %0 = %1%P1")
- (QI "ld1.c.nc%O1 %0 = %1%P1")
- (HI "ld2.c.nc%O1 %0 = %1%P1")
- (SI "ld4.c.nc%O1 %0 = %1%P1")
- (DI
- "@
- ld8.c.nc%O1 %0 = %1%P1
- ldf8.c.nc %0 = %1%P1")
- (SF
- "@
- ldfs.c.nc %0 = %1%P1
- ld4.c.nc%O1 %0 = %1%P1")
- (DF
- "@
- ldfd.c.nc %0 = %1%P1
- ld8.c.nc%O1 %0 = %1%P1")
- (XF "ldfe.c.nc %0 = %1%P1")
- (TI "ldfp8.c.nc %X0 = %1%P1")])
-
(define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
(define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
(define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
@@ -567,15 +530,6 @@
(set_attr "data_speculative" "<attr_yes>")
(set_attr "control_speculative" "<attr_yes>")])
-(define_insn "mov<mode>_speculative_a"
- [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
- (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))]
- "ia64_move_ok (operands[0], operands[1])"
- "<output_sa>"
- [(set_attr "itanium_class" "<ld_class>")
- (set_attr "data_speculative" "<attr_yes>")
- (set_attr "control_speculative" "<attr_yes>")])
-
(define_insn "zero_extend<mode>di2_speculative_advanced"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
@@ -585,15 +539,6 @@
(set_attr "data_speculative" "<attr_yes>")
(set_attr "control_speculative" "<attr_yes>")])
-(define_insn "zero_extend<mode>di2_speculative_a"
- [(set (match_operand:DI 0 "gr_register_operand" "=r")
- (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))]
- ""
- "<output_sa>"
- [(set_attr "itanium_class" "<ld_class>")
- (set_attr "data_speculative" "<attr_yes>")
- (set_attr "control_speculative" "<attr_yes>")])
-
(define_insn "mov<mode>_clr"
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
(if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
@@ -604,16 +549,6 @@
[(set_attr "itanium_class" "<ld_class>")
(set_attr "check_load" "<attr_yes>")])
-(define_insn "mov<mode>_nc"
- [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
- (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
- (match_operand:MODE 1 "memory_operand" "<mem_constr>")
- (match_dup 0)))]
- "ia64_move_ok (operands[0], operands[1])"
- "<output_c_nc>"
- [(set_attr "itanium_class" "<ld_class>")
- (set_attr "check_load" "<attr_yes>")])
-
(define_insn "zero_extend<mode>di2_clr"
[(set (match_operand:DI 0 "gr_register_operand" "+r")
(if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
@@ -624,16 +559,6 @@
[(set_attr "itanium_class" "<ld_class>")
(set_attr "check_load" "<attr_yes>")])
-(define_insn "zero_extend<mode>di2_nc"
- [(set (match_operand:DI 0 "gr_register_operand" "+r")
- (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
- (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
- (match_dup 0)))]
- ""
- "<output_c_nc>"
- [(set_attr "itanium_class" "<ld_class>")
- (set_attr "check_load" "<attr_yes>")])
-
(define_insn "advanced_load_check_clr_<mode>"
[(set (pc)
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
@@ -643,15 +568,6 @@
"chk.a.clr %0, %l1"
[(set_attr "itanium_class" "<chka_class>")])
-(define_insn "advanced_load_check_nc_<mode>"
- [(set (pc)
- (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0))
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- ""
- "chk.a.clr %0, %l1"
- [(set_attr "itanium_class" "<chka_class>")])
-
(define_insn "speculation_check_<mode>"
[(set (pc)
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
@@ -947,7 +863,7 @@
operands[1] = op1;
})
-(define_insn_and_split "movti_internal"
+(define_insn_and_split "*movti_internal"
[(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
(match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -963,9 +879,7 @@
ia64_split_tmode_move (operands);
DONE;
}
- [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, no, yes, no, no")])
+ [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])
;; Floating Point Moves
;;
@@ -983,7 +897,7 @@
operands[1] = op1;
})
-(define_insn "movsf_internal"
+(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -996,9 +910,7 @@
mov %0 = %1
ld4%O1 %0 = %1%P1
st4%Q0 %0 = %1%P0"
- [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")])
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
@@ -1011,7 +923,7 @@
operands[1] = op1;
})
-(define_insn "movdf_internal"
+(define_insn "*movdf_internal"
[(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -1024,9 +936,7 @@
mov %0 = %1
ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0"
- [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")])
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word if the variable winds up in GRs.
@@ -1041,7 +951,7 @@
;; ??? There's no easy way to mind volatile acquire/release semantics.
-(define_insn "movxf_internal"
+(define_insn "*movxf_internal"
[(set (match_operand:XF 0 "destination_operand" "=f,f, m")
(match_operand:XF 1 "general_operand" "fG,m,fG"))]
"ia64_move_ok (operands[0], operands[1])"
@@ -1049,9 +959,7 @@
mov %0 = %F1
ldfe %0 = %1%P1
stfe %0 = %F1%P0"
- [(set_attr "itanium_class" "fmisc,fld,stf")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes,no")])
+ [(set_attr "itanium_class" "fmisc,fld,stf")])
;; Same as for movxf, but for RFmode.
(define_expand "movrf"
@@ -1141,9 +1049,7 @@
"@
zxt1 %0 = %1
ld1%O1 %0 = %1%P1"
- [(set_attr "itanium_class" "xtd,ld")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes")])
+ [(set_attr "itanium_class" "xtd,ld")])
(define_insn "zero_extendhidi2"
[(set (match_operand:DI 0 "gr_register_operand" "=r,r")
@@ -1152,9 +1058,7 @@
"@
zxt2 %0 = %1
ld2%O1 %0 = %1%P1"
- [(set_attr "itanium_class" "xtd,ld")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes")])
+ [(set_attr "itanium_class" "xtd,ld")])
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
@@ -1165,9 +1069,7 @@
addp4 %0 = %1, r0
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1"
- [(set_attr "itanium_class" "ialu,ld,fmisc")
- (set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes,no")])
+ [(set_attr "itanium_class" "ialu,ld,fmisc")])
;; Convert between floating point types of different sizes.
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 18:49:40 +0000