diff options
Diffstat (limited to 'gcc/config/m68hc11/m68hc11.md')
| -rw-r--r-- | gcc/config/m68hc11/m68hc11.md | 938 |
1 files changed, 654 insertions, 284 deletions
diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md index 4cd495aad37..b7b8fe38d90 100644 --- a/gcc/config/m68hc11/m68hc11.md +++ b/gcc/config/m68hc11/m68hc11.md @@ -115,6 +115,24 @@ ;; Such split pattern must also be valid when z_replacement_completed == 2 ;; because flow/cse is not aware that D is composed of {a, b}. ;; +;; o Split patterns that generate a (mem:QI (symbol_reg _.dx)) to access +;; the high part of a soft register must be expanded after z_replacement +;; pass. +;; +;;--------------------------------------------------------------------------- +;; Constants + +(define_constants [ + ;; Register numbers + (X_REGNUM 0) ; Index X register + (D_REGNUM 1) ; Data register + (Y_REGNUM 2) ; Index Y register + (SP_REGNUM 3) ; Stack pointer + (PC_REGNUM 4) ; Program counter + (A_REGNUM 5) ; A (high part of D) + (B_REGNUM 6) ; B (low part of D) + (CC_REGNUM 7) ; Condition code register +]) ;;-------------------------------------------------------------------- ;;- Test @@ -156,7 +174,7 @@ "" "* { - if (D_REG_P (operands[0])) + if (D_REG_P (operands[0]) && !TARGET_M6812) return \"std\\t%t0\"; else return \"cp%0\\t#0\"; @@ -189,11 +207,11 @@ (define_insn "tstqi_1" [(set (cc0) - (match_operand:QI 0 "tst_operand" "d,m,*A,!u"))] + (match_operand:QI 0 "tst_operand" "m,d,*A,!u"))] "" "@ - tstb tst\\t%0 + tstb # tst\\t%b0") @@ -222,10 +240,10 @@ (use (match_operand:HI 1 "hard_reg_operand" "dxy")) (use (reg:HI 11))] "z_replacement_completed == 2" - [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 1)) + [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1)) (set (match_dup 1) (match_dup 2)) (set (cc0) (match_dup 0)) - (set (match_dup 1) (mem:HI (post_inc:HI (reg:HI 3))))] + (set (match_dup 1) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))] "operands[2] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);") @@ -313,10 +331,10 @@ (use (match_operand:HI 2 "hard_reg_operand" "dxy")) (use (reg:HI 11))] "z_replacement_completed == 2" - [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2)) + [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2)) (set (match_dup 2) (match_dup 3)) (set (cc0) (compare (match_dup 0) (match_dup 1))) - (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI 3))))] + (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))] "operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);") ;; @@ -330,12 +348,12 @@ (compare (match_operand:QI 0 "hard_addr_reg_operand" "xy") (match_operand:QI 1 "cmp_operand" "uimA")))] "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode" - [(parallel [(set (reg:HI 1) (match_dup 3)) - (set (match_dup 3) (reg:HI 1))]) + [(parallel [(set (reg:HI D_REGNUM) (match_dup 3)) + (set (match_dup 3) (reg:HI D_REGNUM))]) (set (cc0) - (compare (reg:QI 1) (match_dup 1))) - (parallel [(set (reg:HI 1) (match_dup 3)) - (set (match_dup 3) (reg:HI 1))])] + (compare (reg:QI D_REGNUM) (match_dup 1))) + (parallel [(set (reg:HI D_REGNUM) (match_dup 3)) + (set (match_dup 3) (reg:HI D_REGNUM))])] "operands[3] = gen_rtx (REG, HImode, REGNO (operands[0]));") (define_split @@ -365,10 +383,91 @@ DONE; }") +(define_insn "bitcmpqi" + [(set (cc0) + (and:QI (match_operand:QI 0 "tst_operand" "d,d,d") + (match_operand:QI 1 "cmp_operand" "im,*A,u")))] + "" + "@ + bitb\\t%1 + # + bitb\\t%1") + +(define_insn "bitcmpqi_z_used" + [(set (cc0) + (and:QI (match_operand:QI 0 "tst_operand" "d") + (match_operand:QI 1 "cmp_operand" "m"))) + (use (match_operand:HI 2 "hard_reg_operand" "xy")) + (use (reg:HI 11))] + "" + "#") + +(define_split /* "bitcmpqi_z_used" */ + [(set (cc0) + (and:QI (match_operand:QI 0 "tst_operand" "d") + (match_operand:QI 1 "cmp_operand" "m"))) + (use (match_operand:HI 2 "hard_reg_operand" "xy")) + (use (reg:HI 11))] + "z_replacement_completed == 2" + [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2)) + (set (match_dup 2) (match_dup 3)) + (set (cc0) (and:QI (match_dup 0) (match_dup 1))) + (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI 3))))] + "operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);") + +(define_insn "bitcmphi" + [(set (cc0) + (and:HI (match_operand:HI 0 "tst_operand" "d") + (match_operand:HI 1 "const_int_operand" "i")))] + "(INTVAL (operands[1]) & 0x0ff) == 0 + || (INTVAL (operands[1]) & 0x0ff00) == 0" + "* +{ + if ((INTVAL (operands[1]) & 0x0ff) == 0) + return \"bita\\t%h1\"; + else + return \"bitb\\t%1\"; +}") + +(define_insn "bitcmpqi_12" + [(set (cc0) + (zero_extract (match_operand:HI 0 "tst_operand" "d") + (match_operand:HI 1 "const_int_operand" "i") + (match_operand:HI 2 "const_int_operand" "i")))] + "(unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 8 + || (((unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 16) + && (unsigned) INTVAL (operands[2]) >= 8)" + "* +{ + rtx ops[1]; + int mask; + int startpos = INTVAL (operands[2]); + int bitsize = INTVAL (operands[1]); + + if (startpos >= 8) + { + startpos -= 8; + mask = (1 << (startpos + bitsize)) - 1; + mask &= ~((1 << startpos) - 1); + + ops[0] = GEN_INT (mask); + output_asm_insn (\"bita\\t%0\", ops); + } + else + { + mask = (1 << (startpos + bitsize)) - 1; + mask &= ~((1 << startpos) - 1); + + ops[0] = GEN_INT (mask); + output_asm_insn (\"bitb\\t%0\", ops); + } + return \"\"; +}") + (define_insn "cmpqi_1" [(set (cc0) (compare (match_operand:QI 0 "tst_operand" "d,d,*x*y,*x*y") - (match_operand:QI 1 "cmp_operand" "im,?u,?u,?dim*x*y")))] + (match_operand:QI 1 "cmp_operand" "im,!u,!u,?dim*x*y")))] "" "@ cmpb\\t%1 @@ -392,10 +491,10 @@ (use (match_operand:HI 2 "hard_reg_operand" "dxy")) (use (reg:HI 11))] "z_replacement_completed == 2" - [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2)) + [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2)) (set (match_dup 2) (match_dup 3)) (set (cc0) (compare (match_dup 0) (match_dup 1))) - (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI 3))))] + (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))] "operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);") (define_expand "cmpdf" @@ -432,40 +531,40 @@ ;; description but not for GCC optimization passes. ;; (define_insn "movstrictsi" - [(set (strict_low_part (match_operand:SI 0 "non_push_operand" "+um,+D,+D")) + [(set (strict_low_part (match_operand:SI 0 "non_push_operand" "+um,D,D")) (match_operand:SI 1 "general_operand" "D,Dim,uD"))] "" "#") (define_split - [(set (strict_low_part (match_operand:SI 0 "non_push_operand" "+um,+D,+D")) + [(set (strict_low_part (match_operand:SI 0 "non_push_operand" "+um,D,D")) (match_operand:SI 1 "general_operand" "D,Dim,u"))] "z_replacement_completed == 2" [(set (match_dup 0) (match_dup 1))] "") (define_insn "movstricthi" - [(set (strict_low_part (match_operand:HI 0 "non_push_operand" "+um,+d,+d")) - (match_operand:HI 1 "general_operand" "d,dim,u"))] + [(set (strict_low_part (match_operand:HI 0 "non_push_operand" "+um,dA,dA")) + (match_operand:HI 1 "general_operand" "dA,dAim,u"))] "" "#") (define_split - [(set (strict_low_part (match_operand:HI 0 "non_push_operand" "+um,+d,+d")) - (match_operand:HI 1 "general_operand" "d,dim,u"))] + [(set (strict_low_part (match_operand:HI 0 "non_push_operand" "+um,dA,dA")) + (match_operand:HI 1 "general_operand" "dA,dAim,u"))] "z_replacement_completed == 2" [(set (match_dup 0) (match_dup 1))] "") (define_insn "movstrictqi" - [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,+!d")) - (match_operand:QI 1 "general_operand" "d,imu"))] + [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,!dA")) + (match_operand:QI 1 "general_operand" "d,imudA"))] "" "#") (define_split - [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,+d,+d")) - (match_operand:QI 1 "general_operand" "d,dim,u"))] + [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,dA")) + (match_operand:QI 1 "general_operand" "d,imudA"))] "z_replacement_completed == 2" [(set (match_dup 0) (match_dup 1))] "") @@ -703,11 +802,11 @@ "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode && !reg_mentioned_p (operands[0], operands[1]) && !D_REG_P (operands[1])" - [(parallel [(set (reg:HI 1) (match_dup 2)) - (set (match_dup 2) (reg:HI 1))]) - (set (reg:QI 1) (match_dup 1)) - (parallel [(set (reg:HI 1) (match_dup 2)) - (set (match_dup 2) (reg:HI 1))])] + [(parallel [(set (reg:HI D_REGNUM) (match_dup 2)) + (set (match_dup 2) (reg:HI D_REGNUM))]) + (set (reg:QI D_REGNUM) (match_dup 1)) + (parallel [(set (reg:HI D_REGNUM) (match_dup 2)) + (set (match_dup 2) (reg:HI D_REGNUM))])] "operands[2] = gen_rtx (REG, HImode, REGNO (operands[0]));") ;; @@ -719,11 +818,11 @@ "z_replacement_completed == 2 && GET_MODE (operands[1]) == QImode && !reg_mentioned_p (operands[1], operands[0]) && !D_REG_P (operands[0])" - [(parallel [(set (reg:HI 1) (match_dup 2)) - (set (match_dup 2) (reg:HI 1))]) - (set (match_dup 0) (reg:QI 1)) - (parallel [(set (reg:HI 1) (match_dup 2)) - (set (match_dup 2) (reg:HI 1))])] + [(parallel [(set (reg:HI D_REGNUM) (match_dup 2)) + (set (match_dup 2) (reg:HI D_REGNUM))]) + (set (match_dup 0) (reg:QI D_REGNUM)) + (parallel [(set (reg:HI D_REGNUM) (match_dup 2)) + (set (match_dup 2) (reg:HI D_REGNUM))])] "operands[2] = gen_rtx (REG, HImode, REGNO (operands[1]));") (define_insn "*movqi2_push" @@ -1048,15 +1147,11 @@ [(set (match_operand:SI 0 "non_push_operand" "=mu") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dxy")))] "reload_completed && !X_REG_P (operands[0])" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (const_int 0)) - (set (match_dup 5) (const_int 0))] + [(set (match_dup 2) (zero_extend:HI (match_dup 1))) + (set (match_dup 3) (const_int 0))] " operands[2] = m68hc11_gen_lowpart (HImode, operands[0]); - operands[3] = gen_rtx (REG, HImode, REGNO (operands[1])); - operands[4] = m68hc11_gen_lowpart (HImode, operands[0]); - operands[4] = m68hc11_gen_highpart (QImode, operands[4]); - operands[5] = m68hc11_gen_highpart (HImode, operands[0]);") + operands[3] = m68hc11_gen_highpart (HImode, operands[0]);") (define_split [(set (match_operand:SI 0 "hard_reg_operand" "=D") @@ -1178,6 +1273,20 @@ rtx ops[3]; int need_tst = 0; + /* The 68HC12 has a sign-extension instruction. Use it when the + destination is the register (X,D). First sign-extend the low + part and fill X with the sign-extension of the high part. */ + if (TARGET_M6812 && X_REG_P (operands[0])) + { + if (!D_REG_P (operands[1])) + { + ops[0] = gen_rtx (REG, QImode, HARD_D_REGNUM); + ops[1] = operands[1]; + m68hc11_gen_movqi (insn, ops); + } + return \"sex\\tb,d\\n\\tsex\\ta,x\"; + } + ops[2] = gen_label_rtx (); if (X_REG_P (operands[1])) @@ -1273,6 +1382,16 @@ ops[0] = gen_label_rtx (); if (D_REG_P (operands[0])) { + if (TARGET_M6812) + { + if (!D_REG_P (operands[1])) + { + ops[0] = gen_rtx (REG, QImode, HARD_D_REGNUM); + ops[1] = operands[1]; + m68hc11_gen_movqi (insn, ops); + } + return \"sex\\tb,d\"; + } output_asm_insn (\"clra\", operands); if (H_REG_P (operands[1])) { @@ -1320,25 +1439,23 @@ [(set (match_operand:SI 0 "register_operand" "=D") (sign_extend:SI (match_operand:HI 1 "register_operand" "A")))] "reload_completed && (Y_REG_P (operands[1]) || Z_REG_P (operands[1]))" - [(set (reg:HI 1) (match_dup 1)) - (set (match_dup 0) (sign_extend:SI (reg:HI 1)))] + [(set (reg:HI D_REGNUM) (match_dup 1)) + (set (match_dup 0) (sign_extend:SI (reg:HI D_REGNUM)))] "") (define_insn "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=D,D") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "dm,!uA")))] + [(set (match_operand:SI 0 "register_operand" "=D,D,D") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,!r,0")))] "" "* { extern rtx ix_reg; - rtx ops[1]; + rtx ops[2]; int x_reg_used; if (Y_REG_P (operands[1])) return \"#\"; - ops[0] = gen_label_rtx (); - if (X_REG_P (operands[1])) { output_asm_insn (\"xgdx\", operands); @@ -1351,9 +1468,29 @@ x_reg_used = reg_mentioned_p (ix_reg, operands[1]); if (x_reg_used) { - output_asm_insn (\"ldd\\t%1\", operands); + ops[0] = gen_rtx (REG, HImode, HARD_D_REGNUM); + ops[1] = operands[1]; + m68hc11_gen_movhi (insn, ops); } } + + CC_STATUS_INIT; + if (TARGET_M6812 && 0) + { + /* This sequence of code is larger than the one for 68HC11. + Don't use it; keep it for documentation. */ + if (!D_REG_P (operands[1]) && !x_reg_used) + { + ops[0] = gen_rtx (REG, HImode, HARD_D_REGNUM); + ops[1] = operands[1]; + m68hc11_gen_movhi (insn, ops); + } + output_asm_insn (\"sex\\ta,x\", operands); + output_asm_insn (\"xgdx\", operands); + output_asm_insn (\"sex\\ta,d\", operands); + return \"xgdx\"; + } + output_asm_insn (\"ldx\\t#0\", operands); if (D_REG_P (operands[1]) || x_reg_used) { @@ -1361,18 +1498,107 @@ } else { - output_asm_insn (\"ldd\\t%1\", operands); + ops[0] = gen_rtx (REG, HImode, HARD_D_REGNUM); + ops[1] = operands[1]; + m68hc11_gen_movhi (insn, ops); } + + ops[0] = gen_label_rtx (); output_asm_insn (\"bpl\\t%l0\", ops); output_asm_insn (\"dex\", operands); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[0])); - CC_STATUS_INIT; return \"\"; }") ;;-------------------------------------------------------------------- +;;- Min and Max instructions (68HC12). +;;-------------------------------------------------------------------- +(define_insn "uminqi3" + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m") + (umin:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") + (match_operand:QI 2 "general_operand" "m,d")))] + "TARGET_M6812" + "* +{ + /* Flags are set according to (sub:QI (operand 1) (operand2)). + The mina/minm use A as the source or destination. This is the + high part of D. There is no way to express that in the pattern + so we must use 'exg a,b' to put the operand in the good register. */ + CC_STATUS_INIT; + if (D_REG_P (operands[0])) + { + return \"exg\\ta,b\\n\\tmina\\t%2\\n\\texg\\ta,b\"; + } + else + { + return \"exg\\ta,b\\n\\tminm\\t%0\\n\\texg\\ta,b\"; + } +}") + +(define_insn "umaxqi3" + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m") + (umax:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") + (match_operand:QI 2 "general_operand" "m,d")))] + "TARGET_M6812" + "* +{ + /* Flags are set according to (sub:QI (operand 1) (operand2)). + The maxa/maxm use A as the source or destination. This is the + high part of D. There is no way to express that in the pattern + so we must use 'exg a,b' to put the operand in the good register. */ + CC_STATUS_INIT; + if (D_REG_P (operands[0])) + { + return \"exg\\ta,b\\n\\tmaxa\\t%2\\n\\texg\\ta,b\"; + } + else + { + return \"exg\\ta,b\\n\\tmaxm\\t%0\\n\\texg\\ta,b\"; + } +}") + +(define_insn "uminhi3" + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m") + (umin:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") + (match_operand:HI 2 "general_operand" "m,d")))] + "TARGET_M6812" + "* +{ + /* Flags are set according to (sub:HI (operand 1) (operand2)). */ + CC_STATUS_INIT; + if (D_REG_P (operands[0])) + { + return \"emind\\t%2\"; + } + else + { + return \"eminm\\t%0\"; + } +}") + +(define_insn "umaxhi3" + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m") + (umax:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") + (match_operand:HI 2 "general_operand" "m,d")))] + "TARGET_M6812" + "* +{ + /* Flags are set according to (sub:HI (operand 1) (operand2)). */ + CC_STATUS_INIT; + if (D_REG_P (operands[0])) + { + return \"emaxd\\t%2\"; + } + else + { + return \"emaxm\\t%0\"; + } +}") + + +;;-------------------------------------------------------------------- ;;- Add instructions. ;;-------------------------------------------------------------------- ;; 64-bit: Use a library call because what GCC generates is huge. @@ -1409,13 +1635,13 @@ (match_dup 0))) (clobber (match_scratch:HI 1 "=X"))] "reload_completed && z_replacement_completed == 2" - [(set (reg:HI 1) (ashift:HI (reg:HI 1) (const_int 1))) - (parallel [(set (reg:HI 1) (reg:HI 0)) - (set (reg:HI 0) (reg:HI 1))]) - (set (reg:QI 6) (rotate:QI (reg:QI 6) (reg:QI 7))) - (set (reg:QI 5) (rotate:QI (reg:QI 5) (reg:QI 7))) - (parallel [(set (reg:HI 1) (reg:HI 0)) - (set (reg:HI 0) (reg:HI 1))])] + [(set (reg:HI D_REGNUM) (ashift:HI (reg:HI D_REGNUM) (const_int 1))) + (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))]) + (set (reg:QI B_REGNUM) (rotate:QI (reg:QI B_REGNUM) (reg:QI CC_REGNUM))) + (set (reg:QI A_REGNUM) (rotate:QI (reg:QI A_REGNUM) (reg:QI CC_REGNUM))) + (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))])] "") @@ -1472,9 +1698,9 @@ (match_operand:SI 2 "memory_operand" "m,m"))) (clobber (match_scratch:HI 3 "=X,X"))] "reload_completed" - [(set (reg:HI 1) (zero_extend:HI (match_dup 1))) + [(set (reg:HI D_REGNUM) (zero_extend:HI (match_dup 1))) (parallel [(set (match_dup 0) - (plus:SI (zero_extend:SI (reg:HI 1)) (match_dup 2))) + (plus:SI (zero_extend:SI (reg:HI D_REGNUM)) (match_dup 2))) (clobber (match_dup 3))])] "") @@ -1550,9 +1776,9 @@ }") (define_insn "*addsi3" - [(set (match_operand:SI 0 "non_push_operand" "=m,D,!u,D,!D") + [(set (match_operand:SI 0 "non_push_operand" "=m,D,!u,?D,D") (plus:SI (match_operand:SI 1 "non_push_operand" "%0,0,0,0,0") - (match_operand:SI 2 "general_operand" "ML,i,L,?miu,!D"))) + (match_operand:SI 2 "general_operand" "ML,i,ML,?D,?miu"))) (clobber (match_scratch:HI 3 "=d,X,d,X,X"))] "" "* @@ -1652,14 +1878,26 @@ }") (define_split - [(set (match_operand:SI 0 "register_operand" "=D") - (plus:SI (match_operand:SI 1 "register_operand" "%0") + [(set (match_operand:SI 0 "register_operand" "=D,u") + (plus:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "const_int_operand" ""))) - (clobber (match_scratch:HI 3 "=X"))] + (clobber (match_scratch:HI 3 "=X,d"))] "reload_completed && z_replacement_completed == 2 && ((INTVAL (operands[2]) & 0x0FFFF) == 0)" - [(set (reg:HI 0) (plus:HI (reg:HI 0) (match_dup 3)))] - "operands[3] = m68hc11_gen_highpart (HImode, operands[2]);") + [(set (match_dup 5) (match_dup 6)) + (set (reg:HI 0) (plus:HI (reg:HI 0) (match_dup 4))) + (set (match_dup 6) (match_dup 5))] + "operands[4] = m68hc11_gen_highpart (HImode, operands[2]); + if (X_REG_P (operands[0])) + { + operands[5] = operands[6] = gen_rtx (REG, HImode, HARD_D_REGNUM); + } + else + { + operands[6] = m68hc11_gen_highpart (HImode, operands[1]); + operands[5] = operands[3]; + } + ") (define_split [(set (match_operand:SI 0 "register_operand" "=D") @@ -1669,13 +1907,13 @@ "reload_completed && z_replacement_completed == 2 && (GET_CODE (operands[2]) != CONST_INT || (!(INTVAL (operands[2]) >= -65536 && INTVAL (operands[2]) <= 65535)))" - [(set (reg:HI 1) (plus:HI (reg:HI 1) (match_dup 3))) - (parallel [(set (reg:HI 1) (reg:HI 0)) - (set (reg:HI 0) (reg:HI 1))]) - (set (reg:QI 6) (plus:QI (plus:QI (reg:QI 7) (reg:QI 6)) (match_dup 4))) - (set (reg:QI 5) (plus:QI (plus:QI (reg:QI 7) (reg:QI 5)) (match_dup 5))) - (parallel [(set (reg:HI 1) (reg:HI 0)) - (set (reg:HI 0) (reg:HI 1))])] + [(set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 3))) + (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))]) + (set (reg:QI B_REGNUM) (plus:QI (plus:QI (reg:QI CC_REGNUM) (reg:QI B_REGNUM)) (match_dup 4))) + (set (reg:QI A_REGNUM) (plus:QI (plus:QI (reg:QI CC_REGNUM) (reg:QI A_REGNUM)) (match_dup 5))) + (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))])] "operands[3] = m68hc11_gen_lowpart (HImode, operands[2]); operands[4] = m68hc11_gen_highpart (HImode, operands[2]); operands[5] = m68hc11_gen_highpart (QImode, operands[4]); @@ -1689,7 +1927,7 @@ [(set (match_operand:HI 0 "register_operand" "=x") (plus:HI (plus:HI (match_operand:HI 1 "register_operand" "0") (const_int 0)) - (reg:HI 7)))] + (reg:HI CC_REGNUM)))] "" "* { @@ -1746,25 +1984,39 @@ "") (define_insn "*addhi3_68hc12" - [(set (match_operand:HI 0 "register_operand" "=d,A*w,A*w") - (plus:HI (match_operand:HI 1 "register_operand" "%0,0,Aw") - (match_operand:HI 2 "general_operand" "imA*wu,id,id")))] + [(set (match_operand:HI 0 "register_operand" "=*d,A*w,A*w,A") + (plus:HI (match_operand:HI 1 "register_operand" "%0,0,Aw,0") + (match_operand:HI 2 "general_operand" "imA*wu,id,id,!muA")))] "TARGET_M6812" "* { int val; const char* insn_code; + if (which_alternative >= 3) + { + if (A_REG_P (operands[2])) + { + CC_STATUS_INIT; + output_asm_insn (\"xgd%2\", operands); + output_asm_insn (\"lea%0 d,%0\", operands); + return \"xgd%2\"; + } + return \"#\"; + } + if (D_REG_P (operands[0])) { if (X_REG_P (operands[2])) { + m68hc11_notice_keep_cc (operands[0]); output_asm_insn (\"xgdx\", operands); output_asm_insn (\"leax\\td,%2\", operands); return \"xgdx\"; } else if (Y_REG_P (operands[2])) { + m68hc11_notice_keep_cc (operands[0]); output_asm_insn (\"xgdy\", operands); output_asm_insn (\"leay\\td,%2\", operands); return \"xgdy\"; @@ -1784,7 +2036,7 @@ if (val != -1 || val != 1 || !rtx_equal_p (operands[0], operands[1])) { - cc_status = cc_prev_status; + m68hc11_notice_keep_cc (operands[0]); switch (REGNO (operands[0])) { case HARD_X_REGNUM: @@ -1922,9 +2174,9 @@ "") (define_insn "*addhi3" - [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d,!w") - (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0") - (match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w,i")))] + [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d") + (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0") + (match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w")))] "TARGET_M6811" "* { @@ -2110,7 +2362,7 @@ ;; (define_insn "*adcq" [(set (match_operand:QI 0 "register_operand" "=q") - (plus:QI (plus:QI (reg:QI 7) + (plus:QI (plus:QI (reg:QI CC_REGNUM) (match_operand:QI 1 "register_operand" "%0")) (match_operand:QI 2 "general_operand" "ium")))] "" @@ -2201,13 +2453,13 @@ (clobber (match_scratch:HI 3 "=X"))] "reload_completed && z_replacement_completed == 2 && X_REG_P (operands[1])" - [(set (reg:HI 1) (minus:HI (reg:HI 1) (match_dup 3))) - (parallel [(set (reg:HI 0) (reg:HI 1)) - (set (reg:HI 1) (reg:HI 0))]) - (set (reg:QI 6) (minus:QI (minus:QI (reg:QI 7) (reg:QI 6)) (match_dup 4))) - (set (reg:QI 5) (minus:QI (minus:QI (reg:QI 7) (reg:QI 5)) (match_dup 5))) - (parallel [(set (reg:HI 0) (reg:HI 1)) - (set (reg:HI 1) (reg:HI 0))])] + [(set (reg:HI D_REGNUM) (minus:HI (reg:HI D_REGNUM) (match_dup 3))) + (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))]) + (set (reg:QI B_REGNUM) (minus:QI (minus:QI (reg:QI CC_REGNUM) (reg:QI B_REGNUM)) (match_dup 4))) + (set (reg:QI A_REGNUM) (minus:QI (minus:QI (reg:QI CC_REGNUM) (reg:QI A_REGNUM)) (match_dup 5))) + (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))])] "operands[3] = m68hc11_gen_lowpart (HImode, operands[2]); operands[4] = m68hc11_gen_highpart (HImode, operands[2]); operands[5] = m68hc11_gen_highpart (QImode, operands[4]); @@ -2220,13 +2472,13 @@ (clobber (match_scratch:HI 3 "=X"))] "reload_completed && z_replacement_completed == 2 && X_REG_P (operands[2])" - [(set (reg:HI 1) (minus:HI (reg:HI 1) (match_dup 3))) - (parallel [(set (reg:HI 0) (reg:HI 1)) - (set (reg:HI 1) (reg:HI 0))]) - (set (reg:QI 6) (minus:QI (minus:QI (reg:QI 7) (reg:QI 6)) (match_dup 4))) - (set (reg:QI 5) (minus:QI (minus:QI (reg:QI 7) (reg:QI 5)) (match_dup 5))) - (parallel [(set (reg:HI 0) (reg:HI 1)) - (set (reg:HI 1) (reg:HI 0))]) + [(set (reg:HI D_REGNUM) (minus:HI (reg:HI D_REGNUM) (match_dup 3))) + (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))]) + (set (reg:QI B_REGNUM) (minus:QI (minus:QI (reg:QI CC_REGNUM) (reg:QI B_REGNUM)) (match_dup 4))) + (set (reg:QI A_REGNUM) (minus:QI (minus:QI (reg:QI CC_REGNUM) (reg:QI A_REGNUM)) (match_dup 5))) + (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))]) (set (reg:SI 0) (neg:SI (reg:SI 0)))] "operands[3] = m68hc11_gen_lowpart (HImode, operands[1]); operands[4] = m68hc11_gen_highpart (HImode, operands[1]); @@ -2346,9 +2598,9 @@ }") (define_insn "subqi3" - [(set (match_operand:QI 0 "hard_reg_operand" "=dq*x*y") - (minus:QI (match_operand:QI 1 "hard_reg_operand" "0") - (match_operand:QI 2 "general_operand" "uim*x*y*d")))] + [(set (match_operand:QI 0 "hard_reg_operand" "=dq,!*x*y") + (minus:QI (match_operand:QI 1 "hard_reg_operand" "0,0") + (match_operand:QI 2 "general_operand" "uim*A*d,uim*A*d")))] "" "* { @@ -2365,7 +2617,7 @@ ;; (define_insn "*subcq" [(set (match_operand:QI 0 "register_operand" "=q") - (minus:QI (minus:QI (reg:QI 7) + (minus:QI (minus:QI (reg:QI CC_REGNUM) (match_operand:QI 1 "register_operand" "0")) (match_operand:QI 2 "general_operand" "ium")))] "" @@ -2378,11 +2630,28 @@ ;; 32 and 64-bit multiply are handled by the library ;; -(define_insn "mulhi3" +(define_expand "mulsi3" + [(set (match_operand:SI 0 "nonimmediate_operand" "") + (mult:SI (match_operand:SI 1 "general_operand" "") + (match_operand:SI 2 "general_operand" "")))] + "" + "m68hc11_emit_libcall (\"__mulsi3\", MULT, SImode, SImode, 3, operands); + DONE;") + +(define_expand "mulhi3" + [(parallel [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (match_operand:HI 1 "register_operand" "") + (match_operand:HI 2 "register_operand" ""))) + (clobber (match_scratch:HI 3 ""))])] + "" + "") + +(define_insn "mulhi3_m68hc11" [(set (match_operand:HI 0 "register_operand" "=d") (mult:HI (match_operand:HI 1 "register_operand" "%0") - (match_operand:HI 2 "register_operand" "x")))] - "" + (match_operand:HI 2 "register_operand" "x"))) + (clobber (match_scratch:HI 3 "=X"))] + "TARGET_M6811" "* { CC_STATUS_INIT; @@ -2390,6 +2659,59 @@ return \"jsr\\t___mulhi3\"; }") +(define_insn "mulhi3_m68hc12" + [(set (match_operand:HI 0 "register_operand" "=d,d") + (mult:HI (match_operand:HI 1 "register_operand" "%0,0") + (match_operand:HI 2 "register_operand" "y,x"))) + (clobber (match_scratch:HI 3 "=2,2"))] + "TARGET_M6812" + "* +{ + CC_STATUS_INIT; + if (X_REG_P (operands[2])) + return \"exg\\tx,y\\n\\temul\\n\\texg\\tx,y\"; + else + return \"emul\"; +}") + +(define_insn "umulhisi3" + [(set (match_operand:SI 0 "register_operand" "=D,D") + (mult:SI (zero_extend:SI + (match_operand:HI 1 "register_operand" "%d,d")) + (zero_extend:SI + (match_operand:HI 2 "register_operand" "y,x")))) + (clobber (match_scratch:HI 3 "=2,X"))] + "TARGET_M6812" + "* +{ + if (X_REG_P (operands [2])) + output_asm_insn (\"exg\\tx,y\", operands); + + /* Can't use the carry after that; other flags are ok when testing + the 32-bit result. */ + cc_status.flags |= CC_NO_OVERFLOW; + return \"emul\\n\\texg\\tx,y\"; +}") + +(define_insn "mulhisi3" + [(set (match_operand:SI 0 "register_operand" "=D,D") + (mult:SI (sign_extend:SI + (match_operand:HI 1 "register_operand" "%d,d")) + (sign_extend:SI + (match_operand:HI 2 "register_operand" "y,x")))) + (clobber (match_scratch:HI 3 "=2,X"))] + "TARGET_M6812" + "* +{ + if (X_REG_P (operands [2])) + output_asm_insn (\"exg\\tx,y\", operands); + + /* Can't use the carry after that; other flags are ok when testing + the 32-bit result. */ + cc_status.flags |= CC_NO_OVERFLOW; + return \"emuls\\n\\texg\\tx,y\"; +}") + (define_insn "umulqihi3" [(set (match_operand:HI 0 "register_operand" "=d") (mult:HI (zero_extend:HI @@ -2501,7 +2823,7 @@ [(set (match_operand:HI 0 "register_operand" "=d,d") (div:HI (match_operand:HI 1 "register_operand" "0,0") (match_operand:HI 2 "general_operand" "A,ium"))) - (set (match_operand:HI 3 "register_operand" "=x,x") + (set (match_operand:HI 3 "register_operand" "=&x,&x") (mod:HI (match_dup 1) (match_dup 2)))] "" "* @@ -2518,8 +2840,16 @@ output_asm_insn (\"ldx\\t%2\", operands); } } - CC_STATUS_INIT; - return \"bsr\\t__divmodhi4\"; + if (TARGET_M6812) + { + /* Flags are ok after that. */ + return \"idivs\\n\\txgdx\"; + } + else + { + CC_STATUS_INIT; + return \"bsr\\t__divmodhi4\"; + } }") (define_insn "udivmodhi4" @@ -2927,10 +3257,10 @@ (match_operand:QI 1 "general_operand" "dxy,imu")) (match_operand:SI 2 "general_operand" "imuD,imuD")]))] "z_replacement_completed == 2" - [(set (reg:QI 5) (match_dup 4)) - (set (reg:QI 1) (match_dup 7)) - (set (reg:QI 6) (match_op_dup 3 [(reg:QI 6) (match_dup 5)])) - (set (reg:HI 0) (match_dup 6))] + [(set (reg:QI A_REGNUM) (match_dup 4)) + (set (reg:QI D_REGNUM) (match_dup 7)) + (set (reg:QI B_REGNUM) (match_op_dup 3 [(reg:QI B_REGNUM) (match_dup 5)])) + (set (reg:HI X_REGNUM) (match_dup 6))] "PUT_MODE (operands[3], QImode); if (X_REG_P (operands[2])) { @@ -2957,9 +3287,9 @@ (match_operand:HI 1 "general_operand" "dA,imu")) (match_operand:SI 2 "general_operand" "imuD,imuD")]))] "reload_completed" - [(set (reg:HI 1) (match_dup 4)) - (set (reg:HI 1) (match_op_dup 3 [(reg:HI 1) (match_dup 5)])) - (set (reg:HI 0) (match_dup 6))] + [(set (reg:HI D_REGNUM) (match_dup 4)) + (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)])) + (set (reg:HI X_REGNUM) (match_dup 6))] "PUT_MODE (operands[3], HImode); if (X_REG_P (operands[2])) { @@ -3003,9 +3333,9 @@ (match_operand:QI 1 "general_operand" "imud")) (match_operand:HI 2 "general_operand" "dimu")]))] "z_replacement_completed == 2" - [(set (reg:QI 6) (match_dup 6)) - (set (reg:QI 5) (match_dup 4)) - (set (reg:QI 6) (match_op_dup 3 [(reg:QI 6) (match_dup 5)]))] + [(set (reg:QI B_REGNUM) (match_dup 6)) + (set (reg:QI A_REGNUM) (match_dup 4)) + (set (reg:QI B_REGNUM) (match_op_dup 3 [(reg:QI B_REGNUM) (match_dup 5)]))] " PUT_MODE (operands[3], QImode); if (D_REG_P (operands[2])) @@ -3034,8 +3364,8 @@ (match_operand:HI 2 "general_operand" "dimu") (const_int 8))]))] "z_replacement_completed == 2" - [(set (reg:QI 6) (match_dup 5)) - (set (reg:QI 5) (match_dup 4))] + [(set (reg:QI A_REGNUM) (match_dup 4)) + (set (reg:QI B_REGNUM) (match_dup 5))] " if (GET_CODE (operands[3]) == AND) { @@ -3060,7 +3390,7 @@ [(set (match_operand:SI 0 "register_operand" "=D,D") (match_operator:SI 3 "m68hc11_logical_operator" [(lshiftrt:SI - (match_operand:SI 1 "general_operand" "uim,!D") + (match_operand:SI 1 "general_operand" "uim,?D") (const_int 16)) (match_operand:SI 2 "general_operand" "uim,0")]))] "" @@ -3070,13 +3400,13 @@ [(set (match_operand:SI 0 "register_operand" "=D,D") (match_operator:SI 3 "m68hc11_logical_operator" [(lshiftrt:SI - (match_operand:SI 1 "general_operand" "uim,!D") + (match_operand:SI 1 "general_operand" "uim,?D") (const_int 16)) (match_operand:SI 2 "general_operand" "uim,0")]))] "reload_completed" - [(set (reg:HI 1) (match_dup 4)) - (set (reg:HI 1) (match_op_dup 3 [(reg:HI 1) (match_dup 5)])) - (set (reg:HI 0) (match_dup 6))] + [(set (reg:HI D_REGNUM) (match_dup 4)) + (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)])) + (set (reg:HI X_REGNUM) (match_dup 6))] "operands[5] = m68hc11_gen_highpart (HImode, operands[1]); if (X_REG_P (operands[2])) { @@ -3096,7 +3426,7 @@ [(set (match_operand:SI 0 "register_operand" "=D,D") (match_operator:SI 3 "m68hc11_logical_operator" [(ashift:SI - (match_operand:SI 1 "general_operand" "uim,!D") + (match_operand:SI 1 "general_operand" "uim,?D") (const_int 16)) (match_operand:SI 2 "general_operand" "0,0")]))] "" @@ -3106,15 +3436,15 @@ [(set (match_operand:SI 0 "register_operand" "=D,D") (match_operator:SI 3 "m68hc11_logical_operator" [(ashift:SI - (match_operand:SI 1 "general_operand" "uim,!D") + (match_operand:SI 1 "general_operand" "uim,?D") (const_int 16)) (match_operand:SI 2 "general_operand" "0,0")]))] "z_replacement_completed == 2" - [(parallel [(set (reg:HI 1) (reg:HI 0)) - (set (reg:HI 0) (reg:HI 1))]) - (set (reg:HI 1) (match_op_dup 3 [(reg:HI 1) (match_dup 4)])) - (parallel [(set (reg:HI 1) (reg:HI 0)) - (set (reg:HI 0) (reg:HI 1))])] + [(parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 4)])) + (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))])] "operands[4] = m68hc11_gen_lowpart (HImode, operands[1]); PUT_MODE (operands[3], HImode);") @@ -3177,17 +3507,19 @@ /* If we are adding a small constant to X or Y, it's better to use one or several inx/iny instructions. */ && !(GET_CODE (operands[3]) == PLUS - && (TARGET_M6812 + && ((TARGET_M6812 + && (immediate_operand (operands[2], HImode) + || hard_reg_operand (operands[2], HImode))) || (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= -4 && INTVAL (operands[2]) <= 4)))" [(set (match_dup 4) (match_dup 5)) (set (match_dup 8) (match_dup 7)) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:HI 1) (match_op_dup 3 [(reg:HI 1) (match_dup 6)])) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 6)])) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] " /* Save the operand2 in a temporary location and use it. */ if (H_REG_P (operands[2]) @@ -3224,16 +3556,18 @@ /* If we are adding a small constant to X or Y, it's better to use one or several inx/iny instructions. */ && !(GET_CODE (operands[3]) == PLUS - && (TARGET_M6812 + && ((TARGET_M6812 + && (immediate_operand (operands[2], HImode) + || hard_reg_operand (operands[2], HImode))) || (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= -4 && INTVAL (operands[2]) <= 4)))" [(set (match_dup 0) (match_dup 1)) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:HI 1) (match_op_dup 3 [(reg:HI 1) (match_dup 2)])) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 2)])) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] " ") @@ -3283,11 +3617,11 @@ [(match_operand 1 "general_operand" "uim*d*A")]))] "z_replacement_completed == 2" [(set (match_dup 4) (match_dup 5)) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:HI 1) (match_op_dup 2 [(match_dup 3)])) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) (match_op_dup 2 [(match_dup 3)])) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] " { if ((H_REG_P (operands[1]) @@ -3331,11 +3665,11 @@ && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == -1))" [(set (match_dup 5) (match_dup 6)) - (parallel [(set (reg:HI 1) (match_dup 4)) - (set (match_dup 4) (reg:HI 1))]) - (set (reg:QI 1) (match_op_dup 3 [(reg:QI 1) (match_dup 7)])) - (parallel [(set (reg:HI 1) (match_dup 4)) - (set (match_dup 4) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 4)) + (set (match_dup 4) (reg:HI D_REGNUM))]) + (set (reg:QI D_REGNUM) (match_op_dup 3 [(reg:QI D_REGNUM) (match_dup 7)])) + (parallel [(set (reg:HI D_REGNUM) (match_dup 4)) + (set (match_dup 4) (reg:HI D_REGNUM))])] "operands[4] = gen_rtx (REG, HImode, REGNO (operands[0])); /* For the second operand is a hard register or if the address @@ -3410,11 +3744,11 @@ [(match_operand:QI 1 "general_operand" "uim*d*x*y")]))] "z_replacement_completed == 2" [(set (match_dup 4) (match_dup 5)) - (parallel [(set (reg:HI 1) (match_dup 3)) - (set (match_dup 3) (reg:HI 1))]) - (set (reg:QI 1) (match_op_dup 2 [(match_dup 6)])) - (parallel [(set (reg:HI 1) (match_dup 3)) - (set (match_dup 3) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 3)) + (set (match_dup 3) (reg:HI D_REGNUM))]) + (set (reg:QI D_REGNUM) (match_op_dup 2 [(match_dup 6)])) + (parallel [(set (reg:HI D_REGNUM) (match_dup 3)) + (set (match_dup 3) (reg:HI D_REGNUM))])] " { operands[3] = gen_rtx (REG, HImode, REGNO (operands[0])); @@ -3530,12 +3864,12 @@ (not:SI (match_operand:SI 1 "non_push_operand" "0")))] "z_replacement_completed == 2 && (!D_REG_P (operands[0]) || (optimize && optimize_size == 0))" - [(set (reg:HI 1) (not:HI (reg:HI 1))) - (parallel [(set (reg:HI 0) (reg:HI 1)) - (set (reg:HI 1) (reg:HI 0))]) - (set (reg:HI 1) (not:HI (reg:HI 1))) - (parallel [(set (reg:HI 0) (reg:HI 1)) - (set (reg:HI 1) (reg:HI 0))])] + [(set (reg:HI D_REGNUM) (not:HI (reg:HI D_REGNUM))) + (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))]) + (set (reg:HI D_REGNUM) (not:HI (reg:HI D_REGNUM))) + (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))])] " { /* The result pattern only works for D register. @@ -3576,7 +3910,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u") (ashift:DI (match_operand:DI 1 "general_operand" "umi,umi,umi") (const_int 32))) - (clobber (match_scratch:HI 2 "=A,d,d"))] + (clobber (match_scratch:HI 2 "=&A,d,d"))] "" "#") @@ -3584,7 +3918,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=<,um") (ashift:DI (match_operand:DI 1 "general_operand" "umi,umi") (const_int 32))) - (clobber (match_scratch:HI 2 "=A,d"))] + (clobber (match_scratch:HI 2 "=&A,d"))] "reload_completed" [(const_int 0)] "/* Move the lowpart in the highpart first in case the shift @@ -3623,15 +3957,15 @@ (set (match_dup 4) (match_dup 2)) (set (match_dup 2) (match_dup 5)) - (set (match_dup 2) (rotate:HI (match_dup 2) (reg:HI 7))) + (set (match_dup 2) (rotate:HI (match_dup 2) (reg:HI CC_REGNUM))) (set (match_dup 6) (match_dup 2)) (set (match_dup 2) (match_dup 7)) - (set (match_dup 2) (rotate:HI (match_dup 2) (reg:HI 7))) + (set (match_dup 2) (rotate:HI (match_dup 2) (reg:HI CC_REGNUM))) (set (match_dup 8) (match_dup 2)) (set (match_dup 2) (match_dup 9)) - (set (match_dup 2) (rotate:HI (match_dup 2) (reg:HI 7))) + (set (match_dup 2) (rotate:HI (match_dup 2) (reg:HI CC_REGNUM))) (set (match_dup 10) (match_dup 2))] "operands[3] = m68hc11_gen_lowpart (SImode, operands[1]); operands[5] = m68hc11_gen_highpart (HImode, operands[3]); @@ -3663,8 +3997,8 @@ (const_int 16)) (match_operand:SI 2 "general_operand" "0")))] "z_replacement_completed == 2" - [(set (reg:HI 1) (plus:HI (reg:HI 1) (match_dup 3))) - (set (reg:HI 0) (plus:HI (plus:HI (reg:HI 0) (const_int 0)) (reg:HI 7)))] + [(set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 3))) + (set (reg:HI X_REGNUM) (plus:HI (plus:HI (reg:HI X_REGNUM) (const_int 0)) (reg:HI CC_REGNUM)))] "operands[3] = m68hc11_gen_highpart (HImode, operands[1]);") (define_insn "addsi_ashift16" @@ -3685,7 +4019,7 @@ (match_operand:SI 1 "general_operand" "0"))) (clobber (match_scratch:HI 3 "=X"))] "0 && reload_completed && z_replacement_completed == 2" - [(set (reg:HI 0) (plus:HI (reg:HI 0) (match_dup 4)))] + [(set (reg:HI X_REGNUM) (plus:HI (reg:HI X_REGNUM) (match_dup 4)))] " { operands[4] = m68hc11_gen_lowpart (HImode, operands[2]); @@ -3705,8 +4039,8 @@ (const_int 65535)) (match_operand:SI 2 "general_operand" "0")))] "z_replacement_completed == 2" - [(set (reg:HI 1) (plus:HI (reg:HI 1) (match_dup 3))) - (set (reg:HI 0) (plus:HI (plus:HI (reg:HI 0) (const_int 0)) (reg:HI 7)))] + [(set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 3))) + (set (reg:HI X_REGNUM) (plus:HI (plus:HI (reg:HI X_REGNUM) (const_int 0)) (reg:HI CC_REGNUM)))] "operands[3] = m68hc11_gen_lowpart (HImode, operands[1]);") ;; @@ -3766,8 +4100,8 @@ (const_int 16))) (clobber (match_scratch:HI 2 "=X"))] "reload_completed" - [(set (reg:HI 0) (match_dup 1)) - (set (reg:HI 1) (const_int 0))] + [(set (reg:HI X_REGNUM) (match_dup 1)) + (set (reg:HI D_REGNUM) (const_int 0))] "") (define_insn "*ashlsi3_const1" @@ -3910,7 +4244,7 @@ (define_insn "*ashlhi3_2" [(set (match_operand:HI 0 "register_operand" "=d") (ashift:HI (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "register_operand" "x"))) + (match_operand:HI 2 "register_operand" "+x"))) (clobber (match_dup 2))] "" "* @@ -3919,10 +4253,10 @@ return \"bsr\\t___lshlhi3\"; }") -(define_insn "" +(define_insn "*ashlhi3" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashift:HI (match_dup 0) - (match_operand:HI 1 "register_operand" "x"))) + (match_operand:HI 1 "register_operand" "+x"))) (clobber (match_dup 1))] "" "* @@ -4177,9 +4511,9 @@ output_asm_insn (\"rolb\", operands); output_asm_insn (\"rola\", operands); output_asm_insn (\"tab\", operands); - output_asm_insn (\"anda\\t#1\", operands); + output_asm_insn (\"anda\\t#0\", operands); output_asm_insn (\"bcc\\t%l0\", ops); - output_asm_insn (\"oraa\\t#0xFE\", ops); + output_asm_insn (\"coma\", ops); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[0])); @@ -4199,7 +4533,7 @@ (define_insn "*ashrhi3" [(set (match_operand:HI 0 "register_operand" "=d,x") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "register_operand" "x,d"))) + (match_operand:HI 2 "register_operand" "+x,+d"))) (clobber (match_dup 2))] "" "* @@ -4355,7 +4689,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u") (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi,umi") (const_int 32))) - (clobber (match_scratch:HI 2 "=A,d,d"))] + (clobber (match_scratch:HI 2 "=&A,d,d"))] "" "#") @@ -4363,7 +4697,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=<,um") (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi") (const_int 32))) - (clobber (match_scratch:HI 2 "=A,d"))] + (clobber (match_scratch:HI 2 "=&A,d"))] "reload_completed" [(const_int 0)] "m68hc11_split_move (m68hc11_gen_lowpart (SImode, operands[0]), @@ -4387,14 +4721,14 @@ (match_operand:DI 2 "const_int_operand" ""))) (clobber (match_scratch:HI 3 "=d"))] "z_replacement_completed && INTVAL (operands[2]) >= 56" - [(set (reg:QI 1) (match_dup 9)) - (set (reg:QI 1) (lshiftrt:QI (reg:QI 1) (match_dup 8))) - (set (reg:HI 1) (zero_extend:HI (reg:QI 1))) - (set (match_dup 4) (reg:HI 1)) - (set (reg:QI 1) (const_int 0)) - (set (match_dup 5) (reg:HI 1)) - (set (match_dup 6) (reg:HI 1)) - (set (match_dup 7) (reg:HI 1))] + [(set (reg:QI D_REGNUM) (match_dup 9)) + (set (reg:QI D_REGNUM) (lshiftrt:QI (reg:QI D_REGNUM) (match_dup 8))) + (set (reg:HI D_REGNUM) (zero_extend:HI (reg:QI D_REGNUM))) + (set (match_dup 4) (reg:HI D_REGNUM)) + (set (reg:QI D_REGNUM) (const_int 0)) + (set (match_dup 5) (reg:HI D_REGNUM)) + (set (match_dup 6) (reg:HI D_REGNUM)) + (set (match_dup 7) (reg:HI D_REGNUM))] "operands[8] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 56); operands[4] = m68hc11_gen_lowpart (SImode, operands[0]); operands[5] = m68hc11_gen_highpart (HImode, operands[4]); @@ -4415,13 +4749,13 @@ (clobber (match_scratch:HI 3 "=d"))] "z_replacement_completed && INTVAL (operands[2]) >= 48 && INTVAL (operands[2]) < 56" - [(set (reg:HI 1) (match_dup 9)) - (set (reg:HI 1) (lshiftrt:HI (reg:HI 1) (match_dup 8))) - (set (match_dup 4) (reg:HI 1)) - (set (reg:HI 1) (const_int 0)) - (set (match_dup 5) (reg:HI 1)) - (set (match_dup 6) (reg:HI 1)) - (set (match_dup 7) (reg:HI 1))] + [(set (reg:HI D_REGNUM) (match_dup 9)) + (set (reg:HI D_REGNUM) (lshiftrt:HI (reg:HI D_REGNUM) (match_dup 8))) + (set (match_dup 4) (reg:HI D_REGNUM)) + (set (reg:HI D_REGNUM) (const_int 0)) + (set (match_dup 5) (reg:HI D_REGNUM)) + (set (match_dup 6) (reg:HI D_REGNUM)) + (set (match_dup 7) (reg:HI D_REGNUM))] "operands[8] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 48); operands[4] = m68hc11_gen_lowpart (SImode, operands[0]); operands[5] = m68hc11_gen_highpart (HImode, operands[4]); @@ -4452,15 +4786,15 @@ (set (match_dup 4) (match_dup 2)) (set (match_dup 2) (match_dup 5)) - (set (match_dup 2) (rotatert:HI (match_dup 2) (reg:HI 7))) + (set (match_dup 2) (rotatert:HI (match_dup 2) (reg:HI CC_REGNUM))) (set (match_dup 6) (match_dup 2)) (set (match_dup 2) (match_dup 7)) - (set (match_dup 2) (rotatert:HI (match_dup 2) (reg:HI 7))) + (set (match_dup 2) (rotatert:HI (match_dup 2) (reg:HI CC_REGNUM))) (set (match_dup 8) (match_dup 2)) (set (match_dup 2) (match_dup 9)) - (set (match_dup 2) (rotatert:HI (match_dup 2) (reg:HI 7))) + (set (match_dup 2) (rotatert:HI (match_dup 2) (reg:HI CC_REGNUM))) (set (match_dup 10) (match_dup 2))] "operands[3] = m68hc11_gen_highpart (SImode, operands[1]); operands[5] = m68hc11_gen_lowpart (HImode, operands[3]); @@ -4508,8 +4842,10 @@ (const_int 16))) (clobber (match_scratch:HI 2 "=X,X,X,X"))] "" - "# + "@ + # xgdx\\n\\tldx\\t#0 + # #") (define_insn "*lshrsi3_const1" @@ -4637,7 +4973,7 @@ return \"lsrd\"; CC_STATUS_INIT; - return \"lsr\\t%h0\\n\\trol\\t%b0\"; + return \"lsr\\t%h0\\n\\tror\\t%b0\"; }") (define_insn "lshrhi3_const" @@ -4727,7 +5063,7 @@ (define_insn "*lshrhi3" [(set (match_operand:HI 0 "register_operand" "=d,x") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "register_operand" "x,d"))) + (match_operand:HI 2 "register_operand" "+x,+d"))) (clobber (match_dup 2))] "" "* @@ -4751,13 +5087,13 @@ "") (define_insn "*lshrqi3_const1" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*q,!*A") + [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d,!u,!*q,!*A") (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0") (const_int 1)))] "" "@ - lsrb lsr\\t%b0 + lsrb lsr\\t%b0 lsr%0 #") @@ -4868,7 +5204,7 @@ (define_insn "*rotlqi3_with_carry" [(set (match_operand:QI 0 "register_operand" "=d,!q") (rotate:QI (match_operand:QI 1 "register_operand" "0,0") - (reg:QI 7)))] + (reg:QI CC_REGNUM)))] "" "* { @@ -4881,7 +5217,7 @@ (define_insn "*rotlhi3_with_carry" [(set (match_operand:HI 0 "register_operand" "=d") (rotate:HI (match_operand:HI 1 "register_operand" "0") - (reg:HI 7)))] + (reg:HI CC_REGNUM)))] "" "* { @@ -4892,7 +5228,7 @@ (define_insn "*rotrhi3_with_carry" [(set (match_operand:HI 0 "register_operand" "=d") (rotatert:HI (match_operand:HI 1 "register_operand" "0") - (reg:HI 7)))] + (reg:HI CC_REGNUM)))] "" "* { @@ -5103,6 +5439,78 @@ DONE; }") +;; +;; Test and branch instructions for 68HC12 for EQ and NE. +;; 'z' must not appear in the constraints because the z replacement +;; pass does not know how to restore the replacement register. +;; +(define_insn "*tbeq" + [(set (pc) + (if_then_else (eq (match_operand:HI 0 "register_operand" "dxy") + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc)))] + "TARGET_M6812" + "* +{ + /* If the flags are already set correctly, use 'bne/beq' which are + smaller and a little bit faster. This happens quite often due + to reloading of operands[0]. In that case, flags are set correctly + due to the load instruction. */ + if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0])) + return \"beq\\t%l1\"; + else + return \"tbeq\\t%0,%l1\"; +}") + +(define_insn "*tbne" + [(set (pc) + (if_then_else (ne (match_operand:HI 0 "register_operand" "dxy") + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc)))] + "TARGET_M6812" + "* +{ + if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0])) + return \"bne\\t%l1\"; + else + return \"tbne\\t%0,%l1\"; +}") + +;; +;; Test and branch with 8-bit register. Register must be B (or A). +;; +(define_insn "*tbeq8" + [(set (pc) + (if_then_else (eq (match_operand:QI 0 "register_operand" "d") + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc)))] + "TARGET_M6812" + "* +{ + if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0])) + return \"beq\\t%l1\"; + else + return \"tbeq\\tb,%l1\"; +}") + +(define_insn "*tbne8" + [(set (pc) + (if_then_else (ne (match_operand:QI 0 "register_operand" "d") + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc)))] + "TARGET_M6812" + "* +{ + if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0])) + return \"bne\\t%l1\"; + else + return \"tbne\\tb,%l1\"; +}") + (define_insn "*beq" [(set (pc) (if_then_else (eq (cc0) @@ -5328,7 +5736,7 @@ ;; ;;- Call a function that returns no value. (define_insn "call" - [(call (match_operand:QI 0 "memory_operand" "mAi") + [(call (match_operand:QI 0 "memory_operand" "m") (match_operand:SI 1 "general_operand" "g"))] ;; Operand 1 not really used on the m68hc11. "" @@ -5349,7 +5757,7 @@ (define_insn "call_value" [(set (match_operand 0 "" "=g") - (call (match_operand:QI 1 "general_operand" "mAi") + (call (match_operand:QI 1 "memory_operand" "m") (match_operand:SI 2 "general_operand" "g")))] "" "* @@ -5478,7 +5886,7 @@ (define_insn "*return_16bit" [(return) - (use (reg:HI 1))] + (use (reg:HI D_REGNUM))] "reload_completed && m68hc11_total_frame_size () == 0" "* { @@ -5545,13 +5953,13 @@ (define_peephole [(set (match_operand:HI 0 "hard_reg_operand" "xy") (match_operand:HI 1 "const_int_operand" "")) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:HI 1) - (plus (reg:HI 1) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) + (plus (reg:HI D_REGNUM) (match_operand:HI 2 "general_operand" ""))) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] "(INTVAL (operands[1]) & 0x0FF) == 0" "* { @@ -5634,9 +6042,9 @@ ;; (set ...) insn. ;; (define_peephole - [(set (match_operand:HI 0 "hard_reg_operand" "A") (reg:HI 1)) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + [(set (match_operand:HI 0 "hard_reg_operand" "A") (reg:HI D_REGNUM)) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] "find_regno_note (ins1, REG_DEAD, HARD_D_REGNUM)" "* { @@ -5648,10 +6056,10 @@ ;; Same as above but due to some split, there may be a noop set ;; between the two. (define_peephole - [(set (match_operand:HI 0 "hard_reg_operand" "A") (reg:HI 1)) + [(set (match_operand:HI 0 "hard_reg_operand" "A") (reg:HI D_REGNUM)) (set (match_dup 0) (match_dup 0)) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] "find_regno_note (ins1, REG_DEAD, HARD_D_REGNUM)" "* { @@ -5665,9 +6073,9 @@ ;; and we must, at least, setup X/Y with value of D. ;; (define_peephole - [(set (match_operand:HI 0 "hard_reg_operand" "A") (reg:HI 1)) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + [(set (match_operand:HI 0 "hard_reg_operand" "A") (reg:HI D_REGNUM)) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] "" "* { @@ -5685,9 +6093,9 @@ ;;; need to emit anything. Otherwise, we just need an copy of D to X/Y. ;;; (define_peephole - [(parallel [(set (reg:HI 1) (match_operand:HI 0 "hard_reg_operand" "A")) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:HI 1) (match_dup 0))] + [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A")) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) (match_dup 0))] "find_regno_note (insn, REG_DEAD, REGNO (operands[0]))" "* { @@ -5701,9 +6109,9 @@ ;;; need to emit anything. Otherwise, we just need an copy of D to X/Y. ;;; (define_peephole - [(parallel [(set (reg:HI 1) (match_operand:HI 0 "hard_reg_operand" "A")) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:QI 1) (match_operand:QI 1 "hard_reg_operand" "A"))] + [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A")) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:QI D_REGNUM) (match_operand:QI 1 "hard_reg_operand" "A"))] "REGNO (operands[0]) == REGNO (operands[1]) && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))" "* @@ -5718,9 +6126,9 @@ ;;; need to emit anything. Otherwise, we just need a copy of D to X/Y. ;;; (define_peephole - [(parallel [(set (reg:HI 1) (match_operand:HI 0 "hard_reg_operand" "A")) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:HI 1) (match_dup 0))] + [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A")) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:HI D_REGNUM) (match_dup 0))] "" "* { @@ -5738,9 +6146,9 @@ ;;; with the xgdx. ;;; (define_peephole - [(parallel [(set (reg:HI 1) (match_operand:HI 0 "hard_reg_operand" "A")) - (set (match_dup 0) (reg:HI 1))]) - (set (reg:QI 1) (match_operand:QI 1 "hard_reg_operand" "A"))] + [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A")) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (set (reg:QI D_REGNUM) (match_operand:QI 1 "hard_reg_operand" "A"))] "REGNO (operands[0]) == REGNO (operands[1])" "* { @@ -5757,10 +6165,10 @@ ;;; Catch two consecutive xgdx or xgdy, emit nothing. ;;; (define_peephole - [(parallel [(set (reg:HI 1) (match_operand:HI 0 "hard_reg_operand" "A")) - (set (match_dup 0) (reg:HI 1))]) - (parallel [(set (reg:HI 1) (match_dup 0)) - (set (match_dup 0) (reg:HI 1))])] + [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A")) + (set (match_dup 0) (reg:HI D_REGNUM))]) + (parallel [(set (reg:HI D_REGNUM) (match_dup 0)) + (set (match_dup 0) (reg:HI D_REGNUM))])] "" "* { @@ -5770,44 +6178,6 @@ ") (define_peephole - [(set (match_operand:HI 0 "stack_register_operand" "") - (plus:HI (match_dup 0) - (const_int -2))) - (set (match_operand:HI 2 "memory_operand" "m") - (match_operand:HI 3 "stack_register_operand" ""))] - "0 && GET_CODE (operands[2]) == MEM" - "* -{ - rtx ops[2]; - - ops[0] = gen_rtx (MEM, HImode, - gen_rtx (PRE_DEC, HImode, stack_pointer_rtx)); - ops[1] = operands[3]; - m68hc11_gen_movhi (insn, ops); - return \"\"; -} -") - -(define_peephole - [(set (match_operand:HI 0 "hard_reg_operand" "") - (match_operand:HI 1 "memory_operand" "m")) - (set (match_operand:HI 2 "stack_register_operand" "") - (plus:HI (match_dup 2) - (const_int 2)))] - "GET_CODE (operands[1]) == MEM" - "* -{ - rtx ops[2]; - - ops[0] = operands[0]; - ops[1] = gen_rtx (MEM, HImode, - gen_rtx (POST_INC, HImode, stack_pointer_rtx)); - m68hc11_gen_movhi (insn, ops); - return \"\"; -} -") - -(define_peephole [(set (match_operand:HI 0 "hard_reg_operand" "") (match_operand:HI 1 "stack_register_operand" "")) (set (match_operand:HI 2 "hard_reg_operand" "") @@ -5834,7 +6204,7 @@ ;; (define_peephole [(set (match_operand:HI 0 "hard_reg_operand" "dA") (const_int -1)) - (set (match_dup 0) (plus:HI (match_dup 0) (reg:HI 3)))] + (set (match_dup 0) (plus:HI (match_dup 0) (reg:HI SP_REGNUM)))] "TARGET_M6811" "* { |