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-rw-r--r--gcc/config/mcore/mcore.md6
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index 7e74a98e061..895e7aa216a 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -150,7 +150,7 @@
;; ; This is done to allow bit field masks to fold together in combine.
;; ; The reload phase will force the immediate into a register at the
;; ; very end. This helps in some cases, but hurts in others: we'd
-;; ; really like to cse these immediates. However, there is an phase
+;; ; really like to cse these immediates. However, there is a phase
;; ; ordering problem here. cse picks up individual masks and cse's
;; ; those, but not folded masks (cse happens before combine). It's
;; ; not clear what the best solution is because we really want cse
@@ -1896,7 +1896,7 @@
""
"
{
- emit_insn (gen_jump_real (operand0));
+ emit_jump_insn (gen_jump_real (operand0));
DONE;
}
")
@@ -3319,7 +3319,7 @@
""
"*
{
- int op0 = REGNO (operands[0]);
+ unsigned int op0 = REGNO (operands[0]);
if (GET_CODE (operands[3]) == REG)
{