diff options
Diffstat (limited to 'gcc/config/mips/mips.md')
| -rw-r--r-- | gcc/config/mips/mips.md | 53 |
1 files changed, 47 insertions, 6 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 5d58b735503..e8a6b2a8576 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -266,7 +266,7 @@ ;; Attribute describing the processor. This attribute must match exactly ;; with the processor_type enumeration in mips.h. (define_attr "cpu" - "default,4kc,4kp,5kc,20kc,24k,24kx,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000" + "r3000,4kc,4kp,5kc,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000" (const (symbol_ref "mips_tune"))) ;; The type of hardware hazard associated with this instruction. @@ -2818,7 +2818,7 @@ beq\t%2,%.,1b\;\ (define_expand "extzv" [(set (match_operand 0 "register_operand") - (zero_extract (match_operand:QI 1 "memory_operand") + (zero_extract (match_operand 1 "nonimmediate_operand") (match_operand 2 "immediate_operand") (match_operand 3 "immediate_operand")))] "!TARGET_MIPS16" @@ -2827,12 +2827,33 @@ beq\t%2,%.,1b\;\ INTVAL (operands[2]), INTVAL (operands[3]))) DONE; + else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3])) + { + if (GET_MODE (operands[0]) == DImode) + emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], + operands[3])); + else + emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], + operands[3])); + DONE; + } else FAIL; }) +(define_insn "extzv<mode>" + [(set (match_operand:GPR 0 "register_operand" "=d") + (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I") + (match_operand:SI 3 "immediate_operand" "I")))] + "mips_use_ins_ext_p (operands[1], operands[2], operands[3])" + "<d>ext\t%0,%1,%3,%2" + [(set_attr "type" "arith") + (set_attr "mode" "<MODE>")]) + + (define_expand "insv" - [(set (zero_extract (match_operand:QI 0 "memory_operand") + [(set (zero_extract (match_operand 0 "nonimmediate_operand") (match_operand 1 "immediate_operand") (match_operand 2 "immediate_operand")) (match_operand 3 "reg_or_0_operand"))] @@ -2842,10 +2863,30 @@ beq\t%2,%.,1b\;\ INTVAL (operands[1]), INTVAL (operands[2]))) DONE; - else - FAIL; + else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2])) + { + if (GET_MODE (operands[0]) == DImode) + emit_insn (gen_insvdi (operands[0], operands[1], operands[2], + operands[3])); + else + emit_insn (gen_insvsi (operands[0], operands[1], operands[2], + operands[3])); + DONE; + } + else + FAIL; }) +(define_insn "insv<mode>" + [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d") + (match_operand:SI 1 "immediate_operand" "I") + (match_operand:SI 2 "immediate_operand" "I")) + (match_operand:GPR 3 "reg_or_0_operand" "dJ"))] + "mips_use_ins_ext_p (operands[0], operands[1], operands[2])" + "<d>ins\t%0,%z3,%2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "<MODE>")]) + ;; Unaligned word moves generated by the bit field patterns. ;; ;; As far as the rtl is concerned, both the left-part and right-part @@ -5326,7 +5367,7 @@ beq\t%2,%.,1b\;\ ; Thread-Local Storage -; The TLS base pointer is acessed via "rdhwr $v1, $29". No current +; The TLS base pointer is accessed via "rdhwr $v1, $29". No current ; MIPS architecture defines this register, and no current ; implementation provides it; instead, any OS which supports TLS is ; expected to trap and emulate this instruction. rdhwr is part of the |