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Diffstat (limited to 'gcc/config/rs6000/altivec.md')
-rw-r--r--gcc/config/rs6000/altivec.md66
1 files changed, 22 insertions, 44 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 1af96877424..3419e3a7a1c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2042,8 +2042,7 @@
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_insn "altivec_vperm_v8hiv16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v,?wo")
@@ -2055,8 +2054,7 @@
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand")
@@ -2083,8 +2081,7 @@
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand")
@@ -2110,8 +2107,7 @@
"@
vpermr %0,%1,%2,%3
xxpermr %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_insn "altivec_vrfip" ; ceil
[(set (match_operand:V4SF 0 "register_operand" "=v")
@@ -3268,8 +3264,7 @@
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_insn "vperm_v16qiv8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v,?wo")
@@ -3281,8 +3276,7 @@
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_expand "vec_unpacku_hi_v16qi"
@@ -3857,8 +3851,7 @@
(clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P8_VECTOR"
"vclz<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector absolute difference unsigned
(define_expand "vadu<mode>3"
@@ -3884,8 +3877,7 @@
(ctz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P9_VECTOR"
"vctz<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector population count
(define_insn "*p8v_popcount<mode>2"
@@ -3893,8 +3885,7 @@
(popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P8_VECTOR"
"vpopcnt<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector parity
(define_insn "*p9v_parity<mode>2"
@@ -3902,8 +3893,7 @@
(parity:VParity (match_operand:VParity 1 "register_operand" "v")))]
"TARGET_P9_VECTOR"
"vprtyb<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector Gather Bits by Bytes by Doubleword
(define_insn "p8v_vgbbd"
@@ -3912,8 +3902,7 @@
UNSPEC_VGBBD))]
"TARGET_P8_VECTOR"
"vgbbd %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; 128-bit binary integer arithmetic
@@ -3927,8 +3916,7 @@
(match_operand:V1TI 2 "register_operand" "v")))]
"TARGET_VADDUQM"
"vadduqm %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddcuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3937,8 +3925,7 @@
UNSPEC_VADDCUQ))]
"TARGET_VADDUQM"
"vaddcuq %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3946,8 +3933,7 @@
(match_operand:V1TI 2 "register_operand" "v")))]
"TARGET_VADDUQM"
"vsubuqm %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubcuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3956,8 +3942,7 @@
UNSPEC_VSUBCUQ))]
"TARGET_VADDUQM"
"vsubcuq %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddeuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3967,8 +3952,7 @@
UNSPEC_VADDEUQM))]
"TARGET_VADDUQM"
"vaddeuqm %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddecuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3978,8 +3962,7 @@
UNSPEC_VADDECUQ))]
"TARGET_VADDUQM"
"vaddecuq %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubeuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3989,8 +3972,7 @@
UNSPEC_VSUBEUQM))]
"TARGET_VADDUQM"
"vsubeuqm %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubecuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -4000,8 +3982,7 @@
UNSPEC_VSUBECUQ))]
"TARGET_VADDUQM"
"vsubecuq %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; We use V2DI as the output type to simplify converting the permute
;; bits into an integer
@@ -4093,8 +4074,7 @@
(clobber (reg:CCFP CR6_REGNO))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we
;; can use the unordered test for BCD nans and add/subtracts that overflow. An
@@ -4112,8 +4092,7 @@
(clobber (match_scratch:V1TI 0 "=v"))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "*bcd<bcd_add_sub>_test2"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -4130,8 +4109,7 @@
(match_operand:V2DF 4 "zero_constant" "j")))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "darn_32"
[(set (match_operand:SI 0 "register_operand" "=r")
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 15:16:59 +0000