diff options
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 2ede79d9f5c..6a46328fb24 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -388,6 +388,22 @@ "vaddsws %0,%1,%2" [(set_attr "type" "vecsimple")]) +(define_insn "andv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (and:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vand %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "andv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (and:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vand %0,%1,%2" + [(set_attr "type" "vecsimple")]) + (define_insn "andv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") (and:V4SI (match_operand:V4SI 1 "register_operand" "v") @@ -976,6 +992,43 @@ "vnor %0,%1,%2" [(set_attr "type" "vecsimple")]) +(define_insn "one_cmplv16qi2" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (not:V16QI (match_operand:V16QI 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnot %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "one_cmplv8hi2" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (not:V8HI (match_operand:V8HI 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnot %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "one_cmplv4si2" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (not:V4SI (match_operand:V4SI 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnot %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "iorv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (ior:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vor %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "iorv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (ior:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vor %0,%1,%2" + [(set_attr "type" "vecsimple")]) + (define_insn "iorv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") |