diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.c')
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 286 |
1 files changed, 9 insertions, 277 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 197607214ff..d159a9e01fd 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -531,18 +531,8 @@ struct rs6000_reg_addr { enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */ enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */ - enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */ - /* INSNs for fusing addi with loads - or stores for each reg. class. */ - enum insn_code fusion_addi_ld[(int)N_RELOAD_REG]; - enum insn_code fusion_addi_st[(int)N_RELOAD_REG]; - /* INSNs for fusing addis with loads - or stores for each reg. class. */ - enum insn_code fusion_addis_ld[(int)N_RELOAD_REG]; - enum insn_code fusion_addis_st[(int)N_RELOAD_REG]; addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */ bool scalar_in_vmx_p; /* Scalar value can go in VMX. */ - bool fused_toc; /* Mode supports TOC fusion. */ }; static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES]; @@ -2376,7 +2366,6 @@ rs6000_debug_print_mode (ssize_t m) { ssize_t rc; int spaces = 0; - bool fuse_extra_p; fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m)); for (rc = 0; rc < N_RELOAD_REG; rc++) @@ -2385,9 +2374,12 @@ rs6000_debug_print_mode (ssize_t m) if ((reg_addr[m].reload_store != CODE_FOR_nothing) || (reg_addr[m].reload_load != CODE_FOR_nothing)) - fprintf (stderr, " Reload=%c%c", - (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', - (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*'); + { + fprintf (stderr, "%*s Reload=%c%c", spaces, "", + (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', + (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*'); + spaces = 0; + } else spaces += sizeof (" Reload=sl") - 1; @@ -2399,82 +2391,6 @@ rs6000_debug_print_mode (ssize_t m) else spaces += sizeof (" Upper=y") - 1; - fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing) - || reg_addr[m].fused_toc); - if (!fuse_extra_p) - { - for (rc = 0; rc < N_RELOAD_REG; rc++) - { - if (rc != RELOAD_REG_ANY) - { - if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing - || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing - || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing - || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing - || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing) - { - fuse_extra_p = true; - break; - } - } - } - } - - if (fuse_extra_p) - { - fprintf (stderr, "%*s Fuse:", spaces, ""); - spaces = 0; - - for (rc = 0; rc < N_RELOAD_REG; rc++) - { - if (rc != RELOAD_REG_ANY) - { - char load, store; - - if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing) - load = 'l'; - else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing) - load = 'L'; - else - load = '-'; - - if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing) - store = 's'; - else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing) - store = 'S'; - else - store = '-'; - - if (load == '-' && store == '-') - spaces += 5; - else - { - fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "", - reload_reg_map[rc].name[0], load, store); - spaces = 0; - } - } - } - - if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing) - { - fprintf (stderr, "%*sP8gpr", (spaces + 1), ""); - spaces = 0; - } - else - spaces += sizeof (" P8gpr") - 1; - - if (reg_addr[m].fused_toc) - { - fprintf (stderr, "%*sToc", (spaces + 1), ""); - spaces = 0; - } - else - spaces += sizeof (" Toc") - 1; - } - else - spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1; - if (rs6000_vector_unit[m] != VECTOR_NONE || rs6000_vector_mem[m] != VECTOR_NONE) { @@ -2870,9 +2786,6 @@ rs6000_debug_reg_global (void) char options[80]; strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8"); - if (TARGET_TOC_FUSION) - strcat (options, ", toc"); - if (TARGET_P8_FUSION_SIGN) strcat (options, ", sign"); @@ -3540,135 +3453,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } - /* Setup the fusion operations. */ - if (TARGET_P8_FUSION) - { - reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi; - reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi; - reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si; - if (TARGET_64BIT) - reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di; - } - - if (TARGET_P9_FUSION) - { - struct fuse_insns { - enum machine_mode mode; /* mode of the fused type. */ - enum machine_mode pmode; /* pointer mode. */ - enum rs6000_reload_reg_type rtype; /* register type. */ - enum insn_code load; /* load insn. */ - enum insn_code store; /* store insn. */ - }; - - static const struct fuse_insns addis_insns[] = { - { E_SFmode, E_DImode, RELOAD_REG_FPR, - CODE_FOR_fusion_vsx_di_sf_load, - CODE_FOR_fusion_vsx_di_sf_store }, - - { E_SFmode, E_SImode, RELOAD_REG_FPR, - CODE_FOR_fusion_vsx_si_sf_load, - CODE_FOR_fusion_vsx_si_sf_store }, - - { E_DFmode, E_DImode, RELOAD_REG_FPR, - CODE_FOR_fusion_vsx_di_df_load, - CODE_FOR_fusion_vsx_di_df_store }, - - { E_DFmode, E_SImode, RELOAD_REG_FPR, - CODE_FOR_fusion_vsx_si_df_load, - CODE_FOR_fusion_vsx_si_df_store }, - - { E_DImode, E_DImode, RELOAD_REG_FPR, - CODE_FOR_fusion_vsx_di_di_load, - CODE_FOR_fusion_vsx_di_di_store }, - - { E_DImode, E_SImode, RELOAD_REG_FPR, - CODE_FOR_fusion_vsx_si_di_load, - CODE_FOR_fusion_vsx_si_di_store }, - - { E_QImode, E_DImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_di_qi_load, - CODE_FOR_fusion_gpr_di_qi_store }, - - { E_QImode, E_SImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_si_qi_load, - CODE_FOR_fusion_gpr_si_qi_store }, - - { E_HImode, E_DImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_di_hi_load, - CODE_FOR_fusion_gpr_di_hi_store }, - - { E_HImode, E_SImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_si_hi_load, - CODE_FOR_fusion_gpr_si_hi_store }, - - { E_SImode, E_DImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_di_si_load, - CODE_FOR_fusion_gpr_di_si_store }, - - { E_SImode, E_SImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_si_si_load, - CODE_FOR_fusion_gpr_si_si_store }, - - { E_SFmode, E_DImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_di_sf_load, - CODE_FOR_fusion_gpr_di_sf_store }, - - { E_SFmode, E_SImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_si_sf_load, - CODE_FOR_fusion_gpr_si_sf_store }, - - { E_DImode, E_DImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_di_di_load, - CODE_FOR_fusion_gpr_di_di_store }, - - { E_DFmode, E_DImode, RELOAD_REG_GPR, - CODE_FOR_fusion_gpr_di_df_load, - CODE_FOR_fusion_gpr_di_df_store }, - }; - - machine_mode cur_pmode = Pmode; - size_t i; - - for (i = 0; i < ARRAY_SIZE (addis_insns); i++) - { - machine_mode xmode = addis_insns[i].mode; - enum rs6000_reload_reg_type rtype = addis_insns[i].rtype; - - if (addis_insns[i].pmode != cur_pmode) - continue; - - if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT) - continue; - - reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load; - reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store; - - if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR) - { - reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] - = addis_insns[i].load; - reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] - = addis_insns[i].store; - } - } - } - - /* Note which types we support fusing TOC setup plus memory insn. We only do - fused TOCs for medium/large code models. */ - if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64 - && (TARGET_CMODEL != CMODEL_SMALL)) - { - reg_addr[QImode].fused_toc = true; - reg_addr[HImode].fused_toc = true; - reg_addr[SImode].fused_toc = true; - reg_addr[DImode].fused_toc = true; - if (TARGET_HARD_FLOAT) - { - reg_addr[SFmode].fused_toc = true; - reg_addr[DFmode].fused_toc = true; - } - } - /* Precalculate HARD_REGNO_NREGS. */ for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) for (m = 0; m < NUM_MACHINE_MODES; ++m) @@ -4425,7 +4209,7 @@ rs6000_option_override_internal (bool global_init_p) & OPTION_MASK_P8_FUSION); /* Setting additional fusion flags turns on base fusion. */ - if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION)) + if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN) { if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION) { @@ -4433,9 +4217,6 @@ rs6000_option_override_internal (bool global_init_p) error ("%qs requires %qs", "-mpower8-fusion-sign", "-mpower8-fusion"); - if (TARGET_TOC_FUSION) - error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion"); - rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION; } else @@ -4473,28 +4254,6 @@ rs6000_option_override_internal (bool global_init_p) && optimize >= 3) rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN; - /* TOC fusion requires 64-bit and medium/large code model. */ - if (TARGET_TOC_FUSION && !TARGET_POWERPC64) - { - rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION; - if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0) - warning (0, N_("-mtoc-fusion requires 64-bit")); - } - - if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL)) - { - rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION; - if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0) - warning (0, N_("-mtoc-fusion requires medium/large code model")); - } - - /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code - model. */ - if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64 - && (TARGET_CMODEL != CMODEL_SMALL) - && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION)) - rs6000_isa_flags |= OPTION_MASK_TOC_FUSION; - /* ISA 3.0 vector instructions include ISA 2.07. */ if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR) { @@ -9535,9 +9294,6 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) if (legitimate_constant_pool_address_p (x, mode, reg_ok_strict || lra_in_progress)) return 1; - if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC - && XINT (x, 1) == UNSPEC_FUSION_ADDIS) - return 1; } /* For TImode, if we have TImode in VSX registers, only allow register @@ -35880,7 +35636,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true }, { "string", 0, false, true }, - { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true }, { "update", OPTION_MASK_NO_UPDATE, true , true }, { "vsx", OPTION_MASK_VSX, false, true }, #ifdef OPTION_MASK_64BIT @@ -38043,37 +37798,17 @@ emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset, return; } -/* Wrap a TOC address that can be fused to indicate that special fusion - processing is needed. */ - -rtx -fusion_wrap_memory_address (rtx old_mem) -{ - rtx old_addr = XEXP (old_mem, 0); - rtvec v = gen_rtvec (1, old_addr); - rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS); - return replace_equiv_address_nv (old_mem, new_addr, false); -} - /* Given an address, convert it into the addis and load offset parts. Addresses created during the peephole2 process look like: (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL)) - (unspec [(...)] UNSPEC_TOCREL)) - - Addresses created via toc fusion look like: - (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */ + (unspec [(...)] UNSPEC_TOCREL)) */ static void fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo) { rtx hi, lo; - if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS) - { - lo = XVECEXP (addr, 0, 0); - hi = gen_rtx_HIGH (Pmode, lo); - } - else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) + if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) { hi = XEXP (addr, 0); lo = XEXP (addr, 1); @@ -38090,9 +37825,6 @@ fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo) is the logical address that was formed during peephole2: (lo_sum (high) (low-part)) - Or the address is the TOC address that is wrapped before register allocation: - (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS) - The code is complicated, so we call output_asm_insn directly, and just return "". */ |