diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 281 |
1 files changed, 201 insertions, 80 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 29b36d6e4e5..d48acd96811 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -67,7 +67,7 @@ (const_string "integer")) ;; Length (in bytes). -; '(pc)' in the following doesn't include the instruction itself; it is +; '(pc)' in the following doesn't include the instruction itself; it is ; calculated as if the instruction had zero size. (define_attr "length" "" (if_then_else (eq_attr "type" "branch") @@ -1632,7 +1632,7 @@ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }) - + (define_expand "ffssi2" [(set (match_dup 2) (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) @@ -1648,7 +1648,7 @@ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }) - + (define_expand "mulsi3" [(use (match_operand:SI 0 "gpc_reg_operand" "")) (use (match_operand:SI 1 "gpc_reg_operand" "")) @@ -1672,10 +1672,10 @@ "@ {muls|mullw} %0,%1,%2 {muli|mulli} %0,%1,%2" - [(set (attr "type") + [(set (attr "type") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") (const_string "imul3") - (match_operand:SI 2 "short_cint_operand" "") + (match_operand:SI 2 "short_cint_operand" "") (const_string "imul2")] (const_string "imul")))]) @@ -1687,10 +1687,10 @@ "@ {muls|mullw} %0,%1,%2 {muli|mulli} %0,%1,%2" - [(set (attr "type") + [(set (attr "type") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") (const_string "imul3") - (match_operand:SI 2 "short_cint_operand" "") + (match_operand:SI 2 "short_cint_operand" "") (const_string "imul2")] (const_string "imul")))]) @@ -2568,7 +2568,7 @@ (const_int 0)))] "") -;; Split a logical operation that we can't do in one insn into two insns, +;; Split a logical operation that we can't do in one insn into two insns, ;; each of which does one 16-bit part. This is used by combine. (define_split @@ -4686,7 +4686,7 @@ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" [(const_int 0)] " -{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), +{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1], operands[2]); DONE; }") @@ -4879,7 +4879,7 @@ (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && ! HONOR_SIGNED_ZEROS (DFmode)" "{fnms|fnmsub} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -4892,7 +4892,7 @@ [(set_attr "type" "dsqrt")]) ;; The conditional move instructions allow us to perform max and min -;; operations even when +;; operations even when (define_expand "maxdf3" [(set (match_operand:DF 0 "gpc_reg_operand" "") @@ -4920,7 +4920,7 @@ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" [(const_int 0)] " -{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), +{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1], operands[2]); DONE; }") @@ -4991,7 +4991,11 @@ { if (TARGET_POWERPC64) { - rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + /* APPLE LOCAL assign_stack_local_with_alias is used instead of + assign_stack_temp to get better scheduling, at the cost of some + stack space. */ + rtx mem = assign_stack_local_with_alias (DImode, GET_MODE_SIZE (DImode), + GET_MODE_ALIGNMENT (DImode)); rtx t1 = gen_reg_rtx (DImode); rtx t2 = gen_reg_rtx (DImode); emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); @@ -5000,7 +5004,11 @@ operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); - operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); + /* APPLE LOCAL assign_stack_local_with_alias is used instead of + assign_stack_temp to get better scheduling, at the cost of some + stack space. */ + operands[4] = assign_stack_local_with_alias (DFmode, GET_MODE_SIZE (DFmode), + GET_MODE_ALIGNMENT (DFmode)); operands[5] = gen_reg_rtx (DFmode); operands[6] = gen_reg_rtx (SImode); }") @@ -5046,7 +5054,7 @@ tmp = highword; highword = lowword; lowword = tmp; } - emit_insn (gen_xorsi3 (operands[6], operands[1], + emit_insn (gen_xorsi3 (operands[6], operands[1], GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); @@ -5073,7 +5081,11 @@ { if (TARGET_POWERPC64) { - rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + /* APPLE LOCAL assign_stack_local_with_alias is used instead of + assign_stack_temp to get better scheduling, at the cost of some + stack space. */ + rtx mem = assign_stack_local_with_alias (DImode, GET_MODE_SIZE (DImode), + GET_MODE_ALIGNMENT (DImode)); rtx t1 = gen_reg_rtx (DImode); rtx t2 = gen_reg_rtx (DImode); emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, @@ -5083,7 +5095,11 @@ operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); - operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); + /* APPLE LOCAL assign_stack_local_with_alias is used instead of + assign_stack_temp to get better scheduling, at the cost of some + stack space. */ + operands[4] = assign_stack_local_with_alias (DFmode, GET_MODE_SIZE (DFmode), + GET_MODE_ALIGNMENT (DFmode)); operands[5] = gen_reg_rtx (DFmode); }") @@ -5141,7 +5157,11 @@ " { operands[2] = gen_reg_rtx (DImode); - operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + /* APPLE LOCAL assign_stack_local_with_alias is used instead of + assign_stack_temp to get better scheduling, at the cost of some + stack space. */ + operands[3] = assign_stack_local_with_alias (DImode, GET_MODE_SIZE (DImode), + GET_MODE_ALIGNMENT (DImode)); }") (define_insn "*fix_truncdfsi2_internal" @@ -5642,7 +5662,7 @@ (define_insn "*ashrdisi3_noppc64" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 32)) 4))] "TARGET_32BIT && !TARGET_POWERPC64" "* @@ -5652,7 +5672,7 @@ else return \"mr %0,%1\"; }" - [(set_attr "length" "4")]) + [(set_attr "length" "4")]) ;; PowerPC64 DImode operations. @@ -6032,15 +6052,15 @@ (define_expand "ctzdi2" [(set (match_dup 2) (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) - (parallel [(set (match_dup 3) (and:DI (match_dup 1) - (match_dup 2))) + (parallel [(set (match_dup 3) (and:DI (match_dup 1) + (match_dup 2))) (clobber (scratch:CC))]) (set (match_dup 4) (clz:DI (match_dup 3))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (minus:DI (const_int 63) (match_dup 4)))] "TARGET_POWERPC64" { - operands[2] = gen_reg_rtx (DImode); + operands[2] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); }) @@ -6048,15 +6068,15 @@ (define_expand "ffsdi2" [(set (match_dup 2) (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) - (parallel [(set (match_dup 3) (and:DI (match_dup 1) - (match_dup 2))) + (parallel [(set (match_dup 3) (and:DI (match_dup 1) + (match_dup 2))) (clobber (scratch:CC))]) (set (match_dup 4) (clz:DI (match_dup 3))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (minus:DI (const_int 64) (match_dup 4)))] "TARGET_POWERPC64" { - operands[2] = gen_reg_rtx (DImode); + operands[2] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); }) @@ -6656,7 +6676,7 @@ "TARGET_POWERPC64" "sld%I2 %0,%1,%H2" [(set_attr "length" "8")]) - + (define_insn "*ashldi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") @@ -6669,7 +6689,7 @@ #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) - + (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7335,7 +7355,7 @@ (const_int 0)))] "") -;; Split a logical operation that we can't do in one insn into two insns, +;; Split a logical operation that we can't do in one insn into two insns, ;; each of which does one 16-bit part. This is used by combine. (define_split @@ -7349,7 +7369,7 @@ " { rtx i3,i4; - + if (GET_CODE (operands[2]) == CONST_DOUBLE) { HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); @@ -7577,7 +7597,7 @@ ;; Used by sched, shorten_branches and final when the GOT pseudo reg ;; didn't get allocated to a hard register. -(define_split +(define_split [(set (match_operand:SI 0 "gpc_reg_operand" "") (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") (match_operand:SI 2 "memory_operand" "")] @@ -7640,12 +7660,16 @@ return \"ld %0,lo16(%2)(%1)\"; else { - operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); + /* APPLE LOCAL volatile pic base reg in leaves */ + operands2[3] = gen_rtx_REG (SImode, + (cfun->machine->substitute_pic_base_reg == INVALID_REGNUM + ? RS6000_PIC_OFFSET_TABLE_REGNUM + : cfun->machine->substitute_pic_base_reg)); output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); #if TARGET_MACHO if (MACHO_DYNAMIC_NO_PIC_P) output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); - else + else /* We cannot rely on ha16(low half)==ha16(high half), alas, although in practice it almost always is. */ output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); @@ -8474,7 +8498,7 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "input_operand" ""))] - "reload_completed && !TARGET_POWERPC64 + "reload_completed && !TARGET_POWERPC64 && gpr_or_gpr_p (operands[0], operands[1])" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) @@ -8634,7 +8658,7 @@ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] - "TARGET_POWER && ! TARGET_POWERPC64 + "TARGET_POWER && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "* { @@ -8682,7 +8706,7 @@ case 3: /* If the address is not used in the output, we can use lsi. Otherwise, fall through to generating four loads. */ - if (TARGET_STRING + if (TARGET_STRING && ! reg_overlap_mentioned_p (operands[0], operands[1])) return \"{lsi|lswi} %0,%P1,16\"; /* ... fall through ... */ @@ -8698,8 +8722,8 @@ "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "@ - # - # + # + # #" [(set_attr "type" "*,load,store")]) @@ -9831,7 +9855,7 @@ if (current_function_limit_stack) { rtx available; - available = expand_binop (Pmode, sub_optab, + available = expand_binop (Pmode, sub_optab, stack_pointer_rtx, stack_limit_rtx, NULL_RTX, 1, OPTAB_WIDEN); emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); @@ -10277,6 +10301,12 @@ else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) output_asm_insn (\"creqv 6,6,6\", operands); +/* APPLE LOCAL -mlongcall */ +#ifdef RS6000_LONG_BRANCH + if (!flag_pic) + return output_call(insn, operands, 0, 0); + else +#endif return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; }" [(set_attr "type" "branch") @@ -10392,7 +10422,7 @@ (match_operand 1 "" "g")) (use (match_operand:SI 2 "immediate_operand" "O")) (clobber (match_scratch:SI 3 "=l"))] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[2]) & CALL_LONG) == 0" "bl %z0\;%." @@ -10446,7 +10476,7 @@ (match_operand 2 "" "g"))) (use (match_operand:SI 3 "immediate_operand" "O")) (clobber (match_scratch:SI 4 "=l"))] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[3]) & CALL_LONG) == 0" "bl %z1\;%." @@ -10459,11 +10489,12 @@ ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument ;; which indicates how to set cr1 +;; APPLE LOCAL separate cl into c,*l; switch and attr's expanded to match (define_insn "*call_indirect_nonlocal_sysv" - [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) - (match_operand 1 "" "g,g")) - (use (match_operand:SI 2 "immediate_operand" "O,n")) - (clobber (match_scratch:SI 3 "=l,l"))] + [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l")) + (match_operand 1 "" "g,g,g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) + (clobber (match_scratch:SI 3 "=l,l,l,l"))] "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN" { @@ -10475,8 +10506,8 @@ return "b%T0l"; } - [(set_attr "type" "jmpreg,jmpreg") - (set_attr "length" "4,8")]) + [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") + (set_attr "length" "4,4,8,8")]) (define_insn "*call_nonlocal_sysv" [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) @@ -10502,12 +10533,13 @@ [(set_attr "type" "branch,branch") (set_attr "length" "4,8")]) +;; APPLE LOCAL separate cl into c,*l; switch and attr's expanded to match (define_insn "*call_value_indirect_nonlocal_sysv" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) - (match_operand 2 "" "g,g"))) - (use (match_operand:SI 3 "immediate_operand" "O,n")) - (clobber (match_scratch:SI 4 "=l,l"))] + (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l")) + (match_operand 2 "" "g,g,g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) + (clobber (match_scratch:SI 4 "=l,l,l,l"))] "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN" { @@ -10519,8 +10551,8 @@ return "b%T1l"; } - [(set_attr "type" "jmpreg,jmpreg") - (set_attr "length" "4,8")]) + [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") + (set_attr "length" "4,4,8,8")]) (define_insn "*call_value_nonlocal_sysv" [(set (match_operand 0 "" "") @@ -10575,6 +10607,52 @@ DONE; }") +;; APPLE LOCAL sibcall patterns +;; APPLE MERGE modify FSF patterns below instead? +;; this and similar patterns must be marked as using LR, otherwise +;; dataflow will try to delete the store into it. This is true +;; even when the actual reg to jump to is in CTR, when LR was +;; saved and restored around the PIC-setting BCL. +(define_insn "*sibcall_symbolic" + [(call (mem:SI (match_operand:SI 0 "call_operand" "s,c")) + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (use (match_scratch:SI 3 "=l,l")) + (return)] + "! TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN" + "* +{ + switch (which_alternative) + { + case 0: return \"b %z0\"; + case 1: return \"b%T0\"; + default: abort(); + } +}" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_value_symbolic" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "call_operand" "s,c")) + (match_operand 2 "" ""))) + (use (match_operand:SI 3 "" "")) + (use (match_scratch:SI 4 "=l,l")) + (return)] + "! TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN" + "* +{ + switch (which_alternative) + { + case 0: return \"b %z1\"; + case 1: return \"b%T1\"; + default: abort(); + } +}" + [(set_attr "type" "branch") + (set_attr "length" "4")]) +;; APPLE LOCAL end sibcall patterns + ;; sibling call patterns (define_expand "sibcall" [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) @@ -10704,7 +10782,7 @@ (use (match_operand:SI 2 "immediate_operand" "O")) (use (match_operand:SI 3 "register_operand" "l")) (return)] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[2]) & CALL_LONG) == 0" "b %z0" @@ -10732,7 +10810,7 @@ (use (match_operand:SI 3 "immediate_operand" "O")) (use (match_operand:SI 4 "register_operand" "l")) (return)] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[3]) & CALL_LONG) == 0" "b %z1" @@ -11009,11 +11087,11 @@ [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] "" " -{ +{ if (! rs6000_compare_fp_p) FAIL; - rs6000_emit_sCOND (NE, operands[0]); + rs6000_emit_sCOND (NE, operands[0]); DONE; }") @@ -11041,7 +11119,7 @@ && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; - rs6000_emit_sCOND (GT, operands[0]); + rs6000_emit_sCOND (GT, operands[0]); DONE; }") @@ -11055,7 +11133,7 @@ && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; - rs6000_emit_sCOND (LE, operands[0]); + rs6000_emit_sCOND (LE, operands[0]); DONE; }") @@ -11065,11 +11143,11 @@ "" " { - if (! rs6000_compare_fp_p + if (! rs6000_compare_fp_p && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; - rs6000_emit_sCOND (LT, operands[0]); + rs6000_emit_sCOND (LT, operands[0]); DONE; }") @@ -13791,7 +13869,7 @@ }") (define_expand "tablejumpdi" - [(set (match_dup 4) + [(set (match_dup 4) (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) (set (match_dup 3) (plus:DI (match_dup 4) @@ -13900,7 +13978,7 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") + (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -13924,7 +14002,7 @@ (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") + (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -13948,7 +14026,7 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -13972,7 +14050,7 @@ (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -13998,7 +14076,7 @@ (const_int 0)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") + (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14022,7 +14100,7 @@ (const_int 0)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") + (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14046,7 +14124,7 @@ (const_int 0)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14070,7 +14148,7 @@ (const_int 0)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14096,7 +14174,7 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") + (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14120,7 +14198,7 @@ (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") + (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14144,7 +14222,7 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14168,7 +14246,7 @@ (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -14363,7 +14441,7 @@ (define_insn "movesi_from_cr" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) + (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] UNSPEC_MOVESI_FROM_CR))] "" @@ -14376,7 +14454,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r"))])] "TARGET_MULTIPLE" "{stm|stmw} %2,%1") - + (define_insn "*save_fpregs_si" [(match_parallel 0 "any_operand" [(clobber (match_operand:SI 1 "register_operand" "=l")) @@ -14388,6 +14466,35 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) +/* APPLE LOCAL begin unnamed*/ +(define_insn "*save_fpregs_with_label_si" + [(match_parallel 0 "any_operand" + [(clobber (match_operand:SI 1 "register_operand" "=l")) + (use (match_operand:SI 2 "call_operand" "s")) + (use (match_operand:SI 3 "" "")) + (set (match_operand:DF 4 "memory_operand" "=m") + (match_operand:DF 5 "gpc_reg_operand" "f"))])] + "TARGET_32BIT" + "* +#if TARGET_MACHO + const char *picbase = machopic_function_base_name (); + char *tmp; + operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); + if (TARGET_LONG_BRANCH) + { + tmp = ggc_alloc (strlen (XSTR (operands[2], 0)) + strlen (XSTR (operands[3], 0)) + 2); + strcpy (tmp, output_call(insn, operands, 2, 2)); + strcat (tmp, \"\\n%3:\"); + return tmp; + } + else +#endif + return \"bl %z2\\n%3:\"; +" + [(set_attr "type" "branch") + (set_attr "length" "4")]) +/* APPLE LOCAL end unnamed */ + (define_insn "*save_fpregs_di" [(match_parallel 0 "any_operand" [(clobber (match_operand:DI 1 "register_operand" "=l")) @@ -14452,7 +14559,7 @@ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") (match_operand 2 "immediate_operand" "n")] UNSPEC_MOVESI_TO_CR))] - "GET_CODE (operands[0]) == REG + "GET_CODE (operands[0]) == REG && CR_REGNO_P (REGNO (operands[0])) && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" @@ -14469,7 +14576,7 @@ (match_operand:SI 2 "memory_operand" "m"))])] "TARGET_MULTIPLE" "{lm|lmw} %1,%2") - + (define_insn "*return_internal_si" [(return) (use (match_operand:SI 0 "register_operand" "lc"))] @@ -14495,7 +14602,14 @@ (set (match_operand:DF 3 "gpc_reg_operand" "=f") (match_operand:DF 4 "memory_operand" "m"))])] "TARGET_32BIT" - "b %z2") + { +#if TARGET_MACHO + if (TARGET_LONG_BRANCH) + return output_call(insn, operands, 2, 2); + else +#endif + return "b %z2"; + }) (define_insn "*return_and_restore_fpregs_di" [(match_parallel 0 "any_operand" @@ -14505,7 +14619,14 @@ (set (match_operand:DF 3 "gpc_reg_operand" "=f") (match_operand:DF 4 "memory_operand" "m"))])] "TARGET_64BIT" - "b %z2") + { +#if TARGET_MACHO + if (TARGET_LONG_BRANCH) + return output_call(insn, operands, 2, 2); + else +#endif + return "b %z2"; + }) ; This is used in compiling the unwind routines. (define_expand "eh_return" |