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Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
-rw-r--r--gcc/config/rs6000/rs6000.md290
1 files changed, 241 insertions, 49 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3fdb165dd41..1ecd2f587c9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -50,7 +50,7 @@
(UNSPEC_TLSGOTTPREL 28)
(UNSPEC_TLSTLS 29)
(UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
- (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
+ (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
])
;;
@@ -4622,8 +4622,8 @@
(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
- && ! HONOR_SIGNED_ZEROS (SFmode)"
+;; APPLE LOCAL do this even if honoring siged zeros
+ "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")])
@@ -4641,8 +4641,8 @@
(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
- && ! HONOR_SIGNED_ZEROS (SFmode)"
+;; APPLE LOCAL do this even if honoring siged zeros
+ "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")])
@@ -4661,8 +4661,8 @@
(minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))))]
- "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
- && ! HONOR_SIGNED_ZEROS (SFmode)"
+;; APPLE LOCAL do this even if honoring siged zeros
+ "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")])
@@ -4680,8 +4680,8 @@
(minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
- && ! HONOR_SIGNED_ZEROS (SFmode)"
+;; APPLE LOCAL do this even if honoring siged zeros
+ "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")])
@@ -4984,8 +4984,8 @@
(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
(match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
- && ! HONOR_SIGNED_ZEROS (DFmode)"
+;; APPLE LOCAL do this even if honoring siged zeros
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")])
@@ -5004,8 +5004,8 @@
(minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
- && ! HONOR_SIGNED_ZEROS (DFmode)"
+;; APPLE LOCAL do this even if honoring siged zeros
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")])
@@ -5121,7 +5121,12 @@
}
if (TARGET_POWERPC64)
{
- rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+ /* APPLE LOCAL begin assign_stack_local_with_alias scheduling speedup */
+ /* assign_stack_local_with_alias is used instead of assign_stack_temp
+ * to get better scheduling, at the cost of some stack space. */
+ rtx mem = assign_stack_local_with_alias (DImode, GET_MODE_SIZE (DImode),
+ GET_MODE_ALIGNMENT (DImode));
+ /* APPLE LOCAL end assign_stack_local_with_alias scheduling speedup */
rtx t1 = gen_reg_rtx (DImode);
rtx t2 = gen_reg_rtx (DImode);
emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
@@ -5130,7 +5135,12 @@
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
- operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
+ /* APPLE LOCAL begin assign_stack_local_with_alias scheduling speedup */
+ /* assign_stack_local_with_alias is used instead of assign_stack_temp to get
+ * better scheduling, at the cost of some stack space. */
+ operands[4] = assign_stack_local_with_alias (DFmode, GET_MODE_SIZE (DFmode),
+ GET_MODE_ALIGNMENT (DFmode));
+ /* APPLE LOCAL end assign_stack_local_with_alias scheduling speedup */
operands[5] = gen_reg_rtx (DFmode);
operands[6] = gen_reg_rtx (SImode);
}")
@@ -5208,7 +5218,12 @@
}
if (TARGET_POWERPC64)
{
- rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+ /* APPLE LOCAL begin assign_stack_local_with_alias scheduling speedup */
+ /* assign_stack_local_with_alias is used instead of assign_stack_temp
+ * to get better scheduling, at the cost of some stack space. */
+ rtx mem = assign_stack_local_with_alias (DImode, GET_MODE_SIZE (DImode),
+ GET_MODE_ALIGNMENT (DImode));
+ /* APPLE LOCAL end assign_stack_local_with_alias scheduling speedup */
rtx t1 = gen_reg_rtx (DImode);
rtx t2 = gen_reg_rtx (DImode);
emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
@@ -5218,7 +5233,12 @@
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
- operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
+ /* APPLE LOCAL begin assign_stack_local_with_alias scheduling speedup */
+ /* assign_stack_local_with_alias is used instead of assign_stack_temp
+ * to get better scheduling, at the cost of some stack space. */
+ operands[4] = assign_stack_local_with_alias (DFmode, GET_MODE_SIZE (DFmode),
+ GET_MODE_ALIGNMENT (DFmode));
+ /* APPLE LOCAL end assign_stack_local_with_alias scheduling speedup */
operands[5] = gen_reg_rtx (DFmode);
}")
@@ -5282,7 +5302,12 @@
DONE;
}
operands[2] = gen_reg_rtx (DImode);
- operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+ /* APPLE LOCAL begin assign_stack_local_with_alias scheduling speedup */
+ /* assign_stack_local_with_alias is used instead of assign_stack_temp
+ * to get better scheduling, at the cost of some stack space. */
+ operands[3] = assign_stack_local_with_alias (DImode, GET_MODE_SIZE (DImode),
+ GET_MODE_ALIGNMENT (DImode));
+ /* APPLE LOCAL end assign_stack_local_with_alias scheduling speedup */
}")
(define_insn "*fix_truncdfsi2_internal"
@@ -8326,11 +8351,11 @@
})
(define_expand "trunctfdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
- (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
-"")
+ "")
(define_insn_and_split "trunctfdf2_internal1"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
@@ -10140,11 +10165,10 @@
(define_insn "load_toc_v4_PIC_1b"
[(set (match_operand:SI 0 "register_operand" "=l")
- (match_operand:SI 1 "immediate_operand" "s"))
- (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
UNSPEC_TOCPTR))]
"TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
- "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
+ "bcl 20,31,$+8\\n\\t.long %1-$"
[(set_attr "type" "branch")
(set_attr "length" "8")])
@@ -10406,6 +10430,13 @@
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
+/* APPLE LOCAL begin -mlongcall */
+#ifdef RS6000_LONG_BRANCH
+ if (!flag_pic)
+ return output_call(insn, operands, 0, 0);
+ else
+#endif
+/* APPLE LOCAL end -mlongcall */
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
}"
[(set_attr "type" "branch")
@@ -10588,11 +10619,12 @@
;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
;; which indicates how to set cr1
+;; APPLE LOCAL begin separate cl into c,*l; switch and attr's expanded to match
(define_insn "*call_indirect_nonlocal_sysv"
- [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
- (match_operand 1 "" "g,g"))
- (use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (match_scratch:SI 3 "=l,l"))]
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
+ (match_operand 1 "" "g,g,g,g"))
+ (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
+ (clobber (match_scratch:SI 3 "=l,l,l,l"))]
"DEFAULT_ABI == ABI_V4
|| DEFAULT_ABI == ABI_DARWIN"
{
@@ -10604,8 +10636,9 @@
return "b%T0l";
}
- [(set_attr "type" "jmpreg,jmpreg")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
+ (set_attr "length" "4,4,8,8")])
+;; APPLE LOCAL end separate cl into c,*l; switch and attr's expanded to match
(define_insn "*call_nonlocal_sysv"
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
@@ -10622,6 +10655,21 @@
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn ("creqv 6,6,6", operands);
+ /* APPLE LOCAL begin ObjC direct dispatch. */
+ /* Generate 'bla' instruction for functions with hard-coded addresses. */
+ if (DEFAULT_ABI == ABI_DARWIN)
+ {
+ rtx note = find_reg_note (insn, REG_ABSCALL, NULL_RTX);
+ static char buf[256];
+ if (note)
+ {
+ sprintf (buf, \"bla \" HOST_WIDE_INT_PRINT_HEX,
+ INTVAL (XEXP (note, 0)));
+ return buf;
+ }
+ }
+ /* APPLE LOCAL end ObjC direct dispatch. */
+
#if TARGET_MACHO
return output_call(insn, operands, 0, 2);
#else
@@ -10631,12 +10679,13 @@
[(set_attr "type" "branch,branch")
(set_attr "length" "4,8")])
+;; APPLE LOCAL begin separate cl into c,*l; switch and attr's expanded to match
(define_insn "*call_value_indirect_nonlocal_sysv"
[(set (match_operand 0 "" "")
- (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
- (match_operand 2 "" "g,g")))
- (use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (match_scratch:SI 4 "=l,l"))]
+ (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
+ (match_operand 2 "" "g,g,g,g")))
+ (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
+ (clobber (match_scratch:SI 4 "=l,l,l,l"))]
"DEFAULT_ABI == ABI_V4
|| DEFAULT_ABI == ABI_DARWIN"
{
@@ -10648,8 +10697,9 @@
return "b%T1l";
}
- [(set_attr "type" "jmpreg,jmpreg")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
+ (set_attr "length" "4,4,8,8")])
+;; APPLE LOCAL end separate cl into c,*l; switch and attr's expanded to match
(define_insn "*call_value_nonlocal_sysv"
[(set (match_operand 0 "" "")
@@ -10667,6 +10717,21 @@
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn ("creqv 6,6,6", operands);
+ /* APPLE LOCAL begin ObjC direct dispatch. */
+ /* Generate 'bla' instruction for functions with hard-coded addresses. */
+ if (DEFAULT_ABI == ABI_DARWIN)
+ {
+ rtx note = find_reg_note (insn, REG_ABSCALL, NULL_RTX);
+ static char buf[256];
+ if (note)
+ {
+ sprintf (buf, \"bla \" HOST_WIDE_INT_PRINT_HEX,
+ INTVAL (XEXP (note, 0)));
+ return buf;
+ }
+ }
+ /* APPLE LOCAL end ObjC direct dispatch. */
+
#if TARGET_MACHO
return output_call(insn, operands, 1, 3);
#else
@@ -10704,6 +10769,86 @@
DONE;
}")
+;; APPLE LOCAL begin sibcall patterns
+;; APPLE MERGE modify FSF patterns below instead?
+;; this and similar patterns must be marked as using LR, otherwise
+;; dataflow will try to delete the store into it. This is true
+;; even when the actual reg to jump to is in CTR, when LR was
+;; saved and restored around the PIC-setting BCL.
+(define_insn "*sibcall_symbolic"
+ [(call (mem:SI (match_operand:SI 0 "call_operand" "s,c"))
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand:SI 3 "register_operand" "l,l"))
+ (return)]
+ "! TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
+ "*
+{
+ /* APPLE LOCAL begin ObjC direct dispatch */
+ /* Generate 'ba' instruction for functions with hard-coded addresses. */
+ if (DEFAULT_ABI == ABI_DARWIN)
+ {
+ rtx note = find_reg_note (insn, REG_ABSCALL, NULL_RTX);
+ static char buf[256];
+ if (note)
+ {
+ if (which_alternative != 0)
+ abort ();
+ sprintf (buf, \"ba \" HOST_WIDE_INT_PRINT_HEX,
+ INTVAL (XEXP (note, 0)));
+ return buf;
+ }
+ }
+ /* APPLE LOCAL end ObjC direct dispatch */
+
+ switch (which_alternative)
+ {
+ case 0: return \"b %z0\";
+ case 1: return \"b%T0\";
+ default: abort();
+ }
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4")])
+
+(define_insn "*sibcall_value_symbolic"
+ [(set (match_operand 0 "" "")
+ (call (mem:SI (match_operand:SI 1 "call_operand" "s,c"))
+ (match_operand 2 "" "")))
+ (use (match_operand:SI 3 "" ""))
+ (use (match_operand:SI 4 "register_operand" "l,l"))
+ (return)]
+ "! TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
+ "*
+{
+ /* APPLE LOCAL begin ObjC direct dispatch */
+ /* Generate 'ba' instruction for functions with hard-coded addresses. */
+ if (DEFAULT_ABI == ABI_DARWIN)
+ {
+ rtx note = find_reg_note (insn, REG_ABSCALL, NULL_RTX);
+ static char buf[256];
+ if (note)
+ {
+ if (which_alternative != 0)
+ abort ();
+ sprintf (buf, \"ba \" HOST_WIDE_INT_PRINT_HEX,
+ INTVAL (XEXP (note, 0)));
+ return buf;
+ }
+ }
+ /* APPLE LOCAL end ObjC direct dispatch */
+
+ switch (which_alternative)
+ {
+ case 0: return \"b %z1\";
+ case 1: return \"b%T1\";
+ default: abort();
+ }
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4")])
+;; APPLE LOCAL end sibcall patterns
+
;; sibling call patterns
(define_expand "sibcall"
[(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
@@ -11473,11 +11618,11 @@
(set_attr "length" "8")])
;; Same as above, but get the GT bit.
-(define_insn "move_from_CR_eq_bit"
+(define_insn "move_from_CR_gt_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
+ (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
"TARGET_E500"
- "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
+ "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
[(set_attr "type" "mfcr")
(set_attr "length" "8")])
@@ -12670,25 +12815,25 @@
"")
(define_insn_and_split ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
"TARGET_32BIT"
"#"
- "TARGET_32BIT"
+ "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
[(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
"")
(define_insn_and_split ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
(plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
"TARGET_64BIT"
"#"
- "TARGET_64BIT"
+ "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
[(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
"")
@@ -13628,25 +13773,25 @@
"")
(define_insn_and_split ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(match_operand:SI 3 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
"#"
- "TARGET_32BIT"
+ "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
[(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
"")
(define_insn_and_split ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI"))
(match_operand:DI 3 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
"#"
- "TARGET_64BIT"
+ "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
[(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
"")
@@ -14554,6 +14699,35 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
+/* APPLE LOCAL begin unnamed*/
+(define_insn "*save_fpregs_with_label_si"
+ [(match_parallel 0 "any_parallel_operand"
+ [(clobber (match_operand:SI 1 "register_operand" "=l"))
+ (use (match_operand:SI 2 "call_operand" "s"))
+ (use (match_operand:SI 3 "" ""))
+ (set (match_operand:DF 4 "memory_operand" "=m")
+ (match_operand:DF 5 "gpc_reg_operand" "f"))])]
+ "TARGET_32BIT"
+ "*
+#if TARGET_MACHO
+ const char *picbase = machopic_function_base_name ();
+ char *tmp;
+ operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
+ if (TARGET_LONG_BRANCH)
+ {
+ tmp = ggc_alloc (strlen (XSTR (operands[2], 0)) + strlen (XSTR (operands[3], 0)) + 2);
+ strcpy (tmp, output_call(insn, operands, 2, 2));
+ strcat (tmp, \"\\n%3:\");
+ return tmp;
+ }
+ else
+#endif
+ return \"bl %z2\\n%3:\";
+"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4")])
+/* APPLE LOCAL end unnamed */
+
(define_insn "*save_fpregs_di"
[(match_parallel 0 "any_parallel_operand"
[(clobber (match_operand:DI 1 "register_operand" "=l"))
@@ -14661,7 +14835,16 @@
(set (match_operand:DF 3 "gpc_reg_operand" "=f")
(match_operand:DF 4 "memory_operand" "m"))])]
"TARGET_32BIT"
- "b %z2")
+; APPLE LOCAL begin -mlongcall
+ {
+#if TARGET_MACHO
+ if (TARGET_LONG_BRANCH)
+ return output_call(insn, operands, 2, 2);
+ else
+#endif
+ return "b %z2";
+ })
+; APPLE LOCAL end -mlongcall
(define_insn "*return_and_restore_fpregs_di"
[(match_parallel 0 "any_parallel_operand"
@@ -14671,7 +14854,16 @@
(set (match_operand:DF 3 "gpc_reg_operand" "=f")
(match_operand:DF 4 "memory_operand" "m"))])]
"TARGET_64BIT"
- "b %z2")
+; APPLE LOCAL begin -mlongcall
+ {
+#if TARGET_MACHO
+ if (TARGET_LONG_BRANCH)
+ return output_call(insn, operands, 2, 2);
+ else
+#endif
+ return "b %z2";
+ })
+; APPLE LOCAL end -mlongcall
; This is used in compiling the unwind routines.
(define_expand "eh_return"
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 07:13:13 +0000