diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 78 |
1 files changed, 11 insertions, 67 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 44d32d9edc8..93995390644 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -137,7 +137,6 @@ UNSPEC_FUSION_GPR UNSPEC_STACK_CHECK UNSPEC_FUSION_P9 - UNSPEC_FUSION_ADDIS UNSPEC_ADD_ROUND_TO_ODD UNSPEC_SUB_ROUND_TO_ODD UNSPEC_MUL_ROUND_TO_ODD @@ -13593,66 +13592,11 @@ ;; a GPR. The addis instruction must be adjacent to the load, and use the same ;; register that is being loaded. The fused ops must be physically adjacent. -;; There are two parts to addis fusion. The support for fused TOCs occur -;; before register allocation, and is meant to reduce the lifetime for the -;; tempoary register that holds the ADDIS result. On Power8 GPR loads, we try -;; to use the register that is being load. The peephole2 then gathers any -;; other fused possibilities that it can find after register allocation. If -;; power9 fusion is selected, we also fuse floating point loads/stores. +;; On Power8 GPR loads, we try to use the register that is being load. The +;; peephole2 then gathers any other fused possibilities that it can find after +;; register allocation. If power9 fusion is selected, we also fuse floating +;; point loads/stores. -;; Fused TOC support: Replace simple GPR loads with a fused form. This is done -;; before register allocation, so that we can avoid allocating a temporary base -;; register that won't be used, and that we try to load into base registers, -;; and not register 0. If we can't get a fused GPR load, generate a P9 fusion -;; (addis followed by load) even on power8. - -(define_split - [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand") - (match_operand:INT1 1 "toc_fusion_mem_raw"))] - "TARGET_TOC_FUSION_INT && can_create_pseudo_p ()" - [(parallel [(set (match_dup 0) (match_dup 2)) - (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS) - (use (match_dup 3)) - (clobber (scratch:DI))])] -{ - operands[2] = fusion_wrap_memory_address (operands[1]); - operands[3] = gen_rtx_REG (Pmode, TOC_REGISTER); -}) - -(define_insn "*toc_fusionload_<mode>" - [(set (match_operand:QHSI 0 "int_reg_operand" "=&b,??r") - (match_operand:QHSI 1 "toc_fusion_mem_wrapped" "wG,wG")) - (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS) - (use (match_operand:DI 2 "base_reg_operand" "r,r")) - (clobber (match_scratch:DI 3 "=X,&b"))] - "TARGET_TOC_FUSION_INT" -{ - if (base_reg_operand (operands[0], <MODE>mode)) - return emit_fusion_gpr_load (operands[0], operands[1]); - - return emit_fusion_p9_load (operands[0], operands[1], operands[3]); -} - [(set_attr "type" "load") - (set_attr "length" "8")]) - -(define_insn "*toc_fusionload_di" - [(set (match_operand:DI 0 "int_reg_operand" "=&b,??r,?d") - (match_operand:DI 1 "toc_fusion_mem_wrapped" "wG,wG,wG")) - (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS) - (use (match_operand:DI 2 "base_reg_operand" "r,r,r")) - (clobber (match_scratch:DI 3 "=X,&b,&b"))] - "TARGET_TOC_FUSION_INT && TARGET_POWERPC64 - && (MEM_P (operands[1]) || int_reg_operand (operands[0], DImode))" -{ - if (base_reg_operand (operands[0], DImode)) - return emit_fusion_gpr_load (operands[0], operands[1]); - - return emit_fusion_p9_load (operands[0], operands[1], operands[3]); -} - [(set_attr "type" "load") - (set_attr "length" "8")]) - - ;; Find cases where the addis that feeds into a load instruction is either used ;; once or is the same as the target register, and replace it with the fusion ;; insn @@ -13674,7 +13618,7 @@ ;; Fusion insn, created by the define_peephole2 above (and eventually by ;; reload) -(define_insn "fusion_gpr_load_<mode>" +(define_insn "*fusion_gpr_load_<mode>" [(set (match_operand:INT1 0 "base_reg_operand" "=b") (unspec:INT1 [(match_operand:INT1 1 "fusion_addis_mem_combo_load" "wF")] UNSPEC_FUSION_GPR))] @@ -13691,7 +13635,7 @@ (define_peephole2 [(set (match_operand:P 0 "base_reg_operand") (match_operand:P 1 "fusion_gpr_addis")) - (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand") + (set (match_operand:SFDF 2 "p9_fusion_reg_operand") (match_operand:SFDF 3 "fusion_offsettable_mem_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3])" @@ -13705,7 +13649,7 @@ [(set (match_operand:P 0 "base_reg_operand") (match_operand:P 1 "fusion_gpr_addis")) (set (match_operand:SFDF 2 "offsettable_mem_operand") - (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))] + (match_operand:SFDF 3 "p9_fusion_reg_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3]) && !rtx_equal_p (operands[0], operands[3])" @@ -13743,7 +13687,7 @@ ;; reload). Because we want to eventually have secondary_reload generate ;; these, they have to have a single alternative that gives the register ;; classes. This means we need to have separate gpr/fpr/altivec versions. -(define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load" +(define_insn "*fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load" [(set (match_operand:GPR_FUSION 0 "int_reg_operand" "=r") (unspec:GPR_FUSION [(match_operand:GPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")] @@ -13761,7 +13705,7 @@ [(set_attr "type" "load") (set_attr "length" "8")]) -(define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store" +(define_insn "*fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store" [(set (match_operand:GPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF") (unspec:GPR_FUSION [(match_operand:GPR_FUSION 1 "int_reg_operand" "r")] @@ -13774,7 +13718,7 @@ [(set_attr "type" "store") (set_attr "length" "8")]) -(define_insn "fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load" +(define_insn "*fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load" [(set (match_operand:FPR_FUSION 0 "vsx_register_operand" "=dwb") (unspec:FPR_FUSION [(match_operand:FPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")] @@ -13787,7 +13731,7 @@ [(set_attr "type" "fpload") (set_attr "length" "8")]) -(define_insn "fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store" +(define_insn "*fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store" [(set (match_operand:FPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF") (unspec:FPR_FUSION [(match_operand:FPR_FUSION 1 "vsx_register_operand" "dwb")] |