diff options
Diffstat (limited to 'gcc/config/rs6000')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/dfp.md | 39 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 94 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-c.c | 40 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-cpus.def | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 29 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.opt | 6 |
8 files changed, 210 insertions, 11 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 0cd67a4ec99..fa6314fd758 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3680,21 +3680,21 @@ (define_insn "darn_32" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] - "TARGET_MODULO" + "TARGET_P9_MISC" "darn %0,0" [(set_attr "type" "integer")]) (define_insn "darn_raw" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] - "TARGET_MODULO && TARGET_64BIT" + "TARGET_P9_MISC && TARGET_64BIT" "darn %0,2" [(set_attr "type" "integer")]) (define_insn "darn" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(const_int 0)] UNSPEC_DARN))] - "TARGET_MODULO && TARGET_64BIT" + "TARGET_P9_MISC && TARGET_64BIT" "darn %0,1" [(set_attr "type" "integer")]) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 7029eb6da38..0e828063569 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -319,8 +319,11 @@ UNSPEC_DXEX UNSPEC_DIEX UNSPEC_DSCLI + UNSPEC_DTSTSFI UNSPEC_DSCRI]) +(define_code_iterator DFP_TEST [eq lt gt unordered]) + (define_mode_iterator D64_D128 [DD TD]) (define_mode_attr dfp_suffix [(DD "") @@ -352,6 +355,42 @@ "dxex<dfp_suffix> %0,%1" [(set_attr "type" "fp")]) +(define_expand "dfptstsfi_<code>_<mode>" + [(set (match_dup 3) + (compare:CCFP + (unspec:D64_D128 + [(match_operand:SI 1 "const_int_operand" "n") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DTSTSFI) + (match_dup 4))) + (set (match_operand:SI 0 "register_operand" "") + (DFP_TEST:SI (match_dup 3) + (const_int 0))) + ] + "TARGET_P9_MISC" +{ + operands[3] = gen_reg_rtx (CCFPmode); + operands[4] = CONST0_RTX (SImode); +}) + +(define_insn "*dfp_sgnfcnc_<mode>" + [(set (match_operand:CCFP 0 "" "=y") + (compare:CCFP + (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DTSTSFI) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_MISC" + { + /* If immediate operand is greater than 63, it will behave as if + * the value had been 63. The code generator does not support + * immediate operand values greater than 63. */ + if (!(IN_RANGE (INTVAL (operands[1]), 0, 63))) + operands[1] = GEN_INT (63); + return "dtstsfi<dfp_suffix> %0,%1,%2"; + } + [(set_attr "type" "fp")]) + (define_insn "dfp_diex_<mode>" [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index a52da3bfb27..a1e718e5aff 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -656,10 +656,18 @@ /* Miscellaneous builtins for instructions added in ISA 3.0. These instructions don't require either the DFP or VSX options, just the basic ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO, /* MASK */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -671,23 +679,65 @@ #define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO \ + RS6000_BTM_P9_MISC \ | RS6000_BTM_64BIT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_ ## ICODE) /* ICODE */ -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers. */ -#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ +/* Miscellaneous builtins for decimal floating point instructions + added in ISA 3.0. These instructions don't require the VSX + options, just the basic ISA 3.0 enablement since they operate on + general purpose registers. */ +#define BU_P9_DFP_MISC_0(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO, /* MASK */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P9_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P9_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Decimal floating point overloaded functions added in ISA 3.0 */ +#define BU_P9_DFP_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ + "__builtin_dfp_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9_DFP_OVERLOAD_2(ENUM, NAME) \ + RS6000_BUILTIN_2 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ + "__builtin_dfp_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9_DFP_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ + "__builtin_dfp_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + /* ISA 3.0 (power9) vector convenience macros. */ /* For the instructions that are encoded as altivec instructions use __builtin_altivec_ as the builtin name. */ @@ -1794,6 +1844,36 @@ BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) +/* 2 argument DFP (Decimal Floating Point) functions added in ISA 3.0. */ +BU_P9_DFP_MISC_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd", CONST, dfptstsfi_lt_dd) +BU_P9_DFP_MISC_2 (TSTSFI_LT_TD, "dtstsfi_lt_td", CONST, dfptstsfi_lt_td) + +BU_P9_DFP_MISC_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd", CONST, dfptstsfi_eq_dd) +BU_P9_DFP_MISC_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td", CONST, dfptstsfi_eq_td) + +BU_P9_DFP_MISC_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd", CONST, dfptstsfi_gt_dd) +BU_P9_DFP_MISC_2 (TSTSFI_GT_TD, "dtstsfi_gt_td", CONST, dfptstsfi_gt_td) + +BU_P9_DFP_MISC_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd", CONST, dfptstsfi_unordered_dd) +BU_P9_DFP_MISC_2 (TSTSFI_OV_TD, "dtstsfi_ov_td", CONST, dfptstsfi_unordered_td) + +/* 2 argument overloaded DFP functions added in ISA 3.0. */ +BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT, "dtstsfi_lt") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_TD, "dtstsfi_lt_td") + +BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ, "dtstsfi_eq") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td") + +BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT, "dtstsfi_gt") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_TD, "dtstsfi_gt_td") + +BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV, "dtstsfi_ov") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_TD, "dtstsfi_ov_td") + /* 1 argument vector functions added in ISA 3.0 (power9). */ BU_P9V_AV_1 (VCTZB, "vctzb", CONST, ctzv16qi2) BU_P9V_AV_1 (VCTZH, "vctzh", CONST, ctzv8hi2) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 79a7e88a5ee..4500668ed9f 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4203,6 +4203,46 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index a67b2d91b4e..83dd9af4f5f 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -69,6 +69,7 @@ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_FUSION \ | OPTION_MASK_P9_DFORM_SCALAR \ + | OPTION_MASK_P9_MISC \ | OPTION_MASK_P9_VECTOR) #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) @@ -108,6 +109,7 @@ | OPTION_MASK_P9_DFORM_VECTOR \ | OPTION_MASK_P9_FUSION \ | OPTION_MASK_P9_MINMAX \ + | OPTION_MASK_P9_MISC \ | OPTION_MASK_P9_VECTOR \ | OPTION_MASK_POPCNTB \ | OPTION_MASK_POPCNTD \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7e9e908619a..bff43d687f5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3676,6 +3676,7 @@ rs6000_builtin_mask_calculate (void) | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) + | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0) | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) @@ -13398,6 +13399,26 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) return const0_rtx; } } + else if (icode == CODE_FOR_dfptstsfi_eq_dd + || icode == CODE_FOR_dfptstsfi_lt_dd + || icode == CODE_FOR_dfptstsfi_gt_dd + || icode == CODE_FOR_dfptstsfi_unordered_dd + || icode == CODE_FOR_dfptstsfi_eq_td + || icode == CODE_FOR_dfptstsfi_lt_td + || icode == CODE_FOR_dfptstsfi_gt_td + || icode == CODE_FOR_dfptstsfi_unordered_td) + { + /* Only allow 6-bit unsigned literals. */ + STRIP_NOPS (arg0); + if (TREE_CODE (arg0) != INTEGER_CST + || TREE_INT_CST_LOW (arg0) & ~0x3f) + { + error ("argument 1 must be a 6-bit unsigned literal"); + return CONST0_RTX (tmode); + } + } + + if (target == 0 || GET_MODE (target) != tmode @@ -15504,6 +15525,12 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode) error ("Builtin function %s requires the -mpower8-vector option", name); else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0) error ("Builtin function %s requires the -mpower9-vector option", name); + else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) + == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) + error ("Builtin function %s requires the -mpower9-misc and" + " -m64 options", name); + else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC) + error ("Builtin function %s requires the -mpower9-misc option", name); else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128)) == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128)) error ("Builtin function %s requires the -mhard-float and" @@ -35508,6 +35535,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power9-dform-vector", OPTION_MASK_P9_DFORM_VECTOR, false, true }, { "power9-fusion", OPTION_MASK_P9_FUSION, false, true }, { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true }, + { "power9-misc", OPTION_MASK_P9_MISC, false, true }, { "power9-vector", OPTION_MASK_P9_VECTOR, false, true }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, @@ -35564,6 +35592,7 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "cell", RS6000_BTM_CELL, false, false }, { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, { "power9-vector", RS6000_BTM_P9_VECTOR, false, false }, + { "power9-misc", RS6000_BTM_P9_MISC, false, false }, { "crypto", RS6000_BTM_CRYPTO, false, false }, { "htm", RS6000_BTM_HTM, false, false }, { "hard-dfp", RS6000_BTM_DFP, false, false }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d3cba82748b..51d7ab358b5 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -314,12 +314,14 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #undef TARGET_P9_MINMAX #undef TARGET_P9_DFORM_SCALAR #undef TARGET_P9_DFORM_VECTOR +#undef TARGET_P9_MISC #define TARGET_FLOAT128_HW 0 #define TARGET_MODULO 0 #define TARGET_P9_VECTOR 0 #define TARGET_P9_MINMAX 0 #define TARGET_P9_DFORM_SCALAR 0 #define TARGET_P9_DFORM_VECTOR 0 +#define TARGET_P9_MISC 0 #endif /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If @@ -645,6 +647,7 @@ extern int rs6000_vector_align[]; #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR +#define MASK_P9_MISC OPTION_MASK_P9_MISC #define MASK_POPCNTB OPTION_MASK_POPCNTB #define MASK_POPCNTD OPTION_MASK_POPCNTD #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT @@ -2695,6 +2698,7 @@ extern int frame_pointer_needed; #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ +#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ #define RS6000_BTM_SPE MASK_STRING /* E500 */ @@ -2714,6 +2718,7 @@ extern int frame_pointer_needed; | RS6000_BTM_VSX \ | RS6000_BTM_P8_VECTOR \ | RS6000_BTM_P9_VECTOR \ + | RS6000_BTM_P9_MISC \ | RS6000_BTM_MODULO \ | RS6000_BTM_CRYPTO \ | RS6000_BTM_FRE \ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 4b9905fe767..992e1dda79c 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -609,9 +609,13 @@ mpower9-fusion Target Report Mask(P9_FUSION) Var(rs6000_isa_flags) Fuse certain operations together for better performance on power9. +mpower9-misc +Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) +Use/do not certain scalar instructions added in ISA 3.0. + mpower9-vector Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags) -Use/do not use vector and scalar instructions added in ISA 3.0. +Use/do not use vector instructions added in ISA 3.0. mpower9-dform-scalar Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags) |