diff options
Diffstat (limited to 'gcc/config/s390/s390.md')
| -rw-r--r-- | gcc/config/s390/s390.md | 98 |
1 files changed, 85 insertions, 13 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 32753ef746d..93a0bc6767e 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -5795,6 +5795,15 @@ (set_attr "cpu_facility" "*,z196,extimm,z10") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) +(define_insn "*adddi3_sign" + [(set (match_operand:DI 0 "register_operand" "=d") + (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) + (match_operand:DI 1 "register_operand" "0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARCH12" + "agh\t%0,%2" + [(set_attr "op_type" "RXY")]) + ; ; add(tf|df|sf|td|dd)3 instruction pattern(s). ; @@ -6226,6 +6235,15 @@ (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) +(define_insn "*subdi3_sign" + [(set (match_operand:DI 0 "register_operand" "=d") + (minus:DI (match_operand:DI 1 "register_operand" "0") + (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARCH12" + "sgh\t%0,%2" + [(set_attr "op_type" "RXY")]) + ; ; sub(tf|df|sf|td|dd)3 instruction pattern(s). @@ -6565,6 +6583,14 @@ ; muldi3 instruction pattern(s). ; +(define_expand "muldi3" + [(parallel + [(set (match_operand:DI 0 "register_operand") + (mult:DI (match_operand:DI 1 "nonimmediate_operand") + (match_operand:DI 2 "general_operand"))) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_ZARCH") + (define_insn "*muldi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) @@ -6576,24 +6602,68 @@ [(set_attr "op_type" "RRE,RXY") (set_attr "type" "imuldi")]) -(define_insn "muldi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") - (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:DI 2 "general_operand" "d,K,T,Os")))] +(define_insn "*muldi3" + [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") + (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") + (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) + (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] "TARGET_ZARCH" "@ msgr\t%0,%2 + msgrkc\t%0,%1,%2 mghi\t%0,%h2 msg\t%0,%2 msgfi\t%0,%2" - [(set_attr "op_type" "RRE,RI,RXY,RIL") + [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") (set_attr "type" "imuldi") - (set_attr "cpu_facility" "*,*,*,z10")]) + (set_attr "cpu_facility" "*,arch12,*,*,z10")]) + +(define_insn "mulditi3" + [(set (match_operand:TI 0 "register_operand" "=d,d") + (mult:TI (sign_extend:TI + (match_operand:DI 1 "register_operand" "%d,0")) + (sign_extend:TI + (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] + "TARGET_ARCH12" + "@ + mgrk\t%0,%1,%2 + mg\t%0,%2" + [(set_attr "op_type" "RRF,RXY")]) + +; Combine likes op1 and op2 to be swapped sometimes. +(define_insn "mulditi3_2" + [(set (match_operand:TI 0 "register_operand" "=d,d") + (mult:TI (sign_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "%d,T")) + (sign_extend:TI + (match_operand:DI 2 "register_operand" " d,0"))))] + "TARGET_ARCH12" + "@ + mgrk\t%0,%1,%2 + mg\t%0,%1" + [(set_attr "op_type" "RRF,RXY")]) + +(define_insn "*muldi3_sign" + [(set (match_operand:DI 0 "register_operand" "=d") + (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) + (match_operand:DI 1 "register_operand" "0")))] + "TARGET_ARCH12" + "mgh\t%0,%2" + [(set_attr "op_type" "RXY")]) + ; ; mulsi3 instruction pattern(s). ; +(define_expand "mulsi3" + [(parallel + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") + (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") + (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) + (clobber (reg:CC CC_REGNUM))])] + "") + (define_insn "*mulsi3_sign" [(set (match_operand:SI 0 "register_operand" "=d,d") (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) @@ -6606,20 +6676,22 @@ (set_attr "type" "imulhi") (set_attr "cpu_facility" "*,z10")]) -(define_insn "mulsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") - (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] +(define_insn "*mulsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") + (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") + (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) + (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] "" "@ msr\t%0,%2 + msrkc\t%0,%1,%2 mhi\t%0,%h2 ms\t%0,%2 msy\t%0,%2 msfi\t%0,%2" - [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") - (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") - (set_attr "cpu_facility" "*,*,*,longdisp,z10")]) + [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") + (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") + (set_attr "cpu_facility" "*,arch12,*,*,longdisp,z10")]) ; ; mulsidi3 instruction pattern(s). |