diff options
Diffstat (limited to 'gcc/config/s390/s390.md')
-rw-r--r-- | gcc/config/s390/s390.md | 799 |
1 files changed, 627 insertions, 172 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 03ebfcde5b8..d33cc5c3267 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1,8 +1,9 @@ ;;- Machine description for GNU compiler -- S/390 / zSeries version. -;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 +;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 ;; Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and -;; Ulrich Weigand (uweigand@de.ibm.com). +;; Ulrich Weigand (uweigand@de.ibm.com) and +;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. @@ -38,6 +39,7 @@ ;; %Y: print shift count operand. ;; ;; %b: print integer X as if it's an unsigned byte. +;; %c: print integer X as if it's an signed byte. ;; %x: print integer X as if it's an unsigned halfword. ;; %h: print integer X as if it's a signed halfword. ;; %i: print the first nonzero HImode part of X. @@ -189,7 +191,7 @@ ;; Used to determine defaults for length and other attribute values. (define_attr "op_type" - "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR" + "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" (const_string "NN")) ;; Instruction type attribute used for scheduling. @@ -218,8 +220,8 @@ ;; Length in bytes. (define_attr "length" "" - (cond [(eq_attr "op_type" "E,RR") (const_int 2) - (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)] + (cond [(eq_attr "op_type" "E,RR") (const_int 2) + (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] (const_int 6))) @@ -228,10 +230,10 @@ ;; distinguish between g5 and g6, but there are differences between the two ;; CPUs could in theory be modeled. -(define_attr "cpu" "g5,g6,z900,z990,z9_109" +(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10" (const (symbol_ref "s390_tune"))) -(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp" +(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10" (const_string "standard")) (define_attr "enabled" "" @@ -256,6 +258,10 @@ (and (eq_attr "cpu_facility" "dfp") (ne (symbol_ref "TARGET_DFP") (const_int 0))) + (const_int 1) + + (and (eq_attr "cpu_facility" "z10") + (ne (symbol_ref "TARGET_Z10") (const_int 0))) (const_int 1)] (const_int 0))) @@ -282,6 +288,7 @@ (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") (SD "TARGET_HARD_DFP")]) (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) +(define_mode_iterator FPALL [TF DF SF TD DD SD]) (define_mode_iterator BFP [TF DF SF]) (define_mode_iterator DFP [TD DD]) (define_mode_iterator DFP_ALL [TD DD SD]) @@ -311,6 +318,7 @@ ;; This mode iterator allows the integer patterns to be defined from the ;; same template. (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) +(define_mode_iterator INTALL [TI DI SI HI QI]) ;; This iterator allows to unify all 'bCOND' expander patterns. (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered @@ -453,7 +461,6 @@ ;; Maximum unsigned integer that fits in MODE. (define_mode_attr max_uint [(HI "65535") (QI "255")]) - ;; ;;- Compare instructions. ;; @@ -539,14 +546,19 @@ (define_insn "*tstdi_sign" [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) - (const_int 32)) (const_int 32)) - (match_operand:DI 1 "const0_operand" ""))) - (set (match_operand:DI 2 "register_operand" "=d") + (compare + (ashiftrt:DI + (ashift:DI + (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) + (const_int 32)) (const_int 32)) + (match_operand:DI 1 "const0_operand" ""))) + (set (match_operand:DI 2 "register_operand" "=d,d") (sign_extend:DI (match_dup 0)))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" - "ltgfr\t%2,%0" - [(set_attr "op_type" "RRE")]) + "ltgfr\t%2,%0 + ltgf\t%2,%0" + [(set_attr "op_type" "RRE,RXY") + (set_attr "cpu_facility" "*,z10")]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_extimm" @@ -722,90 +734,159 @@ (define_insn "*cmpdi_ccs_sign" [(set (reg CC_REGNUM) - (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")) - (match_operand:DI 0 "register_operand" "d,d")))] + (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" + "d,RT,b")) + (match_operand:DI 0 "register_operand" "d, d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" "@ cgfr\t%0,%1 - cgf\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + cgf\t%0,%1 + cgfrl\t%0,%1" + [(set_attr "op_type" "RRE,RXY,RIL") + (set_attr "cpu_facility" "*,*,z10") + (set_attr "type" "*,*,larl")]) (define_insn "*cmpsi_ccs_sign" [(set (reg CC_REGNUM) - (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) - (match_operand:SI 0 "register_operand" "d,d")))] + (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) + (match_operand:SI 0 "register_operand" "d,d,d")))] "s390_match_ccmode(insn, CCSRmode)" "@ ch\t%0,%1 - chy\t%0,%1" - [(set_attr "op_type" "RX,RXY")]) + chy\t%0,%1 + chrl\t%0,%1" + [(set_attr "op_type" "RX,RXY,RIL") + (set_attr "cpu_facility" "*,*,z10") + (set_attr "type" "*,*,larl")]) + +(define_insn "*cmphi_ccs_z10" + [(set (reg CC_REGNUM) + (compare (match_operand:HI 0 "s_operand" "Q") + (match_operand:HI 1 "immediate_operand" "K")))] + "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" + "chhsi\t%0,%1" + [(set_attr "op_type" "SIL")]) + +(define_insn "*cmpdi_ccs_signhi_rl" + [(set (reg CC_REGNUM) + (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) + (match_operand:GPR 0 "register_operand" "d,d")))] + "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" + "@ + cgh\t%0,%1 + cghrl\t%0,%1" + [(set_attr "op_type" "RXY,RIL") + (set_attr "type" "*,larl")]) -; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg +; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl (define_insn "*cmp<mode>_ccs" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d") - (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))] + (compare (match_operand:GPR 0 "nonimmediate_operand" + "d,d,Q, d,d,d,d") + (match_operand:GPR 1 "general_operand" + "d,K,K,Os,R,T,b")))] "s390_match_ccmode(insn, CCSmode)" "@ c<g>r\t%0,%1 c<g>hi\t%0,%h1 + c<g>hsi\t%0,%h1 c<g>fi\t%0,%1 c<g>\t%0,%1 - c<y>\t%0,%1" - [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")]) + c<y>\t%0,%1 + c<g>rl\t%0,%1" + [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") + (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") + (set_attr "type" "*,*,*,*,*,*,larl")]) ; Compare (unsigned) instructions +(define_insn "*cmpsi_ccu_zerohi_rlsi" + [(set (reg CC_REGNUM) + (compare (zero_extend:SI (mem:HI (match_operand:SI 1 + "larl_operand" "X"))) + (match_operand:SI 0 "register_operand" "d")))] + "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" + "clhrl\t%0,%1" + [(set_attr "op_type" "RIL") + (set_attr "type" "larl")]) + +; clhrl, clghrl +(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" + [(set (reg CC_REGNUM) + (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 + "larl_operand" "X"))) + (match_operand:GPR 0 "register_operand" "d")))] + "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" + "cl<g>hrl\t%0,%1" + [(set_attr "op_type" "RIL") + (set_attr "type" "larl")]) + (define_insn "*cmpdi_ccu_zero" [(set (reg CC_REGNUM) - (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")) - (match_operand:DI 0 "register_operand" "d,d")))] + (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" + "d,RT,b")) + (match_operand:DI 0 "register_operand" "d, d,d")))] "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" "@ clgfr\t%0,%1 - clgf\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + clgf\t%0,%1 + clgfrl\t%0,%1" + [(set_attr "op_type" "RRE,RXY,RIL") + (set_attr "cpu_facility" "*,*,z10") + (set_attr "type" "*,*,larl")]) (define_insn "*cmpdi_ccu" [(set (reg CC_REGNUM) - (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ") - (match_operand:DI 1 "general_operand" "d,Op,RT,BQ,Q")))] + (compare (match_operand:DI 0 "nonimmediate_operand" + "d, d,d,Q, d, Q,BQ") + (match_operand:DI 1 "general_operand" + "d,Op,b,D,RT,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" "@ clgr\t%0,%1 clgfi\t%0,%1 + clgrl\t%0,%1 + clghsi\t%0,%x1 clg\t%0,%1 # #" - [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")]) + [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") + (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") + (set_attr "type" "*,*,larl,*,*,*,*")]) (define_insn "*cmpsi_ccu" [(set (reg CC_REGNUM) - (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ") - (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))] + (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") + (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] "s390_match_ccmode (insn, CCUmode)" "@ clr\t%0,%1 clfi\t%0,%o1 + clrl\t%0,%1 + clfhsi\t%0,%x1 cl\t%0,%1 cly\t%0,%1 # #" - [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")]) + [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") + (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") + (set_attr "type" "*,*,larl,*,*,*,*,*")]) (define_insn "*cmphi_ccu" [(set (reg CC_REGNUM) - (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") - (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] + (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") + (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) && !register_operand (operands[1], HImode)" "@ clm\t%0,3,%S1 clmy\t%0,3,%S1 + clhhsi\t%0,%1 # #" - [(set_attr "op_type" "RS,RSY,SS,SS")]) + [(set_attr "op_type" "RS,RSY,SIL,SS,SS") + (set_attr "cpu_facility" "*,*,z10,*,*")]) (define_insn "*cmpqi_ccu" [(set (reg CC_REGNUM) @@ -881,6 +962,59 @@ [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimp<bfp>")]) + +; Compare and Branch instructions + +; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr +(define_insn "*cmp_and_br_signed_<mode>" + [(set (pc) + (if_then_else (match_operator 0 "s390_signed_integer_comparison" + [(match_operand:GPR 1 "register_operand" "d,d") + (match_operand:GPR 2 "nonmemory_operand" "d,C")]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10" +{ + if (get_attr_length (insn) == 6) + return which_alternative ? + "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; + else + return which_alternative ? + "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; +} + [(set_attr "op_type" "RIE") + (set_attr "type" "branch") + (set (attr "length") + (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) + (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg + ; 10 byte for cgr/jg + +; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr +(define_insn "*cmp_and_br_unsigned_<mode>" + [(set (pc) + (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" + [(match_operand:GPR 1 "register_operand" "d,d") + (match_operand:GPR 2 "nonmemory_operand" "d,I")]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10" +{ + if (get_attr_length (insn) == 6) + return which_alternative ? + "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; + else + return which_alternative ? + "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; +} + [(set_attr "op_type" "RIE") + (set_attr "type" "branch") + (set (attr "length") + (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) + (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg + ; 10 byte for clgr/jg + ;; ;;- Move instructions. ;; @@ -947,6 +1081,60 @@ ; Patterns used for secondary reloads ; +; z10 provides move instructions accepting larl memory operands. +; Unfortunately there is no such variant for QI, TI and FP mode moves. +; These patterns are also used for unaligned SI and DI accesses. + +(define_expand "reload<INTALL:mode><P:mode>_tomem_z10" + [(parallel [(match_operand:INTALL 0 "memory_operand" "") + (match_operand:INTALL 1 "register_operand" "=d") + (match_operand:P 2 "register_operand" "=&a")])] + "TARGET_Z10" +{ + s390_reload_symref_address (operands[1], operands[0], operands[2], 1); + DONE; +}) + +(define_expand "reload<INTALL:mode><P:mode>_toreg_z10" + [(parallel [(match_operand:INTALL 0 "register_operand" "=d") + (match_operand:INTALL 1 "memory_operand" "") + (match_operand:P 2 "register_operand" "=a")])] + "TARGET_Z10" +{ + s390_reload_symref_address (operands[0], operands[1], operands[2], 0); + DONE; +}) + +(define_expand "reload<FPALL:mode><P:mode>_tomem_z10" + [(parallel [(match_operand:FPALL 0 "memory_operand" "") + (match_operand:FPALL 1 "register_operand" "=d") + (match_operand:P 2 "register_operand" "=&a")])] + "TARGET_Z10" +{ + s390_reload_symref_address (operands[1], operands[0], operands[2], 1); + DONE; +}) + +(define_expand "reload<FPALL:mode><P:mode>_toreg_z10" + [(parallel [(match_operand:FPALL 0 "register_operand" "=d") + (match_operand:FPALL 1 "memory_operand" "") + (match_operand:P 2 "register_operand" "=a")])] + "TARGET_Z10" +{ + s390_reload_symref_address (operands[0], operands[1], operands[2], 0); + DONE; +}) + +(define_expand "reload<P:mode>_larl_odd_addend_z10" + [(parallel [(match_operand:P 0 "register_operand" "=d") + (match_operand:P 1 "larl_operand" "") + (match_operand:P 2 "register_operand" "=a")])] + "TARGET_Z10" +{ + s390_reload_larl_operand (operands[0], operands[1], operands[2]); + DONE; +}) + ; Handles loading a PLUS (load address) expression (define_expand "reload<mode>_plus" @@ -1016,11 +1204,11 @@ (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=d,d,d,d,d,d,d,d,f,d,d,d,d, - RT,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") + "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, + RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,?Q") (match_operand:DI 1 "general_operand" - "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,RT, - d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] + "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, + d,*f,R,T,*f,*f,d,K,t,d,t,Q,?Q"))] "TARGET_64BIT" "@ lghi\t%0,%h1 @@ -1034,6 +1222,7 @@ ldgr\t%0,%1 lgdr\t%0,%1 lay\t%0,%a1 + lgrl\t%0,%1 lgr\t%0,%1 lg\t%0,%1 stg\t%1,%0 @@ -1042,17 +1231,21 @@ ldy\t%0,%1 std\t%1,%0 stdy\t%1,%0 + stgrl\t%1,%0 + mvghi\t%0,%1 # # stam\t%1,%N1,%S0 lam\t%0,%N0,%S1 #" - [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RRE,RXY,RXY, - RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") - (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,lr,load,store, - floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*") + [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, + RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,SS") + (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, + floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, + *,*,*") (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, - *,*,*,*,*,longdisp,*,longdisp,*,*,*,*,*")]) + z10,*,*,*,*,*,longdisp,*,longdisp, + z10,z10,*,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1088,8 +1281,10 @@ s390_split_access_reg (operands[0], &operands[3], &operands[4]);") (define_insn "*movdi_31" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q") - (match_operand:DI 1 "general_operand" "Q,S,d,d,dPRT,d,*f,R,T,*f,*f,Q"))] + [(set (match_operand:DI 0 "nonimmediate_operand" + "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,Q,d") + (match_operand:DI 1 "general_operand" + " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,Q,b"))] "!TARGET_64BIT" "@ lm\t%0,%N0,%S1 @@ -1103,9 +1298,26 @@ ldy\t%0,%1 std\t%1,%0 stdy\t%1,%0 + # #" - [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")]) + [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS,*") + (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*") + (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,*,z10")]) + +; For a load from a symbol ref we can use one of the target registers +; together with larl to load the address. +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "memory_operand" ""))] + "!TARGET_64BIT && reload_completed && TARGET_Z10 + && larl_operand (XEXP (operands[1], 0), SImode)" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 0) (match_dup 1))] +{ + operands[2] = operand_subword (operands[0], 1, 0, DImode); + operands[3] = XEXP (operands[1], 0); + operands[1] = replace_equiv_address (operands[1], operands[2]); +}) (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") @@ -1223,9 +1435,9 @@ (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" - "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") + "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,?Q") (match_operand:SI 1 "general_operand" - "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] + "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q,?Q"))] "TARGET_ZARCH" "@ lhi\t%0,%h1 @@ -1233,6 +1445,7 @@ llill\t%0,%i1 iilf\t%0,%o1 lay\t%0,%a1 + lrl\t%0,%1 lr\t%0,%1 l\t%0,%1 ly\t%0,%1 @@ -1246,12 +1459,16 @@ ear\t%0,%1 sar\t%0,%1 stam\t%1,%1,%S0 + strl\t%1,%0 + mvhi\t%0,%1 lam\t%0,%0,%S1 #" - [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY, - RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") - (set_attr "type" "*,*,*,*,la,lr,load,load,store,store, - floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")]) + [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, + RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,SS") + (set_attr "type" "*,*,*,*,la,larl,lr,load,load,store,store, + floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,larl,*,*,*") + (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, + *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*")]) (define_insn "*movsi_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") @@ -1377,19 +1594,23 @@ }) (define_insn "*movhi" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") - (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,?Q") + (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,?Q"))] "" "@ lr\t%0,%1 lhi\t%0,%h1 lh\t%0,%1 lhy\t%0,%1 + lhrl\t%0,%1 sth\t%1,%0 sthy\t%1,%0 + sthrl\t%1,%0 + mvhhi\t%0,%1 #" - [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") - (set_attr "type" "lr,*,*,*,store,store,*")]) + [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,SS") + (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*") + (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*")]) (define_peephole2 [(set (match_operand:HI 0 "register_operand" "") @@ -2010,6 +2231,17 @@ ;; String instructions. ;; +(define_insn "*execute_rl" + [(match_parallel 0 "" + [(unspec [(match_operand 1 "register_operand" "a") + (match_operand 2 "" "") + (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] + "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" + "exrl\t%1,%3" + [(set_attr "op_type" "RIL") + (set_attr "type" "cs")]) + (define_insn "*execute" [(match_parallel 0 "" [(unspec [(match_operand 1 "register_operand" "a") @@ -2154,9 +2386,9 @@ ; (define_expand "movmem<mode>" - [(set (match_operand:BLK 0 "memory_operand" "") - (match_operand:BLK 1 "memory_operand" "")) - (use (match_operand:GPR 2 "general_operand" "")) + [(set (match_operand:BLK 0 "memory_operand" "") ; destination + (match_operand:BLK 1 "memory_operand" "")) ; source + (use (match_operand:GPR 2 "general_operand" "")) ; count (match_operand 3 "" "")] "" "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") @@ -2175,15 +2407,16 @@ "operands[3] = gen_rtx_SCRATCH (Pmode);") (define_insn "*movmem_short" - [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") - (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) - (use (match_operand 2 "nonmemory_operand" "n,a,a")) - (use (match_operand 3 "immediate_operand" "X,R,X")) - (clobber (match_scratch 4 "=X,X,&a"))] + [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") + (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) + (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) + (use (match_operand 3 "immediate_operand" "X,R,X,X")) + (clobber (match_scratch 4 "=X,X,X,&a"))] "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) && GET_MODE (operands[4]) == Pmode" "#" - [(set_attr "type" "cs")]) + [(set_attr "type" "cs") + (set_attr "cpu_facility" "*,*,z10,*")]) (define_split [(set (match_operand:BLK 0 "memory_operand" "") @@ -2216,6 +2449,20 @@ (match_operand:BLK 1 "memory_operand" "")) (use (match_operand 2 "register_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) + (clobber (scratch))] + "TARGET_Z10 && reload_completed" + [(parallel + [(unspec [(match_dup 2) (const_int 0) + (label_ref (match_dup 3))] UNSPEC_EXECUTE) + (set (match_dup 0) (match_dup 1)) + (use (const_int 1))])] + "operands[3] = gen_label_rtx ();") + +(define_split + [(set (match_operand:BLK 0 "memory_operand" "") + (match_operand:BLK 1 "memory_operand" "")) + (use (match_operand 2 "register_operand" "")) + (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_operand 3 "register_operand" ""))] "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) @@ -2247,11 +2494,11 @@ rtx len0 = gen_lowpart (Pmode, reg0); rtx len1 = gen_lowpart (Pmode, reg1); - emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); + emit_clobber (reg0); emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); emit_move_insn (len0, operands[2]); - emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); + emit_clobber (reg1); emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); emit_move_insn (len1, operands[2]); @@ -2354,16 +2601,17 @@ "operands[2] = gen_rtx_SCRATCH (Pmode);") (define_insn "*clrmem_short" - [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") + [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") (const_int 0)) - (use (match_operand 1 "nonmemory_operand" "n,a,a")) - (use (match_operand 2 "immediate_operand" "X,R,X")) - (clobber (match_scratch 3 "=X,X,&a")) + (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) + (use (match_operand 2 "immediate_operand" "X,R,X,X")) + (clobber (match_scratch 3 "=X,X,X,&a")) (clobber (reg:CC CC_REGNUM))] "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) && GET_MODE (operands[3]) == Pmode" "#" - [(set_attr "type" "cs")]) + [(set_attr "type" "cs") + (set_attr "cpu_facility" "*,*,z10,*")]) (define_split [(set (match_operand:BLK 0 "memory_operand" "") @@ -2400,6 +2648,22 @@ (const_int 0)) (use (match_operand 1 "register_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) + (clobber (scratch)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10 && reload_completed" + [(parallel + [(unspec [(match_dup 1) (const_int 0) + (label_ref (match_dup 3))] UNSPEC_EXECUTE) + (set (match_dup 0) (const_int 0)) + (use (const_int 1)) + (clobber (reg:CC CC_REGNUM))])] + "operands[3] = gen_label_rtx ();") + +(define_split + [(set (match_operand:BLK 0 "memory_operand" "") + (const_int 0)) + (use (match_operand 1 "register_operand" "")) + (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_operand 2 "register_operand" "")) (clobber (reg:CC CC_REGNUM))] "reload_completed && TARGET_CPU_ZARCH" @@ -2430,7 +2694,7 @@ rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); rtx len0 = gen_lowpart (Pmode, reg0); - emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); + emit_clobber (reg0); emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); emit_move_insn (len0, operands[1]); @@ -2495,15 +2759,16 @@ (define_insn "*cmpmem_short" [(set (reg:CCU CC_REGNUM) - (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") - (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) - (use (match_operand 2 "nonmemory_operand" "n,a,a")) - (use (match_operand 3 "immediate_operand" "X,R,X")) - (clobber (match_scratch 4 "=X,X,&a"))] + (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") + (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) + (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) + (use (match_operand 3 "immediate_operand" "X,R,X,X")) + (clobber (match_scratch 4 "=X,X,X,&a"))] "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) && GET_MODE (operands[4]) == Pmode" "#" - [(set_attr "type" "cs")]) + [(set_attr "type" "cs") + (set_attr "cpu_facility" "*,*,z10,*")]) (define_split [(set (reg:CCU CC_REGNUM) @@ -2539,6 +2804,21 @@ (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "register_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) + (clobber (scratch))] + "TARGET_Z10 && reload_completed" + [(parallel + [(unspec [(match_dup 2) (const_int 0) + (label_ref (match_dup 4))] UNSPEC_EXECUTE) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) + (use (const_int 1))])] + "operands[4] = gen_label_rtx ();") + +(define_split + [(set (reg:CCU CC_REGNUM) + (compare:CCU (match_operand:BLK 0 "memory_operand" "") + (match_operand:BLK 1 "memory_operand" ""))) + (use (match_operand 2 "register_operand" "")) + (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_operand 3 "register_operand" ""))] "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) @@ -2570,11 +2850,11 @@ rtx len0 = gen_lowpart (Pmode, reg0); rtx len1 = gen_lowpart (Pmode, reg1); - emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); + emit_clobber (reg0); emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); emit_move_insn (len0, operands[2]); - emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); + emit_clobber (reg1); emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); emit_move_insn (len1, operands[2]); @@ -2772,6 +3052,83 @@ FAIL; }) +(define_insn "*insv<mode>_z10" + [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") + (match_operand 1 "const_int_operand" "I") + (match_operand 2 "const_int_operand" "I")) + (match_operand:GPR 3 "nonimmediate_operand" "d")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10 + && (INTVAL (operands[1]) + INTVAL (operands[2])) <= + GET_MODE_BITSIZE (<MODE>mode)" +{ + int start = INTVAL (operands[2]); + int size = INTVAL (operands[1]); + int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); + + operands[2] = GEN_INT (offset + start); /* start bit position */ + operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ + operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - + start - size); /* left shift count */ + + return "risbg\t%0,%3,%b2,%b1,%b4"; +} + [(set_attr "op_type" "RIE")]) + +; and op1 with a mask being 1 for the selected bits and 0 for the rest +; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest +(define_insn "*insv<mode>_z10_noshift" + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") + (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") + (match_operand 2 "const_int_operand" "n")) + (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") + (match_operand 4 "const_int_operand" "n")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10 + && s390_contiguous_bitmask_p (INTVAL (operands[2]), + GET_MODE_BITSIZE (<MODE>mode), NULL, NULL) + && INTVAL (operands[2]) == ~(INTVAL (operands[4]))" + +{ + int start; + int size; + + s390_contiguous_bitmask_p (INTVAL (operands[2]), + GET_MODE_BITSIZE (<MODE>mode), &start, &size); + + operands[5] = GEN_INT (64 - start - size); /* start bit position */ + operands[6] = GEN_INT (64 - 1 - start); /* end bit position */ + operands[7] = const0_rtx; /* left shift count */ + + return "risbg\t%0,%1,%b5,%b6,%b7"; +} + [(set_attr "op_type" "RIE")]) + +; and op1 with a mask being 1 for the selected bits and 0 for the rest +(define_insn "*insv<mode>_or_z10_noshift" + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") + (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") + (match_operand 2 "const_int_operand" "n")) + (match_operand:GPR 3 "nonimmediate_operand" "0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10 + && s390_contiguous_bitmask_p (INTVAL (operands[2]), + GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)" +{ + int start; + int size; + + s390_contiguous_bitmask_p (INTVAL (operands[2]), + GET_MODE_BITSIZE (<MODE>mode), &start, &size); + + operands[4] = GEN_INT (64 - start - size); /* start bit position */ + operands[5] = GEN_INT (64 - 1 - start); /* end bit position */ + operands[6] = const0_rtx; /* left shift count */ + + return "rosbg\t%0,%1,%b4,%b5,%b6"; +} + [(set_attr "op_type" "RIE")]) + (define_insn "*insv<mode>_mem_reg" [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") (match_operand 1 "const_int_operand" "n,n") @@ -2858,7 +3215,7 @@ { if (!TARGET_64BIT) { - emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); + emit_clobber (operands[0]); emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); @@ -2867,13 +3224,16 @@ }) (define_insn "*extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")))] + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] "TARGET_64BIT" "@ lgfr\t%0,%1 - lgf\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + lgf\t%0,%1 + lgfrl\t%0,%1" + [(set_attr "op_type" "RRE,RXY,RIL") + (set_attr "type" "*,*,larl") + (set_attr "cpu_facility" "*,*,z10")]) ; ; extend(hi|qi)(si|di)2 instruction pattern(s). @@ -2908,13 +3268,16 @@ ; (define_insn "*extendhidi2_extimm" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,RT")))] + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] "TARGET_64BIT && TARGET_EXTIMM" "@ lghr\t%0,%1 - lgh\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + lgh\t%0,%1 + lghrl\t%0,%1" + [(set_attr "op_type" "RRE,RXY,RIL") + (set_attr "type" "*,*,larl") + (set_attr "cpu_facility" "extimm,extimm,z10")]) (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") @@ -2928,14 +3291,17 @@ ; (define_insn "*extendhisi2_extimm" - [(set (match_operand:SI 0 "register_operand" "=d,d,d") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))] + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] "TARGET_EXTIMM" "@ lhr\t%0,%1 lh\t%0,%1 - lhy\t%0,%1" - [(set_attr "op_type" "RRE,RX,RXY")]) + lhy\t%0,%1 + lhrl\t%0,%1" + [(set_attr "op_type" "RRE,RX,RXY,RIL") + (set_attr "type" "*,*,*,larl") + (set_attr "cpu_facility" "extimm,extimm,extimm,z10")]) (define_insn "*extendhisi2" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -2999,7 +3365,7 @@ { if (!TARGET_64BIT) { - emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); + emit_clobber (operands[0]); emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); DONE; @@ -3007,13 +3373,16 @@ }) (define_insn "*zero_extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")))] + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] "TARGET_64BIT" "@ llgfr\t%0,%1 - llgf\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + llgf\t%0,%1 + llgfrl\t%0,%1" + [(set_attr "op_type" "RRE,RXY,RIL") + (set_attr "type" "*,*,larl") + (set_attr "cpu_facility" "*,*,z10")]) ; ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). @@ -3112,6 +3481,19 @@ } }) +; llhrl, llghrl +(define_insn "*zero_extendhi<mode>2_z10" + [(set (match_operand:GPR 0 "register_operand" "=d,d,d") + (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] + "TARGET_Z10" + "@ + ll<g>hr\t%0,%1 + ll<g>h\t%0,%1 + ll<g>hrl\t%0,%1" + [(set_attr "op_type" "RXY,RRE,RIL") + (set_attr "type" "*,*,larl") + (set_attr "cpu_facility" "*,*,z10")]) + ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" [(set (match_operand:GPR 0 "register_operand" "=d,d") @@ -3624,7 +4006,7 @@ (define_expand "adddi3" [(parallel - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "nonimmediate_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) (clobber (reg:CC CC_REGNUM))])] @@ -3679,7 +4061,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn_and_split "*adddi3_31z" - [(set (match_operand:DI 0 "register_operand" "=&d") + [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] @@ -3704,7 +4086,7 @@ operands[8] = operand_subword (operands[2], 1, 0, DImode);") (define_insn_and_split "*adddi3_31" - [(set (match_operand:DI 0 "register_operand" "=&d") + [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] @@ -3741,7 +4123,7 @@ (define_expand "addsi3" [(parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "nonimmediate_operand" "") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (reg:CC CC_REGNUM))])] @@ -3763,11 +4145,11 @@ ; add(di|si)3 instruction pattern(s). ; -; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag +; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi (define_insn "*add<mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d") - (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) ) + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS") + (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") + (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) ) (clobber (reg:CC CC_REGNUM))] "" "@ @@ -3776,16 +4158,18 @@ al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 a<g>\t%0,%2 - a<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")]) + a<y>\t%0,%2 + a<g>si\t%0,%c2" + [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")]) -; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg +; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry1_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,Op,On,R,T")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") + (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) (match_dup 1))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ @@ -3793,8 +4177,10 @@ al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 al<g>\t%0,%2 - al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")]) + al<y>\t%0,%2 + al<g>si\t%0,%c2" + [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry1_cconly" @@ -3810,13 +4196,13 @@ al<y>\t%0,%2" [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) -; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg +; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry2_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,Op,On,R,T")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") + (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) (match_dup 2))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ @@ -3824,8 +4210,10 @@ al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 al<g>\t%0,%2 - al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")]) + al<y>\t%0,%2 + al<g>si\t%0,%c2" + [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry2_cconly" @@ -3841,13 +4229,13 @@ al<y>\t%0,%2" [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) -; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg +; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,Op,On,R,T")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") + (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ @@ -3855,8 +4243,10 @@ al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 al<g>\t%0,%2 - al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")]) + al<y>\t%0,%2 + al<g>si\t%0,%c2" + [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly" @@ -3885,22 +4275,25 @@ al<y>\t%0,%2" [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) -; ahi, afi, aghi, agfi +; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add<mode>3_imm_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "const_int_operand" "K,Os")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0") + (match_operand:GPR 2 "const_int_operand" "K,Os,C")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCAmode) && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") - || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")) + || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") + || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" "@ a<g>hi\t%0,%h2 - a<g>fi\t%0,%2" - [(set_attr "op_type" "RI,RIL")]) + a<g>fi\t%0,%2 + a<g>si\t%0,%c2" + [(set_attr "op_type" "RI,RIL,SIY") + (set_attr "cpu_facility" "*,extimm,z10")]) ; ; add(tf|df|sf|td|dd)3 instruction pattern(s). @@ -4499,69 +4892,78 @@ (define_insn "*muldi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") - (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,RT")) + (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0")))] "TARGET_64BIT" "@ msgfr\t%0,%2 msgf\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "type" "imuldi")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "type" "imuldi")]) (define_insn "muldi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:DI 2 "general_operand" "d,K,RT")))] + [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") + (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") + (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] "TARGET_64BIT" "@ msgr\t%0,%2 mghi\t%0,%h2 - msg\t%0,%2" - [(set_attr "op_type" "RRE,RI,RXY") - (set_attr "type" "imuldi")]) + msg\t%0,%2 + msgfi\t%0,%2" + [(set_attr "op_type" "RRE,RI,RXY,RIL") + (set_attr "type" "imuldi") + (set_attr "cpu_facility" "*,*,*,z10")]) ; ; mulsi3 instruction pattern(s). ; (define_insn "*mulsi3_sign" - [(set (match_operand:SI 0 "register_operand" "=d") - (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) - (match_operand:SI 1 "register_operand" "0")))] + [(set (match_operand:SI 0 "register_operand" "=d,d") + (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) + (match_operand:SI 1 "register_operand" "0,0")))] "" - "mh\t%0,%2" - [(set_attr "op_type" "RX") - (set_attr "type" "imulhi")]) + "@ + mh\t%0,%2 + mhy\t%0,%2" + [(set_attr "op_type" "RX,RXY") + (set_attr "type" "imulhi") + (set_attr "cpu_facility" "*,z10")]) (define_insn "mulsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") - (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "d,K,R,T")))] + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") + (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") + (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] "" "@ msr\t%0,%2 mhi\t%0,%h2 ms\t%0,%2 - msy\t%0,%2" - [(set_attr "op_type" "RRE,RI,RX,RXY") - (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) + msy\t%0,%2 + msfi\t%0,%2" + [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") + (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") + (set_attr "cpu_facility" "*,*,*,*,z10")]) ; ; mulsidi3 instruction pattern(s). ; (define_insn "mulsidi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") + [(set (match_operand:DI 0 "register_operand" "=d,d,d") (mult:DI (sign_extend:DI - (match_operand:SI 1 "register_operand" "%0,0")) + (match_operand:SI 1 "register_operand" "%0,0,0")) (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] + (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] "!TARGET_64BIT" "@ mr\t%0,%2 - m\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "type" "imulsi")]) + m\t%0,%2 + mfy\t%0,%2" + [(set_attr "op_type" "RR,RX,RXY") + (set_attr "type" "imulsi") + (set_attr "cpu_facility" "*,*,z10")]) ; ; umulsidi3 instruction pattern(s). @@ -4714,7 +5116,7 @@ gen_rtx_ZERO_EXTEND (TImode, div_equal)); operands[4] = gen_reg_rtx(TImode); - emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); + emit_clobber (operands[4]); emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); @@ -4832,7 +5234,7 @@ gen_rtx_ZERO_EXTEND (DImode, div_equal)); operands[4] = gen_reg_rtx(DImode); - emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); + emit_clobber (operands[4]); emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); @@ -6758,6 +7160,32 @@ [(set_attr "op_type" "RI") (set_attr "type" "branch")]) +; crt, cgrt, cit, cgit +(define_insn "*cmp_and_trap_signed_int<mode>" + [(trap_if (match_operator 0 "s390_signed_integer_comparison" + [(match_operand:GPR 1 "register_operand" "d,d") + (match_operand:GPR 2 "nonmemory_operand" "d,K")]) + (const_int 0))] + "TARGET_Z10" + "@ + c<g>rt%C0\t%1,%2 + c<g>it%C0\t%1,%h2" + [(set_attr "op_type" "RRF,RIE") + (set_attr "type" "branch")]) + +; clrt, clgrt, clfit, clgit +(define_insn "*cmp_and_trap_unsigned_int<mode>" + [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" + [(match_operand:GPR 1 "register_operand" "d,d") + (match_operand:GPR 2 "nonmemory_operand" "d,D")]) + (const_int 0))] + "TARGET_Z10" + "@ + cl<g>rt%C0\t%1,%2 + cl<gf>it%C0\t%1,%x2" + [(set_attr "op_type" "RRF,RIE") + (set_attr "type" "branch")]) + ;; ;;- Loop instructions. ;; @@ -7576,7 +8004,7 @@ "flag_pic" { emit_insn (s390_load_got ()); - emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); + emit_use (pic_offset_table_rtx); DONE; }) @@ -7659,7 +8087,7 @@ if (temp) emit_move_insn (s390_back_chain_rtx (), temp); - emit_insn (gen_rtx_USE (VOIDmode, base)); + emit_use (base); DONE; }) @@ -7904,3 +8332,30 @@ "" "" [(set_attr "length" "0")]) + + +; +; Data prefetch patterns +; + +(define_insn "prefetch" + [(prefetch (match_operand 0 "address_operand" "UW,X") + (match_operand:SI 1 "const_int_operand" "n,n") + (match_operand:SI 2 "const_int_operand" "n,n"))] + "TARGET_Z10" +{ + if (larl_operand (operands[0], Pmode)) + return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; + + if (s390_mem_constraint ("W", operands[0]) + || s390_mem_constraint ("U", operands[0])) + return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; + + /* This point might be reached if op0 is a larl operand with an + uneven addend. In this case we simply omit issuing a prefetch + instruction. */ + + return ""; + +} [(set_attr "type" "load,larl") + (set_attr "op_type" "RXY,RIL")]) |