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Diffstat (limited to 'gcc/config/sparc/sparc.md')
-rw-r--r--gcc/config/sparc/sparc.md88
1 files changed, 50 insertions, 38 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 4024290d436..4c66a7867fa 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2062,9 +2062,9 @@
(define_insn "*movdi_insn_sp32_v9"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f,?e,?e,?W")
+ "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
(match_operand:DI 1 "input_operand"
- " J,J,U,T,r,o,i,r, f, T, o, f, f, e, W, e"))]
+ " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
"! TARGET_ARCH64 && TARGET_V9
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
@@ -2080,13 +2080,12 @@
ldd\t%1, %0
#
#
- #
fmovd\\t%1, %0
ldd\\t%1, %0
std\\t%1, %0"
- [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*,fpmove,fpload,fpstore")
- (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2,*,*,*")
- (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
+ [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
+ (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
+ (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
(define_insn "*movdi_insn_sp32"
[(set (match_operand:DI 0 "nonimmediate_operand"
@@ -2425,7 +2424,14 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "! TARGET_ARCH64 && reload_completed"
+ "reload_completed
+ && (! TARGET_V9
+ || (! TARGET_ARCH64
+ && ((GET_CODE (operands[0]) == REG
+ && REGNO (operands[0]) < 32)
+ || (GET_CODE (operands[0]) == SUBREG
+ && GET_CODE (SUBREG_REG (operands[0])) == REG
+ && REGNO (SUBREG_REG (operands[0])) < 32))))"
[(clobber (const_int 0))]
{
rtx set_dest = operands[0];
@@ -5283,9 +5289,12 @@
if (TARGET_V8PLUS)
emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
operands[2]));
- else
+ else if (TARGET_ARCH32)
emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1],
operands[2]));
+ else
+ emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1],
+ operands[2]));
DONE;
}
if (TARGET_V8PLUS)
@@ -5314,7 +5323,7 @@
(define_insn "const_mulsidi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h,r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (match_operand:SI 2 "small_int" "I,I")))
+ (match_operand:DI 2 "small_int" "I,I")))
(clobber (match_scratch:SI 3 "=X,&h"))]
"TARGET_V8PLUS"
"@
@@ -5355,7 +5364,7 @@
(define_insn "const_mulsidi3_sp32"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:SI 2 "small_int" "I")))]
+ (match_operand:DI 2 "small_int" "I")))]
"TARGET_HARD_MUL32"
{
return TARGET_SPARCLET
@@ -5372,7 +5381,7 @@
(define_insn "const_mulsidi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:SI 2 "small_int" "I")))]
+ (match_operand:DI 2 "small_int" "I")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"smul\t%1, %2, %0"
[(set_attr "type" "imul")])
@@ -5444,7 +5453,7 @@
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (match_operand 2 "small_int" "i,i"))
+ (match_operand:DI 2 "small_int" "i,i"))
(match_operand:SI 3 "const_int_operand" "i,i"))))
(clobber (match_scratch:SI 4 "=X,&h"))]
"TARGET_V8PLUS"
@@ -5471,7 +5480,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:SI 2 "register_operand" "r"))
+ (match_operand:DI 2 "small_int" "i"))
(const_int 32))))]
"TARGET_HARD_MUL32"
"smul\t%1, %2, %%g0\n\trd\t%%y, %0"
@@ -5489,9 +5498,12 @@
if (TARGET_V8PLUS)
emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
operands[2]));
- else
+ else if (TARGET_ARCH32)
emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1],
operands[2]));
+ else
+ emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1],
+ operands[2]));
DONE;
}
if (TARGET_V8PLUS)
@@ -5546,12 +5558,12 @@
(define_insn "const_umulsidi3_sp32"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:SI 2 "uns_small_int" "")))]
+ (match_operand:DI 2 "uns_small_int" "")))]
"TARGET_HARD_MUL32"
{
return TARGET_SPARCLET
- ? "umuld\t%1, %2, %L0"
- : "umul\t%1, %2, %L0\n\trd\t%%y, %H0";
+ ? "umuld\t%1, %s2, %L0"
+ : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0";
}
[(set (attr "type")
(if_then_else (eq_attr "isa" "sparclet")
@@ -5563,21 +5575,21 @@
(define_insn "const_umulsidi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:SI 2 "uns_small_int" "")))]
+ (match_operand:DI 2 "uns_small_int" "")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
- "umul\t%1, %2, %0"
+ "umul\t%1, %s2, %0"
[(set_attr "type" "imul")])
;; XXX
(define_insn "const_umulsidi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h,r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (match_operand:SI 2 "uns_small_int" "")))
+ (match_operand:DI 2 "uns_small_int" "")))
(clobber (match_scratch:SI 3 "=X,h"))]
"TARGET_V8PLUS"
"@
- umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
- umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
+ umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0
+ umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
[(set_attr "type" "multi")
(set_attr "length" "2,3")])
@@ -5630,13 +5642,13 @@
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (match_operand:SI 2 "uns_small_int" ""))
+ (match_operand:DI 2 "uns_small_int" ""))
(match_operand:SI 3 "const_int_operand" "i,i"))))
(clobber (match_scratch:SI 4 "=X,h"))]
"TARGET_V8PLUS"
"@
- umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
- umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
+ umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0
+ umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
@@ -5657,10 +5669,10 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:SI 2 "uns_small_int" ""))
+ (match_operand:DI 2 "uns_small_int" ""))
(const_int 32))))]
"TARGET_HARD_MUL32"
- "umul\t%1, %2, %%g0\n\trd\t%%y, %0"
+ "umul\t%1, %s2, %%g0\n\trd\t%%y, %0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
@@ -7246,7 +7258,7 @@
== INSN_ADDRESSES (INSN_UID (insn))))
return "b\t%l0%#";
else
- return TARGET_V9 ? "ba,pt%*\t%%xcc, %l0%(" : "b%*\t%l0%(";
+ return TARGET_V9 ? "ba%*,pt\t%%xcc, %l0%(" : "b%*\t%l0%(";
}
[(set_attr "type" "uncond_branch")])
@@ -7949,7 +7961,7 @@
&& mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
[(set (match_dup 0)
(const_int 0))]
- "operands[0] = change_address (operands[0], DImode, NULL);")
+ "operands[0] = widen_memory_access (operands[0], DImode, 0);")
(define_peephole2
[(set (match_operand:SI 0 "memory_operand" "")
@@ -7960,7 +7972,7 @@
&& mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
[(set (match_dup 1)
(const_int 0))]
- "operands[1] = change_address (operands[1], DImode, NULL);")
+ "operands[1] = widen_memory_access (operands[1], DImode, 0);")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
@@ -7971,7 +7983,7 @@
&& mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
[(set (match_dup 0)
(match_dup 1))]
- "operands[1] = change_address (operands[1], DImode, NULL);
+ "operands[1] = widen_memory_access (operands[1], DImode, 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));")
(define_peephole2
@@ -7983,7 +7995,7 @@
&& mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
[(set (match_dup 0)
(match_dup 1))]
- "operands[0] = change_address (operands[0], DImode, NULL);
+ "operands[0] = widen_memory_access (operands[0], DImode, 0);
operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
(define_peephole2
@@ -7995,7 +8007,7 @@
&& mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
[(set (match_dup 0)
(match_dup 1))]
- "operands[1] = change_address (operands[1], DFmode, NULL);
+ "operands[1] = widen_memory_access (operands[1], DFmode, 0);
operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));")
(define_peephole2
@@ -8007,7 +8019,7 @@
&& mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
[(set (match_dup 0)
(match_dup 1))]
- "operands[0] = change_address (operands[0], DFmode, NULL);
+ "operands[0] = widen_memory_access (operands[0], DFmode, 0);
operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));")
(define_peephole2
@@ -8019,7 +8031,7 @@
&& mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
[(set (match_dup 2)
(match_dup 3))]
- "operands[3] = change_address (operands[3], DImode, NULL);
+ "operands[3] = widen_memory_access (operands[3], DImode, 0);
operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));")
(define_peephole2
@@ -8031,7 +8043,7 @@
&& mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
[(set (match_dup 2)
(match_dup 3))]
- "operands[2] = change_address (operands[2], DImode, NULL);
+ "operands[2] = widen_memory_access (operands[2], DImode, 0);
operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
")
@@ -8044,7 +8056,7 @@
&& mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
[(set (match_dup 2)
(match_dup 3))]
- "operands[3] = change_address (operands[3], DFmode, NULL);
+ "operands[3] = widen_memory_access (operands[3], DFmode, 0);
operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));")
(define_peephole2
@@ -8056,7 +8068,7 @@
&& mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
[(set (match_dup 2)
(match_dup 3))]
- "operands[2] = change_address (operands[2], DFmode, NULL);
+ "operands[2] = widen_memory_access (operands[2], DFmode, 0);
operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));")
;; Optimize the case of following a reg-reg move with a test
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 13:40:36 +0000