diff options
Diffstat (limited to 'gcc/config')
44 files changed, 1104 insertions, 569 deletions
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index b6c0d0a8eb6..c083cad5327 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -427,6 +427,8 @@ bool aarch64_is_long_call_p (rtx); bool aarch64_is_noplt_call_p (rtx); bool aarch64_label_mentioned_p (rtx); void aarch64_declare_function_name (FILE *, const char*, tree); +void aarch64_asm_output_alias (FILE *, const tree, const tree); +void aarch64_asm_output_external (FILE *, tree, const char*); bool aarch64_legitimate_pic_operand_p (rtx); bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx); bool aarch64_masks_and_shift_for_bfi_p (scalar_int_mode, unsigned HOST_WIDE_INT, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 14259439c90..82e9b1fbfd8 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -15276,6 +15276,19 @@ aarch64_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global) return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type; } +/* Output .variant_pcs for aarch64_vector_pcs function symbols. */ + +static void +aarch64_asm_output_variant_pcs (FILE *stream, const tree decl, const char* name) +{ + if (aarch64_simd_decl_p (decl)) + { + fprintf (stream, "\t.variant_pcs\t"); + assemble_name (stream, name); + fprintf (stream, "\n"); + } +} + /* The last .arch and .tune assembly strings that we printed. */ static std::string aarch64_last_printed_arch_string; static std::string aarch64_last_printed_tune_string; @@ -15325,11 +15338,34 @@ aarch64_declare_function_name (FILE *stream, const char* name, aarch64_last_printed_tune_string = this_tune->name; } + aarch64_asm_output_variant_pcs (stream, fndecl, name); + /* Don't forget the type directive for ELF. */ ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); ASM_OUTPUT_LABEL (stream, name); } +/* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */ + +void +aarch64_asm_output_alias (FILE *stream, const tree decl, const tree target) +{ + const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); + const char *value = IDENTIFIER_POINTER (target); + aarch64_asm_output_variant_pcs (stream, decl, name); + ASM_OUTPUT_DEF (stream, name, value); +} + +/* Implement ASM_OUTPUT_EXTERNAL. Output .variant_pcs for undefined + function symbol references. */ + +void +aarch64_asm_output_external (FILE *stream, tree decl, const char* name) +{ + default_elf_asm_output_external (stream, decl, name); + aarch64_asm_output_variant_pcs (stream, decl, name); +} + /* Implements TARGET_ASM_FILE_START. Output the assembly header. */ static void @@ -18126,19 +18162,21 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, /* Sort the operands. */ qsort (temp_operands, 4, 2 * sizeof (rtx *), aarch64_ldrstr_offset_compare); + /* Copy the memory operands so that if we have to bail for some + reason the original addresses are unchanged. */ if (load) { - mem_1 = temp_operands[1]; - mem_2 = temp_operands[3]; - mem_3 = temp_operands[5]; - mem_4 = temp_operands[7]; + mem_1 = copy_rtx (temp_operands[1]); + mem_2 = copy_rtx (temp_operands[3]); + mem_3 = copy_rtx (temp_operands[5]); + mem_4 = copy_rtx (temp_operands[7]); } else { - mem_1 = temp_operands[0]; - mem_2 = temp_operands[2]; - mem_3 = temp_operands[4]; - mem_4 = temp_operands[6]; + mem_1 = copy_rtx (temp_operands[0]); + mem_2 = copy_rtx (temp_operands[2]); + mem_3 = copy_rtx (temp_operands[4]); + mem_4 = copy_rtx (temp_operands[6]); gcc_assert (code == UNKNOWN); } diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 7bd3bf525dd..fc6df970c2e 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -505,6 +505,15 @@ extern unsigned aarch64_architecture_version; #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ aarch64_declare_function_name (STR, NAME, DECL) +/* Output assembly strings for alias definition. */ +#define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ + aarch64_asm_output_alias (STR, DECL, TARGET) + +/* Output assembly strings for undefined extern symbols. */ +#undef ASM_OUTPUT_EXTERNAL +#define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ + aarch64_asm_output_external (STR, DECL, NAME) + /* For EH returns X4 contains the stack adjustment. */ #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 2f5753b02fa..ee1f70bbb51 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -5971,130 +5971,47 @@ arc_legitimize_tls_address (rtx addr, enum tls_model model) } } -/* Legitimize a pic address reference in ORIG. - The return value is the legitimated address. - If OLDX is non-zero, it is the target to assign the address to first. */ +/* Return true if SYMBOL_REF X binds locally. */ -static rtx -arc_legitimize_pic_address (rtx orig, rtx oldx) +static bool +arc_symbol_binds_local_p (const_rtx x) { - rtx addr = orig; - rtx pat = orig; - rtx base; + return (SYMBOL_REF_DECL (x) + ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) + : SYMBOL_REF_LOCAL_P (x)); +} - if (oldx == orig) - oldx = NULL; +/* Legitimize a pic address reference in ADDR. The return value is + the legitimated address. */ - if (GET_CODE (addr) == LABEL_REF) - ; /* Do nothing. */ - else if (GET_CODE (addr) == SYMBOL_REF) +static rtx +arc_legitimize_pic_address (rtx addr) +{ + if (!flag_pic) + return addr; + + switch (GET_CODE (addr)) { - enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); - if (model != 0) - return arc_legitimize_tls_address (addr, model); - else if (!flag_pic) - return orig; - else if (CONSTANT_POOL_ADDRESS_P (addr) || SYMBOL_REF_LOCAL_P (addr)) - return arc_unspec_offset (addr, ARC_UNSPEC_GOTOFFPC); + case SYMBOL_REF: + /* TLS symbols are handled in different place. */ + if (SYMBOL_REF_TLS_MODEL (addr)) + return addr; /* This symbol must be referenced via a load from the Global Offset Table (@GOTPC). */ - pat = arc_unspec_offset (addr, ARC_UNSPEC_GOT); - pat = gen_const_mem (Pmode, pat); - - if (oldx == NULL) - oldx = gen_reg_rtx (Pmode); - - emit_move_insn (oldx, pat); - pat = oldx; - } - else - { - if (GET_CODE (addr) == CONST) - { - addr = XEXP (addr, 0); - if (GET_CODE (addr) == UNSPEC) - { - /* Check that the unspec is one of the ones we generate? */ - return orig; - } - /* fwprop is placing in the REG_EQUIV notes constant pic - unspecs expressions. Then, loop may use these notes for - optimizations resulting in complex patterns that are not - supported by the current implementation. The following - two if-cases are simplifying the complex patters to - simpler ones. */ - else if (GET_CODE (addr) == MINUS) - { - rtx op0 = XEXP (addr, 0); - rtx op1 = XEXP (addr, 1); - gcc_assert (oldx); - gcc_assert (GET_CODE (op1) == UNSPEC); - - emit_move_insn (oldx, - gen_rtx_CONST (SImode, - arc_legitimize_pic_address (op1, - NULL_RTX))); - emit_insn (gen_rtx_SET (oldx, gen_rtx_MINUS (SImode, op0, oldx))); - return oldx; - - } - else if (GET_CODE (addr) != PLUS) - { - rtx tmp = XEXP (addr, 0); - enum rtx_code code = GET_CODE (addr); - - /* It only works for UNARY operations. */ - gcc_assert (UNARY_P (addr)); - gcc_assert (GET_CODE (tmp) == UNSPEC); - gcc_assert (oldx); - - emit_move_insn - (oldx, - gen_rtx_CONST (SImode, - arc_legitimize_pic_address (tmp, - NULL_RTX))); - - emit_insn (gen_rtx_SET (oldx, - gen_rtx_fmt_ee (code, SImode, - oldx, const0_rtx))); - - return oldx; - } - else - { - gcc_assert (GET_CODE (addr) == PLUS); - if (GET_CODE (XEXP (addr, 0)) == UNSPEC) - return orig; - } - } - - if (GET_CODE (addr) == PLUS) - { - rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); + if (!arc_symbol_binds_local_p (addr)) + return gen_const_mem (Pmode, arc_unspec_offset (addr, ARC_UNSPEC_GOT)); - base = arc_legitimize_pic_address (op0, oldx); - pat = arc_legitimize_pic_address (op1, - base == oldx ? NULL_RTX : oldx); - - if (base == op0 && pat == op1) - return orig; + /* Local symb: use @pcl to access it. */ + /* Fall through. */ + case LABEL_REF: + return arc_unspec_offset (addr, ARC_UNSPEC_GOTOFFPC); - if (GET_CODE (pat) == CONST_INT) - pat = plus_constant (Pmode, base, INTVAL (pat)); - else - { - if (GET_CODE (pat) == PLUS && CONSTANT_P (XEXP (pat, 1))) - { - base = gen_rtx_PLUS (Pmode, base, XEXP (pat, 0)); - pat = XEXP (pat, 1); - } - pat = gen_rtx_PLUS (Pmode, base, pat); - } - } + default: + break; } - return pat; + return addr; } /* Output address constant X to FILE, taking PIC into account. */ @@ -6256,28 +6173,6 @@ arc_output_pic_addr_const (FILE * file, rtx x, int code) } } -#define SYMBOLIC_CONST(X) \ -(GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == LABEL_REF \ - || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) - -/* Emit insns to move operands[1] into operands[0]. */ - -static void -prepare_pic_move (rtx *operands, machine_mode) -{ - if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]) - && flag_pic) - operands[1] = force_reg (Pmode, operands[1]); - else - { - rtx temp = (reload_in_progress ? operands[0] - : flag_pic? gen_reg_rtx (Pmode) : NULL_RTX); - operands[1] = arc_legitimize_pic_address (operands[1], temp); - } -} - - /* The function returning the number of words, at the beginning of an argument, must be put in registers. The returned value must be zero for arguments that are passed entirely in registers or that @@ -9053,54 +8948,37 @@ prepare_move_operands (rtx *operands, machine_mode mode) } } - if (mode == SImode && SYMBOLIC_CONST (operands[1])) + if (GET_CODE (operands[1]) == SYMBOL_REF) { - prepare_pic_move (operands, SImode); - - /* Disable any REG_EQUALs associated with the symref - otherwise the optimization pass undoes the work done - here and references the variable directly. */ + enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); + if (MEM_P (operands[0])) + operands[1] = force_reg (mode, operands[1]); + else if (model) + operands[1] = arc_legitimize_tls_address (operands[1], model); } + operands[1] = arc_legitimize_pic_address (operands[1]); + + /* Store instructions are limited, they only accept as address an + immediate, a register or a register plus a small immediate. */ if (MEM_P (operands[0]) - && !(reload_in_progress || reload_completed)) + && !move_dest_operand (operands[0], mode)) { - operands[1] = force_reg (mode, operands[1]); - if (!move_dest_operand (operands[0], mode)) - { - rtx addr = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); - /* This is like change_address_1 (operands[0], mode, 0, 1) , - except that we can't use that function because it is static. */ - rtx pat = change_address (operands[0], mode, addr); - MEM_COPY_ATTRIBUTES (pat, operands[0]); - operands[0] = pat; - } - if (!cse_not_expected) - { - rtx pat = XEXP (operands[0], 0); - - pat = arc_legitimize_address_0 (pat, pat, mode); - if (pat) - { - pat = change_address (operands[0], mode, pat); - MEM_COPY_ATTRIBUTES (pat, operands[0]); - operands[0] = pat; - } - } + rtx tmp0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + rtx tmp1 = change_address (operands[0], mode, tmp0); + MEM_COPY_ATTRIBUTES (tmp1, operands[0]); + operands[0] = tmp1; } - if (MEM_P (operands[1]) && !cse_not_expected) - { - rtx pat = XEXP (operands[1], 0); - - pat = arc_legitimize_address_0 (pat, pat, mode); - if (pat) - { - pat = change_address (operands[1], mode, pat); - MEM_COPY_ATTRIBUTES (pat, operands[1]); - operands[1] = pat; - } - } + /* Check if it is constant but it is not legitimized. */ + if (CONSTANT_P (operands[1]) + && !arc_legitimate_constant_p (mode, operands[1])) + operands[1] = force_reg (mode, XEXP (operands[1], 0)); + else if (MEM_P (operands[0]) + && ((CONSTANT_P (operands[1]) + && !satisfies_constraint_Cm3 (operands[1])) + || MEM_P (operands[1]))) + operands[1] = force_reg (mode, operands[1]); return false; } @@ -9572,11 +9450,10 @@ arc_legitimize_address_0 (rtx x, rtx oldx ATTRIBUTE_UNUSED, { rtx addr, inner; - if (flag_pic && SYMBOLIC_CONST (x)) - (x) = arc_legitimize_pic_address (x, 0); addr = x; if (GET_CODE (addr) == CONST) addr = XEXP (addr, 0); + if (GET_CODE (addr) == PLUS && CONST_INT_P (XEXP (addr, 1)) && ((GET_CODE (XEXP (addr, 0)) == SYMBOL_REF @@ -9607,13 +9484,6 @@ arc_legitimize_address_0 (rtx x, rtx oldx ATTRIBUTE_UNUSED, static rtx arc_legitimize_address (rtx orig_x, rtx oldx, machine_mode mode) { - if (GET_CODE (orig_x) == SYMBOL_REF) - { - enum tls_model model = SYMBOL_REF_TLS_MODEL (orig_x); - if (model != 0) - return arc_legitimize_tls_address (orig_x, model); - } - rtx new_x = arc_legitimize_address_0 (orig_x, oldx, mode); if (new_x) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ce1004c1b56..78e304d4c71 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -671,7 +671,9 @@ core_3, archs4x, archs4xd, archs4xd_slow" [(set (match_operand:QI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w, w,???w,h, w,Rcq, S,!*x, r,r, Ucm,m,???m, m,Usc") (match_operand:QI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL, I,?Rac,i,?i, T,Rcq,Usd,Ucm,m,?Rac,c,?Rac,Cm3,i"))] "register_operand (operands[0], QImode) - || register_operand (operands[1], QImode)" + || register_operand (operands[1], QImode) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], QImode))" "@ mov%? %0,%1%& mov%? %0,%1%& @@ -713,7 +715,9 @@ core_3, archs4x, archs4xd, archs4xd_slow" /* Don't use a LIMM that we could load with a single insn - we loose delay-slot filling opportunities. */ && !satisfies_constraint_I (operands[1]) - && satisfies_constraint_Usc (operands[0]))" + && satisfies_constraint_Usc (operands[0])) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], HImode))" "@ mov%? %0,%1%& mov%? %0,%1%& diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c index 83311537e76..aa5d2f20b1e 100644 --- a/gcc/config/darwin-c.c +++ b/gcc/config/darwin-c.c @@ -463,41 +463,32 @@ static const char *framework_defaults [] = /* Register the GNU objective-C runtime include path if STDINC. */ void -darwin_register_objc_includes (const char *sysroot, const char *iprefix, - int stdinc) +darwin_register_objc_includes (const char *sysroot ATTRIBUTE_UNUSED, + const char *iprefix, int stdinc) { - const char *fname; - size_t len; - /* We do not do anything if we do not want the standard includes. */ - if (!stdinc) - return; - - fname = GCC_INCLUDE_DIR "-gnu-runtime"; - - /* Register the GNU OBJC runtime include path if we are compiling OBJC - with GNU-runtime. */ + /* If we want standard includes; Register the GNU OBJC runtime include + path if we are compiling OBJC with GNU-runtime. + This path is compiler-relative, we don't want to prepend the sysroot + since it's not expected to find the headers there. */ - if (c_dialect_objc () && !flag_next_runtime) + if (stdinc && c_dialect_objc () && !flag_next_runtime) { + const char *fname = GCC_INCLUDE_DIR "-gnu-runtime"; char *str; - /* See if our directory starts with the standard prefix. + size_t len; + + /* See if our directory starts with the standard prefix. "Translate" them, i.e. replace /usr/local/lib/gcc... with IPREFIX and search them first. */ - if (iprefix && (len = cpp_GCC_INCLUDE_DIR_len) != 0 && !sysroot + if (iprefix && (len = cpp_GCC_INCLUDE_DIR_len) != 0 && !strncmp (fname, cpp_GCC_INCLUDE_DIR, len)) { str = concat (iprefix, fname + len, NULL); - /* FIXME: wrap the headers for C++awareness. */ - add_path (str, INC_SYSTEM, /*c++aware=*/false, false); + add_path (str, INC_SYSTEM, /*c++aware=*/true, false); } - /* Should this directory start with the sysroot? */ - if (sysroot) - str = concat (sysroot, fname, NULL); - else - str = update_path (fname, ""); - - add_path (str, INC_SYSTEM, /*c++aware=*/false, false); + str = update_path (fname, ""); + add_path (str, INC_SYSTEM, /*c++aware=*/true, false); } } diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c index 6a7c85968bd..3d85f29cb3d 100644 --- a/gcc/config/darwin-driver.c +++ b/gcc/config/darwin-driver.c @@ -26,6 +26,91 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "diagnostic-core.h" +/* Validate a version string (either given on the command line or, perhaps + as MACOSX_DEPLOYMENT_TARGET). + + The specs %version-compare() function doesn't accept leading '0' on + numbers so strip them out. Do sanity checking here too. + + Return: + * original string means it was OK and we didn't want to change it. + * new string means it was OK but we rewrote it to avoid possible format + problems. + * NULL means we didn't like what we saw. +*/ + +static const char * +validate_macosx_version_min (const char *version_str) +{ + size_t version_len; + unsigned long major, minor, tiny = 0; + char *end; + const char *old_version = version_str; + bool need_rewrite = false; + + version_len = strlen (version_str); + if (version_len < 4) /* The minimum would be 10.x */ + return NULL; + + /* Version string must consist of digits and periods only. */ + if (strspn (version_str, "0123456789.") != version_len) + return NULL; + + if (!ISDIGIT (version_str[0]) || !ISDIGIT (version_str[version_len - 1])) + return NULL; + + if (version_str[0] == '0') + need_rewrite = true; + + major = strtoul (version_str, &end, 10); + version_str = end + ((*end == '.') ? 1 : 0); + + if (major != 10) /* So far .. all MacOS 10 ... */ + return NULL; + + /* Version string components must be present and numeric. */ + if (!ISDIGIT (version_str[0])) + return NULL; + + /* If we have one or more leading zeros on a component, then rewrite the + version string. */ + if (version_str[0] == '0' && version_str[1] != '\0' + && version_str[1] != '.') + need_rewrite = true; + + minor = strtoul (version_str, &end, 10); + version_str = end + ((*end == '.') ? 1 : 0); + if (minor > 99) + return NULL; + + /* If 'tiny' is present it must be numeric. */ + if (*end != '\0' && !ISDIGIT (version_str[0])) + return NULL; + + /* If we have one or more leading zeros on a component, then rewrite the + version string. */ + if (*end != '\0' && version_str[0] == '0' + && version_str[1] != '\0') + need_rewrite = true; + + tiny = strtoul (version_str, &end, 10); + if (tiny > 99) + return NULL; + + /* Version string must contain no more than three tokens. */ + if (*end != '\0') + return NULL; + + if (need_rewrite) + { + char *new_version; + asprintf (&new_version, "10.%lu.%lu", minor, tiny); + return new_version; + } + + return old_version; +} + #ifndef CROSS_DIRECTORY_STRUCTURE #include <sys/sysctl.h> #include "xregex.h" @@ -114,12 +199,13 @@ darwin_default_min_version (void) if (new_flag != NULL) { - size_t len = strlen (new_flag); - if (len > 128) { /* Arbitrary limit, number should be like xx.yy.zz */ - warning (0, "couldn%'t understand version %s\n", new_flag); - return NULL; - } - new_flag = xstrndup (new_flag, len); + const char *checked = validate_macosx_version_min (new_flag); + if (checked == NULL) + { + warning (0, "couldn%'t understand version %s\n", new_flag); + return NULL; + } + new_flag = xstrndup (checked, strlen (checked)); } return new_flag; } @@ -175,7 +261,7 @@ darwin_driver_init (unsigned int *decoded_options_count, if (*decoded_options_count > i) { memmove (*decoded_options + i, *decoded_options + i + 1, - ((*decoded_options_count - i) + ((*decoded_options_count - i - 1) * sizeof (struct cl_decoded_option))); } --i; @@ -209,7 +295,24 @@ darwin_driver_init (unsigned int *decoded_options_count, case OPT_mmacosx_version_min_: seen_version_min = true; - vers_string = xstrndup ((*decoded_options)[i].arg, 32); + vers_string = + validate_macosx_version_min ((*decoded_options)[i].arg); + if (vers_string == NULL) + warning (0, "%qs is not valid for %<mmacosx-version-min%>\n", + (*decoded_options)[i].arg); + else if (vers_string == (*decoded_options)[i].arg) + vers_string = xstrndup ((*decoded_options)[i].arg, 32); + /* Now we've examined it, and verified/re-written, put it to + one side and append later. */ + if (*decoded_options_count > i) { + memmove (*decoded_options + i, + *decoded_options + i + 1, + ((*decoded_options_count - i - 1) + * sizeof (struct cl_decoded_option))); + } + --i; + --*decoded_options_count; + break; default: break; @@ -276,22 +379,20 @@ darwin_driver_init (unsigned int *decoded_options_count, so that we can figure out the mechanism and source for the sysroot to be used. */ if (! seen_version_min && *decoded_options_count > 1) - { - /* Not set by the User, try to figure it out. */ - vers_string = darwin_default_min_version (); - if (vers_string != NULL) - { - ++*decoded_options_count; - *decoded_options = XRESIZEVEC (struct cl_decoded_option, - *decoded_options, - *decoded_options_count); - generate_option (OPT_mmacosx_version_min_, vers_string, 1, CL_DRIVER, - &(*decoded_options)[*decoded_options_count - 1]); - } - } - /* Create and push the major version for assemblers that need it. */ + /* Not set by the User, try to figure it out. */ + vers_string = darwin_default_min_version (); + + /* Create and push a cleaned up version, plus the major version for + assemblers and other cases that need it. */ if (vers_string != NULL) { + ++*decoded_options_count; + *decoded_options = XRESIZEVEC (struct cl_decoded_option, + *decoded_options, + *decoded_options_count); + generate_option (OPT_mmacosx_version_min_, vers_string, 1, CL_DRIVER, + &(*decoded_options)[*decoded_options_count - 1]); + char *asm_major = NULL; const char *first_period = strchr(vers_string, '.'); if (first_period != NULL) diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index f62f1c79bdd..b9862353843 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -2939,12 +2939,10 @@ darwin_file_end (void) if (flag_objc_abi >= 2) { flags = 16; - output_section_asm_op - (darwin_sections[objc2_image_info_section]->unnamed.data); + switch_to_section (darwin_sections[objc2_image_info_section]); } else - output_section_asm_op - (darwin_sections[objc_image_info_section]->unnamed.data); + switch_to_section (darwin_sections[objc_image_info_section]); ASM_OUTPUT_ALIGN (asm_out_file, 2); fputs ("L_OBJC_ImageInfo:\n", asm_out_file); @@ -3236,8 +3234,6 @@ darwin_override_options (void) /* so no tables either.. */ flag_unwind_tables = 0; flag_asynchronous_unwind_tables = 0; - /* We still need to emit branch islands for kernel context. */ - darwin_emit_branch_islands = true; } if (flag_var_tracking_uninit == 0 @@ -3247,6 +3243,8 @@ darwin_override_options (void) && write_symbols == DWARF2_DEBUG) flag_var_tracking_uninit = flag_var_tracking; + /* Final check on PCI options; for Darwin these are not dependent on the PIE + ones, although PIE does require PIC to support it. */ if (MACHO_DYNAMIC_NO_PIC_P) { if (flag_pic) @@ -3255,9 +3253,11 @@ darwin_override_options (void) " %<-fpie%> or %<-fPIE%>"); flag_pic = 0; } - else if (flag_pic == 1) + else if (flag_pic == 1 + || (flag_pic == 0 && !(flag_mkernel || flag_apple_kext))) { - /* Darwin's -fpic is -fPIC. */ + /* Darwin's -fpic is -fPIC. + We only support "static" code in the kernel and kernel exts. */ flag_pic = 2; } diff --git a/gcc/config/gcn/gcn-run.c b/gcc/config/gcn/gcn-run.c index 00a71014c20..d3def1369c7 100644 --- a/gcc/config/gcn/gcn-run.c +++ b/gcc/config/gcn/gcn-run.c @@ -829,7 +829,10 @@ main (int argc, char *argv[]) unsigned int upper = (return_value & ~0xffff) >> 16; if (upper == 0xcafe) - printf ("Kernel exit value was never set\n"); + { + printf ("Kernel exit value was never set\n"); + return_value = 0xff; + } else if (upper == 0xffff) ; /* Set by exit. */ else if (upper == 0) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 1dd2ff2d4f0..99fa45edcd4 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2826,9 +2826,9 @@ gcn_expand_prologue () emit_move_insn (fp_lo, gen_rtx_REG (SImode, 0)); emit_insn (gen_andsi3_scc (fp_hi, gen_rtx_REG (SImode, 1), gen_int_mode (0xffff, SImode))); - emit_insn (gen_addsi3_scc (fp_lo, fp_lo, wave_offset)); - emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi, - gen_rtx_REG (BImode, SCC_REG))); + rtx scc = gen_rtx_REG (BImode, SCC_REG); + emit_insn (gen_addsi3_scalar_carry (fp_lo, fp_lo, wave_offset, scc)); + emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi, scc)); if (sp_adjust > 0) emit_insn (gen_adddi3_scc (sp, fp, gen_int_mode (sp_adjust, DImode))); @@ -3062,6 +3062,10 @@ gcn_asm_trampoline_template (FILE *f) static void gcn_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) { + if (TARGET_GCN5_PLUS) + sorry ("nested function trampolines not supported on GCN5 due to" + " non-executable stacks"); + emit_block_move (m_tramp, assemble_trampoline_template (), GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 2b805a73c56..7e5cf17629d 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -784,10 +784,10 @@ if (cfun && cfun->machine && cfun->machine->normal_function) return "s_setpc_b64\ts[18:19]"; else - return "s_dcache_wb\;s_endpgm"; + return "s_waitcnt\tlgkmcnt(0)\;s_dcache_wb\;s_endpgm"; } [(set_attr "type" "sop1") - (set_attr "length" "8")]) + (set_attr "length" "12")]) (define_expand "call" [(parallel [(call (match_operand 0 "") @@ -830,18 +830,36 @@ [(set_attr "type" "mult") (set_attr "length" "32")]) -(define_insn_and_split "movdi_symbol_save_scc" +(define_insn "movdi_symbol_save_scc" [(set (match_operand:DI 0 "nonimmediate_operand" "=Sg") (match_operand:DI 1 "general_operand" "Y")) (clobber (reg:BI CC_SAVE_REG))] - "GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == LABEL_REF + "(GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == LABEL_REF) && (lra_in_progress || reload_completed)" - "#" - "reload_completed" - [(set (reg:BI CC_SAVE_REG) (reg:BI SCC_REG)) - (parallel [(set (match_dup 0) (match_dup 1)) - (clobber (reg:BI SCC_REG))]) - (set (reg:BI SCC_REG) (reg:BI CC_SAVE_REG))]) + { + /* !!! These sequences clobber CC_SAVE_REG. */ + + if (SYMBOL_REF_P (operands[1]) + && SYMBOL_REF_WEAK (operands[1])) + return "; s_mov_b32\ts22, scc is not supported by the assembler.\;" + ".long\t0xbe9600fd\;" + "s_getpc_b64\t%0\;" + "s_add_u32\t%L0, %L0, %1@gotpcrel32@lo+4\;" + "s_addc_u32\t%H0, %H0, %1@gotpcrel32@hi+4\;" + "s_load_dwordx2\t%0, %0\;" + "s_cmpk_lg_u32\ts22, 0\;" + "s_waitcnt\tlgkmcnt(0)"; + + return "; s_mov_b32\ts22, scc is not supported by the assembler.\;" + ".long\t0xbe9600fd\;" + "s_getpc_b64\t%0\;" + "s_add_u32\t%L0, %L0, %1@rel32@lo+4\;" + "s_addc_u32\t%H0, %H0, %1@rel32@hi+4\;" + "s_cmpk_lg_u32\ts22, 0"; + } + [(set_attr "type" "mult") + (set_attr "length" "40")]) + (define_insn "gcn_indirect_call" [(call (mem (match_operand:DI 0 "register_operand" "Sg")) diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h index 11284283304..1e96350fa71 100644 --- a/gcc/config/i386/darwin.h +++ b/gcc/config/i386/darwin.h @@ -47,12 +47,13 @@ along with GCC; see the file COPYING3. If not see image. Therefore, for 64b exes at least, we must use the libunwind implementation, even when static-libgcc is specified. We put libSystem first so that - unwinder symbols are satisfied from there. */ + unwinder symbols are satisfied from there. + We default to 64b for single-arch builds, so apply this unconditionally. */ #undef REAL_LIBGCC_SPEC #define REAL_LIBGCC_SPEC \ "%{static-libgcc|static: \ - %{m64:%:version-compare(>= 10.6 mmacosx-version-min= -lSystem)} \ - -lgcc_eh -lgcc; \ + %:version-compare(>= 10.6 mmacosx-version-min= -lSystem) \ + -lgcc_eh -lgcc; \ shared-libgcc|fexceptions|fgnu-runtime: \ %:version-compare(!> 10.5 mmacosx-version-min= -lgcc_s.10.4) \ %:version-compare(>< 10.5 10.6 mmacosx-version-min= -lgcc_s.10.5) \ @@ -141,9 +142,6 @@ extern int darwin_emit_branch_islands; " ASM_OPTIONS " -force_cpusubtype_ALL \ %{static}" ASM_MMACOSX_VERSION_MIN_SPEC -#define DARWIN_ARCH_SPEC "%{m64:x86_64;:i386}" -#define DARWIN_SUBARCH_SPEC DARWIN_ARCH_SPEC - #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ @@ -151,12 +149,15 @@ extern int darwin_emit_branch_islands; %{mpc64:crtprec64.o%s} \ %{mpc80:crtprec80.o%s}" TM_DESTRUCTOR +/* We default to x86_64 for single-arch builds, bi-arch overrides. */ +#define DARWIN_ARCH_SPEC "x86_64" + #undef SUBTARGET_EXTRA_SPECS #define SUBTARGET_EXTRA_SPECS \ DARWIN_EXTRA_SPECS \ - { "darwin_arch", DARWIN_ARCH_SPEC }, \ + { "darwin_arch", DARWIN_ARCH_SPEC }, \ { "darwin_crt2", "" }, \ - { "darwin_subarch", DARWIN_SUBARCH_SPEC }, + { "darwin_subarch", DARWIN_ARCH_SPEC }, /* The Darwin assembler mostly follows AT&T syntax. */ #undef ASSEMBLER_DIALECT @@ -223,6 +224,18 @@ extern int darwin_emit_branch_islands; } \ } while (0) +#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN +#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ + do { \ + if ((LOG) != 0) { \ + if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \ + fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ + else \ + fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ + } \ + } while (0) +#endif + /* Darwin x86 assemblers support the .ident directive. */ #undef TARGET_ASM_OUTPUT_IDENT diff --git a/gcc/config/i386/darwin32-biarch.h b/gcc/config/i386/darwin32-biarch.h new file mode 100644 index 00000000000..8dcc4a3b0b3 --- /dev/null +++ b/gcc/config/i386/darwin32-biarch.h @@ -0,0 +1,58 @@ +/* Target definitions for i386 running Darwin with a 32b host and supporting + a 64b multilib. + Copyright (C) 2019 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#undef DARWIN_ARCH_SPEC +#define DARWIN_ARCH_SPEC "%{m64:x86_64;:i386}" + +/* WORKAROUND pr80556: + For x86_64 Darwin10 and later, the unwinder is in libunwind (redirected + from libSystem). This doesn't use the keymgr (see keymgr.c) and therefore + the calls that libgcc makes to obtain the KEYMGR_GCC3_DW2_OBJ_LIST are not + updated to include new images, and might not even be valid for a single + image. + Therefore, for 64b exes at least, we must use the libunwind implementation, + even when static-libgcc is specified. We put libSystem first so that + unwinder symbols are satisfied from there. */ +#undef REAL_LIBGCC_SPEC +#define REAL_LIBGCC_SPEC \ + "%{static-libgcc|static: \ + %{m64:%:version-compare(>= 10.6 mmacosx-version-min= -lSystem)} \ + -lgcc_eh -lgcc; \ + shared-libgcc|fexceptions|fgnu-runtime: \ + %:version-compare(!> 10.5 mmacosx-version-min= -lgcc_s.10.4) \ + %:version-compare(>< 10.5 10.6 mmacosx-version-min= -lgcc_s.10.5) \ + %:version-compare(!> 10.5 mmacosx-version-min= -lgcc_ext.10.4) \ + %:version-compare(>= 10.5 mmacosx-version-min= -lgcc_ext.10.5) \ + -lgcc ; \ + :%:version-compare(>< 10.3.9 10.5 mmacosx-version-min= -lgcc_s.10.4) \ + %:version-compare(>< 10.5 10.6 mmacosx-version-min= -lgcc_s.10.5) \ + %:version-compare(!> 10.5 mmacosx-version-min= -lgcc_ext.10.4) \ + %:version-compare(>= 10.5 mmacosx-version-min= -lgcc_ext.10.5) \ + -lgcc }" + +#undef DARWIN_SUBARCH_SPEC +#define DARWIN_SUBARCH_SPEC DARWIN_ARCH_SPEC + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + DARWIN_EXTRA_SPECS \ + { "darwin_arch", DARWIN_ARCH_SPEC }, \ + { "darwin_crt2", "" }, \ + { "darwin_subarch", DARWIN_SUBARCH_SPEC }, diff --git a/gcc/config/i386/darwin64.h b/gcc/config/i386/darwin64-biarch.h index ebd65f94208..5af7665c2a7 100644 --- a/gcc/config/i386/darwin64.h +++ b/gcc/config/i386/darwin64-biarch.h @@ -1,4 +1,5 @@ -/* Target definitions for x86_64 running Darwin. +/* Target definitions for x86_64 running Darwin with a 64b host supporting a + 32b multilib. Copyright (C) 2006-2019 Free Software Foundation, Inc. Contributed by Apple Computer Inc. diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 6580890edc0..5dedeb2d18b 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -818,11 +818,11 @@ BDESC (OPTION_MASK_ISA_SSE3, 0, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd" /* SSSE3 */ BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI) BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9288fc4b17c..2b37296e537 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -4817,7 +4817,11 @@ ix86_option_override_internal (bool main_args_p, opts->x_flag_cf_protection = (cf_protection_level) (opts->x_flag_cf_protection | CF_SET); - if (ix86_tune_features [X86_TUNE_AVOID_128FMA_CHAINS]) + if (ix86_tune_features [X86_TUNE_AVOID_256FMA_CHAINS]) + maybe_set_param_value (PARAM_AVOID_FMA_MAX_BITS, 256, + opts->x_param_values, + opts_set->x_param_values); + else if (ix86_tune_features [X86_TUNE_AVOID_128FMA_CHAINS]) maybe_set_param_value (PARAM_AVOID_FMA_MAX_BITS, 128, opts->x_param_values, opts_set->x_param_values); @@ -46195,7 +46199,8 @@ static bool expand_vec_perm_blend (struct expand_vec_perm_d *d) { machine_mode mmode, vmode = d->vmode; - unsigned i, mask, nelt = d->nelt; + unsigned i, nelt = d->nelt; + unsigned HOST_WIDE_INT mask; rtx target, op0, op1, maskop, x; rtx rperm[32], vperm; @@ -46249,7 +46254,7 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d) case E_V16SImode: case E_V8DImode: for (i = 0; i < nelt; ++i) - mask |= (d->perm[i] >= nelt) << i; + mask |= ((unsigned HOST_WIDE_INT) (d->perm[i] >= nelt)) << i; break; case E_V2DImode: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6b8298d957e..152b7cc77f1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12481,8 +12481,8 @@ (const_string "<sseinsnmode>")))]) (define_insn "*andnot<mode>3_bcst" - [(set (match_operand:VI 0 "register_operand" "=v") - (and:VI + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (and:VI48_AVX512VL (not:VI48_AVX512VL (match_operand:VI48_AVX512VL 1 "register_operand" "v")) (vec_duplicate:VI48_AVX512VL @@ -13529,15 +13529,29 @@ switch (<MODE>mode) { case E_V8DFmode: - return "vmovapd\t{%2, %x0|%x0, %2}"; + if (misaligned_operand (operands[2], <ssequartermode>mode)) + return "vmovupd\t{%2, %x0|%x0, %2}"; + else + return "vmovapd\t{%2, %x0|%x0, %2}"; case E_V16SFmode: - return "vmovaps\t{%2, %x0|%x0, %2}"; + if (misaligned_operand (operands[2], <ssequartermode>mode)) + return "vmovups\t{%2, %x0|%x0, %2}"; + else + return "vmovaps\t{%2, %x0|%x0, %2}"; case E_V8DImode: - return which_alternative == 2 ? "vmovdqa64\t{%2, %x0|%x0, %2}" - : "vmovdqa\t{%2, %x0|%x0, %2}"; + if (misaligned_operand (operands[2], <ssequartermode>mode)) + return which_alternative == 2 ? "vmovdqu64\t{%2, %x0|%x0, %2}" + : "vmovdqu\t{%2, %x0|%x0, %2}"; + else + return which_alternative == 2 ? "vmovdqa64\t{%2, %x0|%x0, %2}" + : "vmovdqa\t{%2, %x0|%x0, %2}"; case E_V16SImode: - return which_alternative == 2 ? "vmovdqa32\t{%2, %x0|%x0, %2}" - : "vmovdqa\t{%2, %x0|%x0, %2}"; + if (misaligned_operand (operands[2], <ssequartermode>mode)) + return which_alternative == 2 ? "vmovdqu32\t{%2, %x0|%x0, %2}" + : "vmovdqu\t{%2, %x0|%x0, %2}"; + else + return which_alternative == 2 ? "vmovdqa32\t{%2, %x0|%x0, %2}" + : "vmovdqa\t{%2, %x0|%x0, %2}"; default: gcc_unreachable (); } @@ -16227,7 +16241,7 @@ } }) -(define_insn "abs<mode>2" +(define_insn "ssse3_abs<mode>2" [(set (match_operand:MMXMODEI 0 "register_operand" "=y") (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))] diff --git a/gcc/config/i386/t-darwin b/gcc/config/i386/t-darwin32-biarch index bf44504d4fd..bf44504d4fd 100644 --- a/gcc/config/i386/t-darwin +++ b/gcc/config/i386/t-darwin32-biarch diff --git a/gcc/config/i386/t-darwin64 b/gcc/config/i386/t-darwin64-biarch index 6a6b22f1ee5..6a6b22f1ee5 100644 --- a/gcc/config/i386/t-darwin64 +++ b/gcc/config/i386/t-darwin64-biarch diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index ac06e37733a..8b963c07051 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1279,12 +1279,12 @@ struct processor_costs znver1_cost = { static stringop_algs znver2_memcpy[2] = { {libcall, {{6, loop, false}, {14, unrolled_loop, false}, {-1, rep_prefix_4_byte, false}}}, - {libcall, {{16, loop, false}, {8192, rep_prefix_8_byte, false}, + {libcall, {{16, loop, false}, {64, rep_prefix_4_byte, false}, {-1, libcall, false}}}}; static stringop_algs znver2_memset[2] = { {libcall, {{8, loop, false}, {24, unrolled_loop, false}, {2048, rep_prefix_4_byte, false}, {-1, libcall, false}}}, - {libcall, {{48, unrolled_loop, false}, {8192, rep_prefix_8_byte, false}, + {libcall, {{24, rep_prefix_4_byte, false}, {128, rep_prefix_8_byte, false}, {-1, libcall, false}}}}; struct processor_costs znver2_cost = { @@ -1335,11 +1335,11 @@ struct processor_costs znver2_cost = { in SImode and DImode. */ {8, 8}, /* cost of storing MMX registers in SImode and DImode. */ - 2, 3, 6, /* cost of moving XMM,YMM,ZMM + 2, 2, 3, /* cost of moving XMM,YMM,ZMM register. */ - {6, 6, 6, 10, 20}, /* cost of loading SSE registers + {6, 6, 6, 6, 12}, /* cost of loading SSE registers in 32,64,128,256 and 512-bit. */ - {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ + {6, 6, 6, 6, 12}, /* cost of unaligned loads. */ {8, 8, 8, 8, 16}, /* cost of storing SSE registers in 32,64,128,256 and 512-bit. */ {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ @@ -1372,7 +1372,7 @@ struct processor_costs znver2_cost = { COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */ COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */ COSTS_N_INSNS (3), /* cost of MULSS instruction. */ - COSTS_N_INSNS (4), /* cost of MULSD instruction. */ + COSTS_N_INSNS (3), /* cost of MULSD instruction. */ COSTS_N_INSNS (5), /* cost of FMA SS instruction. */ COSTS_N_INSNS (5), /* cost of FMA SD instruction. */ COSTS_N_INSNS (10), /* cost of DIVSS instruction. */ diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 01e49867dfb..fd59a842658 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -431,6 +431,10 @@ DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather", smaller FMA chain. */ DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER) +/* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or + smaller FMA chain. */ +DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2) + /*****************************************************************************/ /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */ /*****************************************************************************/ diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md index c7f49bf1c57..d5e3efabb27 100644 --- a/gcc/config/i386/znver1.md +++ b/gcc/config/i386/znver1.md @@ -20,7 +20,7 @@ (define_attr "znver1_decode" "direct,vector,double" (const_string "direct")) -;; AMD znver1 Scheduling +;; AMD znver1 and znver2 Scheduling ;; Modeling automatons for zen decoders, integer execution pipes, ;; AGU pipes and floating point execution units. (define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu") @@ -51,13 +51,21 @@ (define_cpu_unit "znver1-ieu3" "znver1_ieu") (define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3") -;; 2 AGU pipes. +;; 2 AGU pipes in znver1 and 3 AGU pipes in znver2 +;; According to CPU diagram last AGU unit is used only for stores. (define_cpu_unit "znver1-agu0" "znver1_agu") (define_cpu_unit "znver1-agu1" "znver1_agu") +(define_cpu_unit "znver2-agu2" "znver1_agu") (define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1") +(define_reservation "znver2-store-agu-reserve" "znver1-agu0|znver1-agu1|znver2-agu2") +;; Load is 4 cycles. We do not model reservation of load unit. +;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing") (define_reservation "znver1-load" "znver1-agu-reserve") +;; Store operations differs between znver1 and znver2 because extra AGU +;; was added. (define_reservation "znver1-store" "znver1-agu-reserve") +(define_reservation "znver2-store" "znver2-store-agu-reserve") ;; vectorpath (microcoded) instructions are single issue instructions. ;; So, they occupy all the integer units. @@ -65,6 +73,9 @@ +znver1-ieu2+znver1-ieu3 +znver1-agu0+znver1-agu1") +(define_reservation "znver2-ivector" "znver1-ieu0+znver1-ieu1 + +znver1-ieu2+znver1-ieu3 + +znver1-agu0+znver1-agu1+znver2-agu2") ;; Floating point unit 4 FP pipes. (define_cpu_unit "znver1-fp0" "znver1_fp") (define_cpu_unit "znver1-fp1" "znver1_fp") @@ -76,6 +87,9 @@ (define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1 +znver1-fp2+znver1-fp3 +znver1-agu0+znver1-agu1") +(define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1 + +znver1-fp2+znver1-fp3 + +znver1-agu0+znver1-agu1+znver2-agu2") ;; Call instruction (define_insn_reservation "znver1_call" 1 @@ -83,27 +97,36 @@ (eq_attr "type" "call,callv")) "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3") +(define_insn_reservation "znver2_call" 1 + (and (eq_attr "cpu" "znver2") + (eq_attr "type" "call,callv")) + "znver1-double,znver2-store,znver1-ieu0|znver1-ieu3") + ;; General instructions (define_insn_reservation "znver1_push" 1 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "push") - (eq_attr "memory" "none,unknown"))) + (eq_attr "memory" "store"))) "znver1-direct,znver1-store") - -(define_insn_reservation "znver1_push_store" 1 - (and (eq_attr "cpu" "znver1") +(define_insn_reservation "znver2_push" 1 + (and (eq_attr "cpu" "znver2") (and (eq_attr "type" "push") (eq_attr "memory" "store"))) "znver1-direct,znver1-store") -(define_insn_reservation "znver1_push_both" 5 +(define_insn_reservation "znver1_push_load" 4 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "push") (eq_attr "memory" "both"))) "znver1-direct,znver1-load,znver1-store") +(define_insn_reservation "znver2_push_load" 4 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "push") + (eq_attr "memory" "both"))) + "znver1-direct,znver1-load,znver2-store") (define_insn_reservation "znver1_pop" 4 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "pop") (eq_attr "memory" "load"))) "znver1-direct,znver1-load") @@ -113,24 +136,33 @@ (and (eq_attr "type" "pop") (eq_attr "memory" "both"))) "znver1-direct,znver1-load,znver1-store") +(define_insn_reservation "znver2_pop_mem" 4 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "pop") + (eq_attr "memory" "both"))) + "znver1-direct,znver1-load,znver2-store") ;; Leave (define_insn_reservation "znver1_leave" 1 (and (eq_attr "cpu" "znver1") (eq_attr "type" "leave")) "znver1-double,znver1-ieu, znver1-store") +(define_insn_reservation "znver2_leave" 1 + (and (eq_attr "cpu" "znver2") + (eq_attr "type" "leave")) + "znver1-double,znver1-ieu, znver2-store") ;; Integer Instructions or General instructions ;; Multiplications ;; Reg operands (define_insn_reservation "znver1_imul" 3 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "imul") (eq_attr "memory" "none"))) "znver1-direct,znver1-ieu1") (define_insn_reservation "znver1_imul_mem" 7 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "imul") (eq_attr "memory" "!none"))) "znver1-direct,znver1-load, znver1-ieu1") @@ -138,28 +170,28 @@ ;; Divisions ;; Reg operands (define_insn_reservation "znver1_idiv_DI" 41 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "none")))) "znver1-double,znver1-ieu2*41") (define_insn_reservation "znver1_idiv_SI" 25 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "memory" "none")))) "znver1-double,znver1-ieu2*25") (define_insn_reservation "znver1_idiv_HI" 17 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "HI") (eq_attr "memory" "none")))) "znver1-double,znver1-ieu2*17") (define_insn_reservation "znver1_idiv_QI" 12 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "none")))) @@ -167,28 +199,28 @@ ;; Mem operands (define_insn_reservation "znver1_idiv_mem_DI" 45 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "none")))) "znver1-double,znver1-load,znver1-ieu2*41") (define_insn_reservation "znver1_idiv_mem_SI" 29 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "memory" "none")))) "znver1-double,znver1-load,znver1-ieu2*25") (define_insn_reservation "znver1_idiv_mem_HI" 21 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "HI") (eq_attr "memory" "none")))) "znver1-double,znver1-load,znver1-ieu2*17") (define_insn_reservation "znver1_idiv_mem_QI" 16 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "none")))) @@ -201,16 +233,34 @@ (and (eq_attr "type" "str,ishift") (eq_attr "memory" "both,store"))) "znver1-vector,znver1-ivector") + +(define_insn_reservation "znver2_str_ishift" 3 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ishift") + (eq_attr "memory" "both,store"))) + "znver1-vector,znver1-ivector") +(define_insn_reservation "znver2_str_istr" 19 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "str") + (eq_attr "memory" "both,store"))) + "znver1-vector,znver1-ivector") ;; MOV - integer moves (define_insn_reservation "znver1_load_imov_double" 2 (and (eq_attr "cpu" "znver1") (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "imovx") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu") + "znver1-double,znver1-ieu|znver1-ieu") + +(define_insn_reservation "znver2_load_imov_double" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "znver1_decode" "double") + (and (eq_attr "type" "imovx") + (eq_attr "memory" "none")))) + "znver1-double,znver1-ieu|znver1-ieu") (define_insn_reservation "znver1_load_imov_direct" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "imov,imovx") (eq_attr "memory" "none"))) "znver1-direct,znver1-ieu") @@ -220,7 +270,14 @@ (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "imovx") (eq_attr "memory" "store")))) - "znver1-double,znver1-ieu,znver1-store") + "znver1-double,znver1-ieu|znver1-ieu,znver1-store") + +(define_insn_reservation "znver2_load_imov_double_store" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "znver1_decode" "double") + (and (eq_attr "type" "imovx") + (eq_attr "memory" "store")))) + "znver1-double,znver1-ieu|znver1-ieu,znver2-store") (define_insn_reservation "znver1_load_imov_direct_store" 1 (and (eq_attr "cpu" "znver1") @@ -228,15 +285,28 @@ (eq_attr "memory" "store"))) "znver1-direct,znver1-ieu,znver1-store") +(define_insn_reservation "znver2_load_imov_direct_store" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "imov,imovx") + (eq_attr "memory" "store"))) + "znver1-direct,znver1-ieu,znver2-store") + (define_insn_reservation "znver1_load_imov_double_load" 5 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") + (and (eq_attr "znver1_decode" "double") + (and (eq_attr "type" "imovx") + (eq_attr "memory" "load")))) + "znver1-double,znver1-load,znver1-ieu|znver1-ieu") + +(define_insn_reservation "znver2_load_imov_double_load" 4 + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "imovx") (eq_attr "memory" "load")))) - "znver1-double,znver1-load") + "znver1-double,znver1-load,znver1-ieu|znver1-ieu") (define_insn_reservation "znver1_load_imov_direct_load" 4 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "imov,imovx") (eq_attr "memory" "load"))) "znver1-direct,znver1-load") @@ -244,13 +314,13 @@ ;; INTEGER/GENERAL instructions ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST (define_insn_reservation "znver1_insn" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov") (eq_attr "memory" "none,unknown"))) "znver1-direct,znver1-ieu") (define_insn_reservation "znver1_insn_load" 5 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-ieu") @@ -261,18 +331,35 @@ (eq_attr "memory" "store"))) "znver1-direct,znver1-ieu,znver1-store") +(define_insn_reservation "znver2_insn_store" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") + (eq_attr "memory" "store"))) + "znver1-direct,znver1-ieu,znver2-store") + (define_insn_reservation "znver1_insn_both" 5 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") (eq_attr "memory" "both"))) "znver1-direct,znver1-load,znver1-ieu,znver1-store") +(define_insn_reservation "znver2_insn_both" 5 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") + (eq_attr "memory" "both"))) + "znver1-direct,znver1-load,znver1-ieu,znver2-store") + ;; Fix me: Other vector type insns keeping latency 6 as of now. (define_insn_reservation "znver1_ieu_vector" 6 (and (eq_attr "cpu" "znver1") (eq_attr "type" "other,str,multi")) "znver1-vector,znver1-ivector") +(define_insn_reservation "znver2_ieu_vector" 5 + (and (eq_attr "cpu" "znver2") + (eq_attr "type" "other,str,multi")) + "znver1-vector,znver2-ivector") + ;; ALU1 register operands. (define_insn_reservation "znver1_alu1_vector" 3 (and (eq_attr "cpu" "znver1") @@ -281,15 +368,22 @@ (eq_attr "memory" "none,unknown")))) "znver1-vector,znver1-ivector") +(define_insn_reservation "znver2_alu1_vector" 3 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "znver1_decode" "vector") + (and (eq_attr "type" "alu1") + (eq_attr "memory" "none,unknown")))) + "znver1-vector,znver2-ivector") + (define_insn_reservation "znver1_alu1_double" 2 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "alu1") (eq_attr "memory" "none,unknown")))) "znver1-double,znver1-ieu") (define_insn_reservation "znver1_alu1_direct" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "znver1_decode" "direct") (and (eq_attr "type" "alu1") (eq_attr "memory" "none,unknown")))) @@ -297,7 +391,7 @@ ;; Branches : Fix me need to model conditional branches. (define_insn_reservation "znver1_branch" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "ibr") (eq_attr "memory" "none"))) "znver1-direct") @@ -309,27 +403,33 @@ (eq_attr "memory" "load"))) "znver1-vector,znver1-ivector") +(define_insn_reservation "znver2_indirect_branch_mem" 6 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ibr") + (eq_attr "memory" "load"))) + "znver1-vector,znver2-ivector") + ;; LEA executes in ALU units with 1 cycle latency. (define_insn_reservation "znver1_lea" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (eq_attr "type" "lea")) "znver1-direct,znver1-ieu") ;; Other integer instrucions (define_insn_reservation "znver1_idirect" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "unit" "integer,unknown") (eq_attr "memory" "none,unknown"))) "znver1-direct,znver1-ieu") ;; Floating point (define_insn_reservation "znver1_fp_cmov" 6 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (eq_attr "type" "fcmov")) "znver1-vector,znver1-fvector") (define_insn_reservation "znver1_fp_mov_direct_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "znver1_decode" "direct") (and (eq_attr "type" "fmov") (eq_attr "memory" "load")))) @@ -341,9 +441,15 @@ (and (eq_attr "type" "fmov") (eq_attr "memory" "store")))) "znver1-direct,znver1-fp2|znver1-fp3,znver1-store") +(define_insn_reservation "znver2_fp_mov_direct_store" 5 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "znver1_decode" "direct") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "store")))) + "znver1-direct,znver1-fp2|znver1-fp3,znver2-store") (define_insn_reservation "znver1_fp_mov_double" 4 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "fmov") (eq_attr "memory" "none")))) @@ -356,13 +462,21 @@ (eq_attr "memory" "load")))) "znver1-double,znver1-load,znver1-fp3") +(define_insn_reservation "znver2_fp_mov_double_load" 12 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "znver1_decode" "double") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "load")))) + "znver1-double,znver1-load,znver1-fp3") + (define_insn_reservation "znver1_fp_mov_direct" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (eq_attr "type" "fmov")) "znver1-direct,znver1-fp3") +;; TODO: AGU? (define_insn_reservation "znver1_fp_spc_direct" 5 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "fpspc") (eq_attr "memory" "store"))) "znver1-direct,znver1-fp3,znver1-fp2") @@ -372,22 +486,27 @@ (and (eq_attr "znver1_decode" "vector") (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov"))) "znver1-vector,znver1-fvector") +(define_insn_reservation "znver2_fp_insn_vector" 6 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "znver1_decode" "vector") + (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov"))) + "znver1-vector,znver2-fvector") ;; FABS (define_insn_reservation "znver1_fp_fsgn" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (eq_attr "type" "fsgn")) "znver1-direct,znver1-fp3") (define_insn_reservation "znver1_fp_fcmp" 2 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "memory" "none") (and (eq_attr "znver1_decode" "double") (eq_attr "type" "fcmp")))) "znver1-double,znver1-fp0,znver1-fp2") (define_insn_reservation "znver1_fp_fcmp_load" 9 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "memory" "none") (and (eq_attr "znver1_decode" "double") (eq_attr "type" "fcmp")))) @@ -395,32 +514,32 @@ ;;FADD FSUB FMUL (define_insn_reservation "znver1_fp_op_mul" 5 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "fop,fmul") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0*5") (define_insn_reservation "znver1_fp_op_mul_load" 12 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "fop,fmul") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0*5") (define_insn_reservation "znver1_fp_op_imul_load" 16 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "fop,fmul") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "load")))) "znver1-double,znver1-load,znver1-fp3,znver1-fp0") (define_insn_reservation "znver1_fp_op_div" 15 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "fdiv") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp3*15") (define_insn_reservation "znver1_fp_op_div_load" 22 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "fdiv") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp3*15") @@ -432,56 +551,63 @@ (eq_attr "memory" "load")))) "znver1-double,znver1-load,znver1-fp3*19") +(define_insn_reservation "znver2_fp_op_idiv_load" 26 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "fdiv") + (and (eq_attr "fp_int_src" "true") + (eq_attr "memory" "load")))) + "znver1-double,znver1-load,znver1-fp3*19") + ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions (define_insn_reservation "znver1_fp_insn" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (eq_attr "type" "mmx")) "znver1-direct,znver1-fpu") (define_insn_reservation "znver1_mmx_add" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxadd") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") (define_insn_reservation "znver1_mmx_add_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxadd") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") (define_insn_reservation "znver1_mmx_cmp" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxcmp") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp3") (define_insn_reservation "znver1_mmx_cmp_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxcmp") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp3") (define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp1|znver1-fp2") (define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") (define_insn_reservation "znver1_mmx_shift_move" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxshft,mmxmov") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp2") (define_insn_reservation "znver1_mmx_shift_move_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxshft,mmxmov") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp2") @@ -491,19 +617,25 @@ (and (eq_attr "type" "mmxshft,mmxmov") (eq_attr "memory" "store,both"))) "znver1-direct,znver1-fp2,znver1-store") +(define_insn_reservation "znver2_mmx_move_store" 1 + (and (eq_attr "cpu" "znver1") + (and (eq_attr "type" "mmxshft,mmxmov") + (eq_attr "memory" "store,both"))) + "znver1-direct,znver1-fp2,znver2-store") (define_insn_reservation "znver1_mmx_mul" 3 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0*3") (define_insn_reservation "znver1_mmx_load" 10 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0*3") +;; TODO (define_insn_reservation "znver1_avx256_log" 1 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF,OI") @@ -519,13 +651,13 @@ "znver1-double,znver1-load,znver1-fpu") (define_insn_reservation "znver1_sse_log" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "sselog") (eq_attr "memory" "none"))) "znver1-direct,znver1-fpu") (define_insn_reservation "znver1_sse_log_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "sselog") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fpu") @@ -545,13 +677,13 @@ "znver1-double,znver1-load,znver1-fp1|znver1-fp2") (define_insn_reservation "znver1_sse_log1" 1 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "sselog1") (eq_attr "memory" "none"))) "znver1-direct,znver1-fp1|znver1-fp2") (define_insn_reservation "znver1_sse_log1_load" 8 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "sselog1") (eq_attr "memory" "!none"))) "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") @@ -566,46 +698,50 @@ "znver1-direct,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_comi_load" 8 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF") - (and (eq_attr "prefix" "!vex") - (and (eq_attr "prefix_extra" "0") - (and (eq_attr "type" "ssecomi") - (eq_attr "memory" "load")))))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "prefix_extra" "0") + (and (eq_attr "type" "ssecomi") + (eq_attr "memory" "load")))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_comi_double" 2 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V4SF,V2DF,TI") - (and (eq_attr "prefix" "vex") - (and (eq_attr "prefix_extra" "0") - (and (eq_attr "type" "ssecomi") - (eq_attr "memory" "none")))))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "prefix" "vex") + (and (eq_attr "prefix_extra" "0") + (and (eq_attr "type" "ssecomi") + (eq_attr "memory" "none"))))) "znver1-double,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_comi_double_load" 10 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V4SF,V2DF,TI") - (and (eq_attr "prefix" "vex") - (and (eq_attr "prefix_extra" "0") - (and (eq_attr "type" "ssecomi") - (eq_attr "memory" "load")))))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "prefix" "vex") + (and (eq_attr "prefix_extra" "0") + (and (eq_attr "type" "ssecomi") + (eq_attr "memory" "load"))))) "znver1-double,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_test" 1 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") - (and (eq_attr "prefix_extra" "1") - (and (eq_attr "type" "ssecomi") - (eq_attr "memory" "none"))))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "prefix_extra" "1") + (and (eq_attr "type" "ssecomi") + (eq_attr "memory" "none")))) "znver1-direct,znver1-fp1|znver1-fp2") (define_insn_reservation "znver1_sse_test_load" 8 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") - (and (eq_attr "prefix_extra" "1") - (and (eq_attr "type" "ssecomi") - (eq_attr "memory" "load"))))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "prefix_extra" "1") + (and (eq_attr "type" "ssecomi") + (eq_attr "memory" "load")))) "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") ;; SSE moves @@ -619,6 +755,14 @@ (eq_attr "memory" "none"))))) "znver1-direct,znver1-ieu0") +(define_insn_reservation "znver2_sse_mov" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "mode" "SI") + (and (eq_attr "isa" "avx") + (and (eq_attr "type" "ssemov") + (eq_attr "memory" "none"))))) + "znver1-direct,znver1-ieu0") + (define_insn_reservation "znver1_avx_mov" 2 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "TI") @@ -628,11 +772,21 @@ (eq_attr "memory" "none")))))) "znver1-direct,znver1-ieu2") +(define_insn_reservation "znver2_avx_mov" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "isa" "avx") + (and (eq_attr "type" "ssemov") + (and (match_operand:SI 1 "register_operand") + (eq_attr "memory" "none")))))) + "znver1-direct,znver1-ieu2") + (define_insn_reservation "znver1_sseavx_mov" 1 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") - (and (eq_attr "type" "ssemov") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "ssemov") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fpu") (define_insn_reservation "znver1_sseavx_mov_store" 1 @@ -641,12 +795,18 @@ (and (eq_attr "type" "ssemov") (eq_attr "memory" "store")))) "znver1-direct,znver1-fpu,znver1-store") +(define_insn_reservation "znver2_sseavx_mov_store" 1 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ssemov") + (eq_attr "memory" "store"))) + "znver1-direct,znver1-fpu,znver2-store") (define_insn_reservation "znver1_sseavx_mov_load" 8 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") - (and (eq_attr "type" "ssemov") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "ssemov") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fpu") (define_insn_reservation "znver1_avx256_mov" 1 @@ -672,17 +832,19 @@ ;; SSE add (define_insn_reservation "znver1_sseavx_add" 3 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") - (and (eq_attr "type" "sseadd") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "sseadd") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp2|znver1-fp3") (define_insn_reservation "znver1_sseavx_add_load" 10 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") - (and (eq_attr "type" "sseadd") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "sseadd") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp2|znver1-fp3") (define_insn_reservation "znver1_avx256_add" 3 @@ -700,17 +862,19 @@ "znver1-double,znver1-load,znver1-fp2|znver1-fp3") (define_insn_reservation "znver1_sseavx_fma" 5 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF") - (and (eq_attr "type" "ssemuladd") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "ssemuladd") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sseavx_fma_load" 12 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF") - (and (eq_attr "type" "ssemuladd") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "ssemuladd") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_avx256_fma" 5 @@ -728,17 +892,19 @@ "znver1-double,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sseavx_iadd" 1 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "DI,TI") - (and (eq_attr "type" "sseiadd") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "DI,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "sseiadd") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") (define_insn_reservation "znver1_sseavx_iadd_load" 8 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "DI,TI") - (and (eq_attr "type" "sseiadd") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "DI,TI")) + (eq_attr "cpu" "znver2")) + (and (eq_attr "type" "sseiadd") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") (define_insn_reservation "znver1_avx256_iadd" 1 @@ -757,7 +923,7 @@ ;; SSE conversions. (define_insn_reservation "znver1_ssecvtsf_si_load" 12 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "mode" "SI") (and (eq_attr "type" "sseicvt") (and (match_operand:SF 1 "memory_operand") @@ -771,6 +937,13 @@ (and (eq_attr "type" "sseicvt") (eq_attr "memory" "none"))))) "znver1-double,znver1-fp3,znver1-ieu0") +(define_insn_reservation "znver2_ssecvtdf_si" 4 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "mode" "SI") + (and (match_operand:DF 1 "register_operand") + (and (eq_attr "type" "sseicvt") + (eq_attr "memory" "none"))))) + "znver1-double,znver1-fp3,znver1-ieu0") (define_insn_reservation "znver1_ssecvtdf_si_load" 12 (and (eq_attr "cpu" "znver1") @@ -780,6 +953,14 @@ (eq_attr "memory" "load"))))) "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") +(define_insn_reservation "znver2_ssecvtdf_si_load" 11 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "mode" "SI") + (and (eq_attr "type" "sseicvt") + (and (match_operand:DF 1 "memory_operand") + (eq_attr "memory" "load"))))) + "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") + ;; All other used ssecvt fp3 pipes ;; Check: Need to revisit this again. ;; Some SSE converts may use different pipe combinations. @@ -789,39 +970,59 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp3") +(define_insn_reservation "znver2_ssecvt" 3 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ssecvt") + (eq_attr "memory" "none"))) + "znver1-direct,znver1-fp3") + (define_insn_reservation "znver1_ssecvt_load" 11 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "ssecvt") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp3") +(define_insn_reservation "znver2_ssecvt_load" 11 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ssecvt") + (eq_attr "memory" "load"))) + "znver1-direct,znver1-load,znver1-fp3") + ;; SSE div (define_insn_reservation "znver1_ssediv_ss_ps" 10 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V4SF,SF") - (and (eq_attr "type" "ssediv") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V4SF,SF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "V8SF,V4SF,SF"))) + (and (eq_attr "type" "ssediv") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp3*10") (define_insn_reservation "znver1_ssediv_ss_ps_load" 17 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V4SF,SF") - (and (eq_attr "type" "ssediv") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V4SF,SF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "V8SF,V4SF,SF"))) + (and (eq_attr "type" "ssediv") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp3*10") (define_insn_reservation "znver1_ssediv_sd_pd" 13 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V2DF,DF") - (and (eq_attr "type" "ssediv") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V2DF,DF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "V4DF,V2DF,DF"))) + (and (eq_attr "type" "ssediv") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp3*13") (define_insn_reservation "znver1_ssediv_sd_pd_load" 20 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V2DF,DF") - (and (eq_attr "type" "ssediv") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V2DF,DF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "V4DF,V2DF,DF"))) + (and (eq_attr "type" "ssediv") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp3*13") (define_insn_reservation "znver1_ssediv_avx256_ps" 12 @@ -853,17 +1054,21 @@ "znver1-double,znver1-load,znver1-fp3*15") ;; SSE MUL (define_insn_reservation "znver1_ssemul_ss_ps" 3 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V4SF,SF") - (and (eq_attr "type" "ssemul") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V4SF,SF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF"))) + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "none"))) "znver1-direct,(znver1-fp0|znver1-fp1)*3") (define_insn_reservation "znver1_ssemul_ss_ps_load" 10 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "V4SF,SF") - (and (eq_attr "type" "ssemul") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "V4SF,SF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "V8SF,V4SF,SF"))) + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") (define_insn_reservation "znver1_ssemul_avx256_ps" 3 @@ -894,12 +1099,23 @@ (eq_attr "memory" "load")))) "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4") +(define_insn_reservation "znver2_ssemul_sd_pd" 3 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "none"))) + "znver1-direct,(znver1-fp0|znver1-fp1)*3") + +(define_insn_reservation "znver2_ssemul_sd_pd_load" 10 + (and (eq_attr "cpu" "znver2") + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "load"))) + "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") + (define_insn_reservation "znver1_ssemul_avx256_pd" 5 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") - (and (eq_attr "mode" "V4DF") - (and (eq_attr "type" "ssemul") - (eq_attr "memory" "none"))))) + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "none")))) "znver1-double,(znver1-fp0|znver1-fp1)*4") (define_insn_reservation "znver1_ssemul_avx256_pd_load" 12 @@ -911,42 +1127,46 @@ ;;SSE imul (define_insn_reservation "znver1_sseimul" 3 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "TI") - (and (eq_attr "type" "sseimul") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "TI")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "TI,OI"))) + (and (eq_attr "type" "sseimul") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0*3") (define_insn_reservation "znver1_sseimul_avx256" 4 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "mode" "OI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "none")))) "znver1-double,znver1-fp0*4") (define_insn_reservation "znver1_sseimul_load" 10 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "TI") - (and (eq_attr "type" "sseimul") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "TI")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "TI,OI"))) + (and (eq_attr "type" "sseimul") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0*3") (define_insn_reservation "znver1_sseimul_avx256_load" 11 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "mode" "OI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "load")))) "znver1-double,znver1-load,znver1-fp0*4") (define_insn_reservation "znver1_sseimul_di" 3 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "mode" "DI") (and (eq_attr "memory" "none") (eq_attr "type" "sseimul")))) "znver1-direct,znver1-fp0*3") (define_insn_reservation "znver1_sseimul_load_di" 10 - (and (eq_attr "cpu" "znver1") + (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "mode" "DI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "load")))) @@ -954,17 +1174,21 @@ ;; SSE compares (define_insn_reservation "znver1_sse_cmp" 1 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF") - (and (eq_attr "type" "ssecmp") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF"))) + (and (eq_attr "type" "ssecmp") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_cmp_load" 8 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "SF,DF,V4SF,V2DF") - (and (eq_attr "type" "ssecmp") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "SF,DF,V4SF,V2DF")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF"))) + (and (eq_attr "type" "ssecmp") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_cmp_avx256" 1 @@ -982,17 +1206,21 @@ "znver1-double,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_sse_icmp" 1 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "QI,HI,SI,DI,TI") - (and (eq_attr "type" "ssecmp") - (eq_attr "memory" "none")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "QI,HI,SI,DI,TI")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "QI,HI,SI,DI,TI,OI"))) + (and (eq_attr "type" "ssecmp") + (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp3") (define_insn_reservation "znver1_sse_icmp_load" 8 - (and (eq_attr "cpu" "znver1") - (and (eq_attr "mode" "QI,HI,SI,DI,TI") - (and (eq_attr "type" "ssecmp") - (eq_attr "memory" "load")))) + (and (ior (and (eq_attr "cpu" "znver1") + (eq_attr "mode" "QI,HI,SI,DI,TI")) + (and (eq_attr "cpu" "znver2") + (eq_attr "mode" "QI,HI,SI,DI,TI,OI"))) + (and (eq_attr "type" "ssecmp") + (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0|znver1-fp3") (define_insn_reservation "znver1_sse_icmp_avx256" 1 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 2ba0850c4fd..2dfc7c73cce 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -16867,6 +16867,19 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, std::swap (ops[1], ops[2]); break; + case CODE_FOR_msa_maddv_b: + case CODE_FOR_msa_maddv_h: + case CODE_FOR_msa_maddv_w: + case CODE_FOR_msa_maddv_d: + case CODE_FOR_msa_fmadd_w: + case CODE_FOR_msa_fmadd_d: + case CODE_FOR_msa_fmsub_w: + case CODE_FOR_msa_fmsub_d: + /* fma(a, b, c) results into (a * b + c), however builtin_msa_fmadd expects + it to be (a + b * c). Swap the 1st and 3rd operands. */ + std::swap (ops[1], ops[3]); + break; + case CODE_FOR_msa_slli_b: case CODE_FOR_msa_slli_h: case CODE_FOR_msa_slli_w: diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 2ae1f7e0440..a9b0c86be07 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7588,7 +7588,7 @@ ;; __builtin_mips_get_fcsr: move the FCSR into operand 0. (define_expand "mips_get_fcsr" [(set (match_operand:SI 0 "register_operand") - (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] + (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] "TARGET_HARD_FLOAT_ABI" { if (TARGET_MIPS16) @@ -7600,7 +7600,7 @@ (define_insn "*mips_get_fcsr" [(set (match_operand:SI 0 "register_operand" "=d") - (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] + (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] "TARGET_HARD_FLOAT" "cfc1\t%0,$31") diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index a28099ac89d..1986e79309a 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -1475,7 +1475,7 @@ nvptx_output_softstack_switch (FILE *file, bool entering, fputs (";\n", file); if (!CONST_INT_P (size) || UINTVAL (align) > GET_MODE_SIZE (DImode)) fprintf (file, - "\t\tand.u%d %%r%d, %%r%d, -" HOST_WIDE_INT_PRINT_DEC ";\n", + "\t\tand.b%d %%r%d, %%r%d, -" HOST_WIDE_INT_PRINT_DEC ";\n", bits, regno, regno, UINTVAL (align)); } if (cfun->machine->has_softstack) diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h index 0d02ebc7fb2..23812e4aded 100644 --- a/gcc/config/pa/pa-linux.h +++ b/gcc/config/pa/pa-linux.h @@ -101,7 +101,7 @@ along with GCC; see the file COPYING3. If not see /* FIXME: Hacked from the <elfos.h> one so that we avoid multiple labels in a function declaration (since pa.c seems determined to do - it differently) */ + it differently). */ #undef ASM_DECLARE_FUNCTION_NAME #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ @@ -109,9 +109,14 @@ along with GCC; see the file COPYING3. If not see { \ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ + pa_output_function_label (FILE); \ } \ while (0) +/* Output function prologue for linux. */ +#undef TARGET_ASM_FUNCTION_PROLOGUE +#define TARGET_ASM_FUNCTION_PROLOGUE pa_linux_output_function_prologue + /* As well as globalizing the label, we need to encode the label to ensure a plabel is generated in an indirect call. */ diff --git a/gcc/config/pa/pa-protos.h b/gcc/config/pa/pa-protos.h index 2504ac8daf3..a62eeb732dc 100644 --- a/gcc/config/pa/pa-protos.h +++ b/gcc/config/pa/pa-protos.h @@ -108,6 +108,7 @@ extern void pa_asm_output_aligned_local (FILE *, const char *, extern void pa_hpux_asm_output_external (FILE *, tree, const char *); extern HOST_WIDE_INT pa_initial_elimination_offset (int, int); extern HOST_WIDE_INT pa_function_arg_size (machine_mode, const_tree); +extern void pa_output_function_label (FILE *); extern const int pa_magic_milli[]; diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 54d5b127fc4..707ae5822c3 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -118,7 +118,8 @@ static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); static rtx pa_function_value (const_tree, const_tree, bool); static rtx pa_libcall_value (machine_mode, const_rtx); static bool pa_function_value_regno_p (const unsigned int); -static void pa_output_function_prologue (FILE *); +static void pa_output_function_prologue (FILE *) ATTRIBUTE_UNUSED; +static void pa_linux_output_function_prologue (FILE *) ATTRIBUTE_UNUSED; static void update_total_code_bytes (unsigned int); static void pa_output_function_epilogue (FILE *); static int pa_adjust_cost (rtx_insn *, int, rtx_insn *, int, unsigned int); @@ -262,8 +263,6 @@ static size_t n_deferred_plabels = 0; #undef TARGET_ASM_INTEGER #define TARGET_ASM_INTEGER pa_assemble_integer -#undef TARGET_ASM_FUNCTION_PROLOGUE -#define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue #undef TARGET_ASM_FUNCTION_EPILOGUE #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue @@ -3842,16 +3841,10 @@ pa_compute_frame_size (poly_int64 size, int *fregs_live) & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); } -/* On HP-PA, move-double insns between fpu and cpu need an 8-byte block - of memory. If any fpu reg is used in the function, we allocate - such a block here, at the bottom of the frame, just in case it's needed. +/* Output function label, and associated .PROC and .CALLINFO statements. */ - If this function is a leaf procedure, then we may choose not - to do a "save" insn. The decision about whether or not - to do this is made in regclass.c. */ - -static void -pa_output_function_prologue (FILE *file) +void +pa_output_function_label (FILE *file) { /* The function's label and associated .PROC must never be separated and must be output *after* any profiling declarations @@ -3897,7 +3890,22 @@ pa_output_function_prologue (FILE *file) fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); fputs ("\n\t.ENTRY\n", file); +} +/* Output function prologue. */ + +static void +pa_output_function_prologue (FILE *file) +{ + pa_output_function_label (file); + remove_useless_addtr_insns (0); +} + +/* The label is output by ASM_DECLARE_FUNCTION_NAME on linux. */ + +static void +pa_linux_output_function_prologue (FILE *file ATTRIBUTE_UNUSED) +{ remove_useless_addtr_insns (0); } @@ -9794,19 +9802,22 @@ pa_som_asm_init_sections (void) = get_unnamed_section (0, output_section_asm_op, "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$"); - /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups - which reference data within the $TEXT$ space (for example constant + /* HPUX ld generates incorrect GOT entries for "T" fixups which + reference data within the $TEXT$ space (for example constant strings in the $LIT$ subspace). The assemblers (GAS and HP as) both have problems with handling - the difference of two symbols which is the other correct way to + the difference of two symbols. This is the other correct way to reference constant data during PIC code generation. - So, there's no way to reference constant data which is in the - $TEXT$ space during PIC generation. Instead place all constant - data into the $PRIVATE$ subspace (this reduces sharing, but it - works correctly). */ - readonly_data_section = flag_pic ? data_section : som_readonly_data_section; + Thus, we can't put constant data needing relocation in the $TEXT$ + space during PIC generation. + + Previously, we placed all constant data into the $DATA$ subspace + when generating PIC code. This reduces sharing, but it works + correctly. Now we rely on pa_reloc_rw_mask() for section selection. + This puts constant data not needing relocation into the $TEXT$ space. */ + readonly_data_section = som_readonly_data_section; /* We must not have a reference to an external symbol defined in a shared library in a readonly section, else the SOM linker will @@ -9839,7 +9850,7 @@ pa_select_section (tree exp, int reloc, && DECL_INITIAL (exp) && (DECL_INITIAL (exp) == error_mark_node || TREE_CONSTANT (DECL_INITIAL (exp))) - && !reloc) + && !(reloc & pa_reloc_rw_mask ())) { if (TARGET_SOM && DECL_ONE_ONLY (exp) @@ -9848,7 +9859,8 @@ pa_select_section (tree exp, int reloc, else return readonly_data_section; } - else if (CONSTANT_CLASS_P (exp) && !reloc) + else if (CONSTANT_CLASS_P (exp) + && !(reloc & pa_reloc_rw_mask ())) return readonly_data_section; else if (TARGET_SOM && TREE_CODE (exp) == VAR_DECL @@ -9864,12 +9876,11 @@ pa_select_section (tree exp, int reloc, static int pa_reloc_rw_mask (void) { - /* We force (const (plus (symbol) (const_int))) to memory when the - const_int doesn't fit in a 14-bit integer. The SOM linker can't - handle this construct in read-only memory and we want to avoid - this for ELF. So, we always force an RTX needing relocation to - the data section. */ - return 3; + if (flag_pic || (TARGET_SOM && !TARGET_HPUX_11)) + return 3; + + /* HP linker does not support global relocs in readonly memory. */ + return TARGET_SOM ? 2 : 0; } static void diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 146ffa2a1e2..561efa51882 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -1305,3 +1305,6 @@ do { \ /* Target CPU versions for D. */ #define TARGET_D_CPU_VERSIONS pa_d_target_versions + +/* Output default function prologue for hpux. */ +#define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 8308b37461d..84630ad536d 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -6904,21 +6904,24 @@ rtx stack = operands[2]; rtx fp = operands[3]; - lab = copy_to_reg (lab); - emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); - /* Restore the frame pointer. The virtual_stack_vars_rtx is saved - instead of the hard_frame_pointer_rtx in the save area. As a - result, an extra instruction is needed to adjust for the offset - of the virtual stack variables and the hard frame pointer. */ - if (GET_CODE (fp) != REG) - fp = force_reg (Pmode, fp); - emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8)); + lab = copy_to_reg (lab); + /* Restore the stack and frame pointers. The virtual_stack_vars_rtx + is saved instead of the hard_frame_pointer_rtx in the save area. + As a result, an extra instruction is needed to adjust for the offset + of the virtual stack variables and the hard frame pointer. */ + fp = copy_to_reg (fp); emit_stack_restore (SAVE_NONLOCAL, stack); + /* Ensure the frame pointer move is not optimized. */ + emit_insn (gen_blockage ()); + emit_clobber (hard_frame_pointer_rtx); + emit_clobber (frame_pointer_rtx); + emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8)); + emit_use (hard_frame_pointer_rtx); emit_use (stack_pointer_rtx); @@ -8695,23 +8698,26 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); - /* Restore the frame pointer. The virtual_stack_vars_rtx is saved - instead of the hard_frame_pointer_rtx in the save area. We need - to adjust for the offset between these two values. */ - if (GET_CODE (fp) != REG) - fp = force_reg (Pmode, fp); - emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8)); - - /* This bit is the same as expand_builtin_longjmp. */ - emit_stack_restore (SAVE_NONLOCAL, stack); - emit_use (hard_frame_pointer_rtx); - emit_use (stack_pointer_rtx); - /* Load the label we are jumping through into r1 so that we know where to look for it when we get back to setjmp's function for restoring the gp. */ emit_move_insn (pv, lab); + /* Restore the stack and frame pointers. The virtual_stack_vars_rtx + is saved instead of the hard_frame_pointer_rtx in the save area. + We need to adjust for the offset between these two values. */ + fp = copy_to_reg (fp); + emit_stack_restore (SAVE_NONLOCAL, stack); + + /* Ensure the frame pointer move is not optimized. */ + emit_insn (gen_blockage ()); + emit_clobber (hard_frame_pointer_rtx); + emit_clobber (frame_pointer_rtx); + emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8)); + + emit_use (hard_frame_pointer_rtx); + emit_use (stack_pointer_rtx); + /* Prevent the insns above from being scheduled into the delay slot of the interspace jump because the space register could change. */ emit_insn (gen_blockage ()); diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index e7440f39095..35219956c80 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -4866,6 +4866,32 @@ riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align) return align; } +/* Implement TARGET_PROMOTE_FUNCTION_MODE. */ + +/* This function is equivalent to default_promote_function_mode_always_promote + except that it returns a promoted mode even if type is NULL_TREE. This is + needed by libcalls which have no type (only a mode) such as fixed conversion + routines that take a signed or unsigned char/short/int argument and convert + it to a fixed type. */ + +static machine_mode +riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, + machine_mode mode, + int *punsignedp ATTRIBUTE_UNUSED, + const_tree fntype ATTRIBUTE_UNUSED, + int for_return ATTRIBUTE_UNUSED) +{ + int unsignedp; + + if (type != NULL_TREE) + return promote_mode (type, mode, punsignedp); + + unsignedp = *punsignedp; + PROMOTE_MODE (mode, unsignedp, type); + *punsignedp = unsignedp; + return mode; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -4907,7 +4933,7 @@ riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align) #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start #undef TARGET_PROMOTE_FUNCTION_MODE -#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote +#define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode #undef TARGET_RETURN_IN_MEMORY #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e3799a5bdd8..a8bac170e72 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1775,10 +1775,11 @@ (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] { - operands[2] = GEN_INT (BITS_PER_WORD + /* Op2 is a VOIDmode constant, so get the mode size from op1. */ + operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])) - exact_log2 (INTVAL (operands[2]) + 1)); }) - + ;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros. This can be ;; split into two shifts. Otherwise it requires 3 instructions: li, sll, and. (define_split diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 9fb36e41e7d..98ecf0ad2fe 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -53,9 +53,23 @@ #define TARGET_OS_CPP_BUILTINS() \ do \ { \ - if (!TARGET_64BIT) builtin_define ("__ppc__"); \ - if (TARGET_64BIT) builtin_define ("__ppc64__"); \ builtin_define ("__POWERPC__"); \ + builtin_define ("__PPC__"); \ + if (TARGET_64BIT) \ + { \ + builtin_define ("__ppc64__"); \ + builtin_define ("__PPC64__"); \ + builtin_define ("__powerpc64__"); \ + builtin_assert ("cpu=powerpc64"); \ + builtin_assert ("machine=powerpc64"); \ + } \ + else \ + { \ + builtin_define ("__ppc__"); \ + builtin_define_std ("PPC"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ builtin_define ("__NATURAL_ALIGNMENT__"); \ darwin_cpp_builtins (pfile); \ } \ @@ -98,11 +112,10 @@ extern int darwin_emit_branch_islands; %<faltivec %<fno-altivec " \ DARWIN_CC1_SPEC -#define DARWIN_ARCH_SPEC "%{m64:ppc64;:ppc}" +/* Default to PPC for single arch builds. */ +#define DARWIN_ARCH_SPEC "ppc" #define DARWIN_SUBARCH_SPEC " \ - %{m64: ppc64} \ - %{!m64: \ %{mcpu=601:ppc601; \ mcpu=603:ppc603; \ mcpu=603e:ppc603; \ @@ -117,7 +130,7 @@ extern int darwin_emit_branch_islands; mcpu=970:ppc970; \ mcpu=power4:ppc970; \ mcpu=G5:ppc970; \ - :ppc}}" + :ppc}" /* We need to jam the crt to 10.5 for 10.6 (Rosetta) use. */ #undef DARWIN_CRT1_SPEC @@ -395,6 +408,7 @@ extern int darwin_emit_branch_islands; do \ { \ DARWIN_REGISTER_TARGET_PRAGMAS(); \ + targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ } \ while (0) diff --git a/gcc/config/rs6000/darwin32-biarch.h b/gcc/config/rs6000/darwin32-biarch.h new file mode 100644 index 00000000000..743aabfcea2 --- /dev/null +++ b/gcc/config/rs6000/darwin32-biarch.h @@ -0,0 +1,49 @@ +/* Target definitions for PowerPC running Darwin (Mac OS X) for a 32b host + with a 64b miultilib. + Copyright (C) 2019 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#undef DARWIN_ARCH_SPEC +#define DARWIN_ARCH_SPEC "%{m64:ppc64;:ppc}" + +#undef DARWIN_SUBARCH_SPEC +#define DARWIN_SUBARCH_SPEC " \ + %{m64: ppc64} \ + %{!m64: \ + %{mcpu=601:ppc601; \ + mcpu=603:ppc603; \ + mcpu=603e:ppc603; \ + mcpu=604:ppc604; \ + mcpu=604e:ppc604e; \ + mcpu=740:ppc750; \ + mcpu=750:ppc750; \ + mcpu=G3:ppc750; \ + mcpu=7400:ppc7400; \ + mcpu=G4:ppc7400; \ + mcpu=7450:ppc7450; \ + mcpu=970:ppc970; \ + mcpu=power4:ppc970; \ + mcpu=G5:ppc970; \ + :ppc}}" + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + DARWIN_EXTRA_SPECS \ + { "darwin_arch", DARWIN_ARCH_SPEC }, \ + { "darwin_crt2", DARWIN_CRT2_SPEC }, \ + { "darwin_subarch", DARWIN_SUBARCH_SPEC }, diff --git a/gcc/config/rs6000/darwin64.h b/gcc/config/rs6000/darwin64-biarch.h index a131ff20bbd..4f789544b9e 100644 --- a/gcc/config/rs6000/darwin64.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -1,4 +1,5 @@ -/* Target definitions for PowerPC running Darwin (Mac OS X). +/* Target definitions for PowerPC64 running Darwin (Mac OS X) for a 64b host + supporting a 32b multilib. Copyright (C) 2006-2019 Free Software Foundation, Inc. Contributed by Apple Computer Inc. @@ -25,8 +26,13 @@ #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" +/* Actually, there's really only 970 as an active option. */ #undef DARWIN_SUBARCH_SPEC #define DARWIN_SUBARCH_SPEC DARWIN_ARCH_SPEC -#undef DARWIN_CRT2_SPEC -#define DARWIN_CRT2_SPEC "" +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + DARWIN_EXTRA_SPECS \ + { "darwin_arch", DARWIN_ARCH_SPEC }, \ + { "darwin_crt2", "" }, \ + { "darwin_subarch", DARWIN_SUBARCH_SPEC }, diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h index 7e819d102f9..98b1cfd50dc 100644 --- a/gcc/config/rs6000/freebsd64.h +++ b/gcc/config/rs6000/freebsd64.h @@ -17,6 +17,10 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* Undef gnu-user.h macros we don't want. */ +#undef CPLUSPLUS_CPP_SPEC +#undef LINK_GCC_C_SEQUENCE_SPEC + /* Override the defaults, which exist to force the proper definition. */ #ifdef IN_LIBGCC2 diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h index 96b97877989..ffceb32bf65 100644 --- a/gcc/config/rs6000/linux.h +++ b/gcc/config/rs6000/linux.h @@ -59,19 +59,6 @@ } \ while (0) -#define GNU_USER_TARGET_D_OS_VERSIONS() \ - do { \ - builtin_version ("linux"); \ - if (OPTION_GLIBC) \ - builtin_version ("CRuntime_Glibc"); \ - else if (OPTION_UCLIBC) \ - builtin_version ("CRuntime_UClibc"); \ - else if (OPTION_BIONIC) \ - builtin_version ("CRuntime_Bionic"); \ - else if (OPTION_MUSL) \ - builtin_version ("CRuntime_Musl"); \ - } while (0) - #undef CPP_OS_DEFAULT_SPEC #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 5380f6a6a6f..9946d3fed94 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -376,7 +376,8 @@ extern int dot_symbols; #define TARGET_OS_CPP_BUILTINS() \ do \ { \ - if (strcmp (rs6000_abi_name, "linux") == 0) \ + if (strcmp (rs6000_abi_name, "linux") == 0 \ + || strcmp (rs6000_abi_name, "aixdesc") == 0) \ GNU_USER_TARGET_OS_CPP_BUILTINS(); \ if (TARGET_64BIT) \ { \ @@ -400,19 +401,6 @@ extern int dot_symbols; } \ while (0) -#define GNU_USER_TARGET_D_OS_VERSIONS() \ - do { \ - builtin_version ("linux"); \ - if (OPTION_GLIBC) \ - builtin_version ("CRuntime_Glibc"); \ - else if (OPTION_UCLIBC) \ - builtin_version ("CRuntime_UClibc"); \ - else if (OPTION_BIONIC) \ - builtin_version ("CRuntime_Bionic"); \ - else if (OPTION_MUSL) \ - builtin_version ("CRuntime_Musl"); \ - } while (0) - #undef CPP_OS_DEFAULT_SPEC #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux) %(include_extra)" diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 09b1f5eab87..6b5f1cd06f7 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3639,10 +3639,22 @@ darwin_rs6000_override_options (void) rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64"); } + + /* The linkers [ld64] that support 64Bit do not need the JBSR longcall + optimisation, and will not work with the most generic case (where the + symbol is undefined external, but there is no symbl stub). */ + if (TARGET_64BIT) + rs6000_default_long_calls = 0; + + /* ld_classic is (so far) still used for kernel (static) code, and supports + the JBSR longcall / branch islands. */ if (flag_mkernel) { rs6000_default_long_calls = 1; - rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + + /* Allow a kext author to do -mkernel -mhard-float. */ + if (! (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)) + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes @@ -29158,6 +29170,8 @@ rs6000_output_function_epilogue (FILE *file) i = 1; else if (! strcmp (language_string, "GNU Ada")) i = 3; + else if (! strcmp (language_string, "GNU Modula-2")) + i = 8; else if (lang_GNU_CXX () || ! strcmp (language_string, "GNU Objective-C++")) i = 9; @@ -36290,10 +36304,20 @@ rs6000_init_dwarf_reg_sizes_extra (tree address) unsigned int rs6000_dbx_register_number (unsigned int regno, unsigned int format) { - /* Except for the above, we use the internal number for non-DWARF - debug information, and also for .eh_frame. */ + /* We use the GCC 7 (and before) internal number for non-DWARF debug + information, and also for .eh_frame. */ if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2) - return regno; + { + /* Translate the regnos to their numbers in GCC 7 (and before). */ + if (regno == TFHAR_REGNO) + regno = 114; + else if (regno == TFIAR_REGNO) + regno = 115; + else if (regno == TEXASR_REGNO) + regno = 116; + + return regno; + } /* On some platforms, we use the standard DWARF register numbering for .debug_info and .debug_frame. */ @@ -36320,6 +36344,12 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format) return 356; if (regno == VSCR_REGNO) return 67; + if (regno == TFHAR_REGNO) + return 228; + if (regno == TFIAR_REGNO) + return 229; + if (regno == TEXASR_REGNO) + return 230; #endif return regno; } diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h index 914dade70d0..5ef0822febc 100644 --- a/gcc/config/rs6000/smmintrin.h +++ b/gcc/config/rs6000/smmintrin.h @@ -66,4 +66,24 @@ _mm_extract_ps (__m128 __X, const int __N) return ((__v4si)__X)[__N & 3]; } +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8) +{ + __v16qi __charmask = vec_splats ((signed char) __imm8); + __charmask = vec_gb (__charmask); + __v8hu __shortmask = (__v8hu) vec_unpackh (__charmask); + #ifdef __BIG_ENDIAN__ + __shortmask = vec_reve (__shortmask); + #endif + return (__m128i) vec_sel ((__v8hu) __A, (__v8hu) __B, __shortmask); +} + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i __mask) +{ + const __v16qu __seven = vec_splats ((unsigned char) 0x07); + __v16qu __lmask = vec_sra ((__v16qu) __mask, __seven); + return (__m128i) vec_sel ((__v16qu) __A, (__v16qu) __B, __lmask); +} + #endif diff --git a/gcc/config/rs6000/t-darwin8 b/gcc/config/rs6000/t-darwin32-biarch index 2f3bb32f821..2f3bb32f821 100644 --- a/gcc/config/rs6000/t-darwin8 +++ b/gcc/config/rs6000/t-darwin32-biarch diff --git a/gcc/config/rs6000/t-darwin64 b/gcc/config/rs6000/t-darwin64-biarch index b0a04c7d89d..b0a04c7d89d 100644 --- a/gcc/config/rs6000/t-darwin64 +++ b/gcc/config/rs6000/t-darwin64-biarch diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index a2c10124577..140ef474a92 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -981,7 +981,7 @@ (VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "v") (match_operand:SI 2 "nonmemory_operand" "an")))] "TARGET_VX" - "<vec_shifts_mnem><bhfgq>\t%v0,%v1,%Y2" + "<vec_shifts_mnem><bhfgq>\t%v0,%v1,<addr_style_op_ops>" [(set_attr "op_type" "VRS")]) ; Shift each element by corresponding vector element diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index a1bf557d3eb..7af62d599b9 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -7381,7 +7381,7 @@ visl") "" { rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); - rtx r_label = copy_to_reg (operands[1]); + rtx r_label = operands[1]; rtx r_sp = adjust_address (operands[2], Pmode, 0); rtx r_fp = operands[3]; rtx r_i7 = adjust_address (operands[2], Pmode, GET_MODE_SIZE (Pmode)); @@ -7394,9 +7394,18 @@ visl") emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); - /* Restore frame pointer for containing function. */ - emit_move_insn (hard_frame_pointer_rtx, r_fp); + r_label = copy_to_reg (r_label); + + /* Restore the frame pointer and stack pointer. We must use a + temporary since the setjmp buffer may be a local. */ + r_fp = copy_to_reg (r_fp); emit_stack_restore (SAVE_NONLOCAL, r_sp); + r_i7 = copy_to_reg (r_i7); + + /* Ensure the frame pointer move is not optimized. */ + emit_insn (gen_blockage ()); + emit_clobber (hard_frame_pointer_rtx); + emit_move_insn (hard_frame_pointer_rtx, r_fp); emit_move_insn (i7, r_i7); /* USE of hard_frame_pointer_rtx added for consistency; @@ -7405,8 +7414,7 @@ visl") emit_use (stack_pointer_rtx); emit_use (i7); - emit_jump_insn (gen_indirect_jump (r_label)); - emit_barrier (); + emit_indirect_jump (r_label); DONE; }) |