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Diffstat (limited to 'gcc/doc/md.texi')
| -rw-r--r-- | gcc/doc/md.texi | 125 |
1 files changed, 45 insertions, 80 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 3ed88d02729..822ec14998f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1,5 +1,5 @@ -@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, 2002 -@c Free Software Foundation, Inc. +@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, +@c 2002, 2003 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -898,7 +898,7 @@ digit is used together with letters within the same alternative, the digit should come last. This number is allowed to be more than a single digit. If multiple -digits are encountered consecutavely, they are interpreted as a single +digits are encountered consecutively, they are interpreted as a single decimal integer. There is scant chance for ambiguity, since to-date it has never been desirable that @samp{10} be interpreted as matching either operand 1 @emph{or} operand 0. Should this be desired, one @@ -965,7 +965,7 @@ The machine description macro @code{REG_CLASS_FROM_LETTER} has first cut at the otherwise unused letters. If it evaluates to @code{NO_REGS}, then @code{EXTRA_CONSTRAINT} is evaluated. -A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain +A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain types of memory references that affect other insn operands. @end ifset @end table @@ -1376,60 +1376,6 @@ An item in the constant pool A symbol in the text segment of the current file @end table -@item AMD 29000 family---@file{a29k.h} -@table @code -@item l -Local register 0 - -@item b -Byte Pointer (@samp{BP}) register - -@item q -@samp{Q} register - -@item h -Special purpose register - -@item A -First accumulator register - -@item a -Other accumulator register - -@item f -Floating point register - -@item I -Constant greater than 0, less than 0x100 - -@item J -Constant greater than 0, less than 0x10000 - -@item K -Constant whose high 24 bits are on (1) - -@item L -16-bit constant whose high 8 bits are on (1) - -@item M -32-bit constant whose high 16 bits are on (1) - -@item N -32-bit negative constant that fits in 8 bits - -@item O -The constant 0x80000000 or, on the 29050, any 32-bit constant -whose low 16 bits are 0. - -@item P -16-bit negative constant that fits in 8 bits - -@item G -@itemx H -A floating point constant (in @code{asm} statements, use the machine -independent @samp{E} or @samp{F} instead) -@end table - @item AVR family---@file{avr.h} @table @code @item l @@ -1609,7 +1555,7 @@ Second floating point register @samp{c} register @item C -Specifies constant that can be easilly constructed in SSE register without +Specifies constant that can be easily constructed in SSE register without loading it from memory. @item d @@ -2078,10 +2024,27 @@ Constants in the range @minus{}8 to 2 @item SPARC---@file{sparc.h} @table @code @item f -Floating-point register that can hold 32- or 64-bit values. +Floating-point register on the SPARC-V8 architecture and +lower floating-point register on the SPARC-V9 architecture. @item e -Floating-point register that can hold 64- or 128-bit values. +Floating-point register. It is equivalent to @samp{f} on the +SPARC-V8 architecture and contains both lower and upper +floating-point registers on the SPARC-V9 architecture. + +@item c +Floating-point condition code register. + +@item d +Lower floating-point register. It is only valid on the SPARC-V9 +architecture when the Visual Instruction Set is available. + +@item b +Floating-point register. It is only valid on the SPARC-V9 architecture +when the Visual Instruction Set is available. + +@item h +64-bit global or out register for the SPARC-V8+ architecture. @item I Signed 13-bit constant @@ -2104,6 +2067,9 @@ Same as @samp{K}, except that it verifies that bits that are not in the lower 32-bit range are all zero. Must be used instead of @samp{K} for modes wider than @code{SImode} +@item O +The constant 4096 + @item G Floating-point zero @@ -2306,7 +2272,7 @@ A memory reference that is a stack push. A memory reference that is a stack pop. @item S -A memory reference that refers to an constant address of known value. +A memory reference that refers to a constant address of known value. @item T The register indicated by Rx (not implemented yet). @@ -2494,8 +2460,7 @@ Write the generated insn as a @code{parallel} with elements being a @code{set} of one register from the appropriate memory location (you may also need @code{use} or @code{clobber} elements). Use a @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See -@file{a29k.md} and @file{rs6000.md} for examples of the use of this insn -pattern. +@file{rs6000.md} for examples of the use of this insn pattern. @cindex @samp{store_multiple} instruction pattern @item @samp{store_multiple} @@ -4249,7 +4214,7 @@ instruction is always valid, as compiler expect identical behavior of new jump. When new sequence contains multiple jump instructions or new labels, more assistance is needed. Splitter is required to create only unconditional jumps, or simple conditional jump instructions. Additionally it must attach a -@code{REG_BR_PROB} note to each conditional jump. An global variable +@code{REG_BR_PROB} note to each conditional jump. A global variable @code{split_branch_probability} hold the probability of original branch in case it was an simple conditional jump, @minus{}1 otherwise. To simplify recomputing of edge frequencies, new sequence is required to have only @@ -5368,7 +5333,7 @@ The first one is a data dependence delay determining @dfn{instruction latency time}. The instruction execution is not started until all source data have been evaluated by prior instructions (there are more complex cases when the instruction execution starts even when the data -are not availaible but will be ready in given time after the +are not available but will be ready in given time after the instruction execution start). Taking the data dependence delays into account is simple. The data dependence (true, output, and anti-dependence) delay between two instructions is given by a @@ -5549,8 +5514,8 @@ in such processors and suggestions for their representation. @cindex automaton based pipeline description This section describes constructions of the automaton based processor -pipeline description. The order of all mentioned below constructions -in the machine description file is not important. +pipeline description. The order of constructions within the machine +description file is not important. @findex define_automaton @cindex pipeline hazard recognizer @@ -5558,7 +5523,7 @@ The following optional construction describes names of automata generated and used for the pipeline hazards recognition. Sometimes the generated finite state automaton used by the pipeline hazard recognizer is large. If we use more than one automaton and bind functional -units to the automata, the summary size of the automata usually is +units to the automata, the total size of the automata is usually less than the size of the single automaton. If there is no one such construction, only one finite state automaton is generated. @@ -5568,12 +5533,12 @@ construction, only one finite state automaton is generated. @var{automata-names} is a string giving names of the automata. The names are separated by commas. All the automata should have unique names. -The automaton name is used in construction @code{define_cpu_unit} and +The automaton name is used in the constructions @code{define_cpu_unit} and @code{define_query_cpu_unit}. @findex define_cpu_unit @cindex processor functional units -Each processor functional unit used in description of instruction +Each processor functional unit used in the description of instruction reservations should be described by the following construction. @smallexample @@ -5634,7 +5599,7 @@ is negative, the cost is considered to be zero). You can always change the default costs for any description by using the target hook @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). -@var{insn-names} is a string giving the internal name of the insn. The +@var{insn-name} is a string giving the internal name of the insn. The internal names are used in constructions @code{define_bypass} and in the automaton description file generated for debugging. The internal name has nothing in common with the names in @code{define_insn}. It is a @@ -5720,7 +5685,7 @@ the common part by the following construction @var{reservation-name} is a string giving name of @var{regexp}. Functional unit names and reservation names are in the same name space. So the reservation names should be different from the -functional unit names and can not be reserved name @samp{nothing}. +functional unit names and can not be the reserved name @samp{nothing}. @findex define_bypass @cindex instruction latency time @@ -5807,8 +5772,8 @@ code. Currently there are the following options: @itemize @bullet @item @dfn{no-minimization} makes no minimization of the automaton. This is -only worth to do when we are going to query CPU functional unit -reservations in an automaton state. +only worth to do when we are debugging the description and need to +look more accurately at reservations of states. @item @dfn{time} means printing additional time statistics about @@ -5860,16 +5825,16 @@ incurred. To describe all of this we could specify @smallexample (define_cpu_unit "div") -(define_insn_reservation "simple" 2 (eq_attr "cpu" "int") +(define_insn_reservation "simple" 2 (eq_attr "type" "int") "(i0_pipeline | i1_pipeline), (port0 | port1)") -(define_insn_reservation "mult" 4 (eq_attr "cpu" "mult") +(define_insn_reservation "mult" 4 (eq_attr "type" "mult") "i1_pipeline, nothing*2, (port0 | port1)") -(define_insn_reservation "div" 8 (eq_attr "cpu" "div") +(define_insn_reservation "div" 8 (eq_attr "type" "div") "i1_pipeline, div*7, div + (port0 | port1)") -(define_insn_reservation "float" 3 (eq_attr "cpu" "float") +(define_insn_reservation "float" 3 (eq_attr "type" "float") "f_pipeline, nothing, (port0 | port1)) (define_bypass 4 "float" "simple,mult,div") @@ -5885,7 +5850,7 @@ and use it in all @code{define_insn_reservation} as in the following construction @smallexample -(define_insn_reservation "simple" 2 (eq_attr "cpu" "int") +(define_insn_reservation "simple" 2 (eq_attr "type" "int") "(i0_pipeline | i1_pipeline), finish") @end smallexample |