diff options
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/arm-neon-intrinsics.texi | 180 | ||||
| -rw-r--r-- | gcc/doc/extend.texi | 42 | ||||
| -rw-r--r-- | gcc/doc/install.texi | 2 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 4 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 20 | ||||
| -rw-r--r-- | gcc/doc/options.texi | 21 |
6 files changed, 173 insertions, 96 deletions
diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi index a75e5821e2b..14e6264aeaa 100644 --- a/gcc/doc/arm-neon-intrinsics.texi +++ b/gcc/doc/arm-neon-intrinsics.texi @@ -972,6 +972,38 @@ +@subsubsection Fused-multiply-accumulate + +@itemize @bullet +@item float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vfmaq_f32 (float32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Fused-multiply-subtract + +@itemize @bullet +@item float32x2_t vfms_f32 (float32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vfmsq_f32 (float32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + @subsubsection Subtraction @itemize @bullet @@ -1497,24 +1529,6 @@ @subsubsection Comparison (greater-than-or-equal-to) @itemize @bullet -@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} -@end itemize - - -@itemize @bullet -@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} -@end itemize - - -@itemize @bullet -@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} -@end itemize - - -@itemize @bullet @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1539,20 +1553,20 @@ @itemize @bullet -@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1580,28 +1594,28 @@ @end itemize - - -@subsubsection Comparison (less-than-or-equal-to) - @itemize @bullet -@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} +@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} +@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} +@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} @end itemize + + +@subsubsection Comparison (less-than-or-equal-to) + @itemize @bullet @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1627,20 +1641,20 @@ @itemize @bullet -@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1668,28 +1682,28 @@ @end itemize - - -@subsubsection Comparison (greater-than) - @itemize @bullet -@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} +@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} +@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} +@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} @end itemize + + +@subsubsection Comparison (greater-than) + @itemize @bullet @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1715,20 +1729,20 @@ @itemize @bullet -@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1756,28 +1770,28 @@ @end itemize - - -@subsubsection Comparison (less-than) - @itemize @bullet -@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} +@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} +@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} +@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} @end itemize + + +@subsubsection Comparison (less-than) + @itemize @bullet @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1803,20 +1817,20 @@ @itemize @bullet -@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1844,6 +1858,24 @@ @end itemize +@itemize @bullet +@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + @subsubsection Comparison (absolute greater-than-or-equal-to) @@ -4810,13 +4842,13 @@ @itemize @bullet @item uint64_t vgetq_lane_u64 (uint64x2_t, const int) -@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}} @end itemize @itemize @bullet @item int64_t vgetq_lane_s64 (int64x2_t, const int) -@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}} @end itemize diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index a07539a4adb..6bf929a5c40 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -2682,17 +2682,16 @@ function through the function vector will reduce code size, however; the function vector has a limited size (maximum 128 entries on the H8/300 and 64 entries on the H8/300H and H8S) and shares space with the interrupt vector. -In SH2A target, this attribute declares a function to be called using the +On SH2A targets, this attribute declares a function to be called using the TBR relative addressing mode. The argument to this attribute is the entry number of the same function in a vector table containing all the TBR -relative addressable functions. For the successful jump, register TBR -should contain the start address of this TBR relative vector table. -In the startup routine of the user application, user needs to care of this -TBR register initialization. The TBR relative vector table can have at -max 256 function entries. The jumps to these functions will be generated -using a SH2A specific, non delayed branch instruction JSR/N @@(disp8,TBR). -You must use GAS and GLD from GNU binutils version 2.7 or later for -this attribute to work correctly. +relative addressable functions. For correct operation the TBR must be setup +accordingly to point to the start of the vector table before any functions with +this attribute are invoked. Usually a good place to do the initialization is +the startup routine. The TBR relative vector table can have at max 256 function +entries. The jumps to these functions will be generated using a SH2A specific, +non delayed branch instruction JSR/N @@(disp8,TBR). You must use GAS and GLD +from GNU binutils version 2.7 or later for this attribute to work correctly. Please refer the example of M16C target, to see the use of this attribute while declaring a function, @@ -3251,6 +3250,13 @@ with the notable exceptions of @code{qsort} and @code{bsearch} that take function pointer arguments. The @code{nothrow} attribute is not implemented in GCC versions earlier than 3.3. +@item nosave_low_regs +@cindex @code{nosave_low_regs} attribute +Use this attribute on SH targets to indicate that an @code{interrupt_handler} +function should not save and restore registers R0..R7. This can be used on SH3* +and SH4* targets which have a second R0..R7 register bank for non-reentrant +interrupt handlers. + @item optimize @cindex @code{optimize} function attribute The @code{optimize} attribute is used to specify that a function is to @@ -3428,6 +3434,11 @@ prologue and epilogue that realigns the runtime stack if necessary. This supports mixing legacy codes that run with a 4-byte aligned stack with modern codes that keep a 16-byte stack for SSE compatibility. +@item renesas +@cindex @code{renesas} attribute +On SH targets this attribute specifies that the function or struct follows the +Renesas ABI. + @item resbank @cindex @code{resbank} attribute On the SH2A target, this attribute enables the high-speed register @@ -3538,6 +3549,7 @@ If both @code{signal} and @code{interrupt} are specified for the same function, @code{signal} will be silently ignored. @item sp_switch +@cindex @code{sp_switch} attribute Use this attribute on the SH to indicate an @code{interrupt_handler} function should switch to an alternate stack. It expects a string argument that names a global variable holding the address of the @@ -3929,10 +3941,16 @@ on data in the tiny data section. Note the tiny data area is limited to slightly under 32kbytes of data. @item trap_exit +@cindex @code{trap_exit} attribute Use this attribute on the SH for an @code{interrupt_handler} to return using @code{trapa} instead of @code{rte}. This attribute expects an integer argument specifying the trap number to be used. +@item trapa_handler +@cindex @code{trapa_handler} attribute +On SH targets this function attribute is similar to @code{interrupt_handler} +but it does not save and restore all registers. + @item unused @cindex @code{unused} attribute. This attribute, attached to a function, means that the function is meant @@ -6751,13 +6769,13 @@ random value. In addition, @code{__builtin_frame_address} may be used to determine if the top of the stack has been reached. Additional post-processing of the returned value may be needed, see -@code{__builtin_extract_return_address}. +@code{__builtin_extract_return_addr}. This function should only be used with a nonzero argument for debugging purposes. @end deftypefn -@deftypefn {Built-in Function} {void *} __builtin_extract_return_address (void *@var{addr}) +@deftypefn {Built-in Function} {void *} __builtin_extract_return_addr (void *@var{addr}) The address as returned by @code{__builtin_return_address} may have to be fed through this function to get the actual encoded address. For example, on the 31-bit S/390 platform the highest bit has to be masked out, or on SPARC @@ -6768,7 +6786,7 @@ If no fixup is needed, this function simply passes through @var{addr}. @end deftypefn @deftypefn {Built-in Function} {void *} __builtin_frob_return_address (void *@var{addr}) -This function does the reverse of @code{__builtin_extract_return_address}. +This function does the reverse of @code{__builtin_extract_return_addr}. @end deftypefn @deftypefn {Built-in Function} {void *} __builtin_frame_address (unsigned int @var{level}) diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index cbd49f50d90..e7d5e10059d 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -3151,7 +3151,7 @@ This is a synonym for @samp{x86_64-*-solaris2.1[0-9]*}. @heading @anchor{arm-x-eabi}arm-*-eabi ARM-family processors. Subtargets that use the ELF object format require GNU binutils 2.13 or newer. Such subtargets include: -@code{arm-*-netbsdelf}, @code{arm-*-*linux-gnueabi} +@code{arm-*-netbsdelf}, @code{arm-*-*linux-*} and @code{arm-*-rtemseabi}. @html diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cb5de9e1993..fbab2935b74 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11133,6 +11133,7 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @samp{armv6}, @samp{armv6j}, @samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, +@samp{armv8-a}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. @option{-march=native} causes the compiler to auto-detect the architecture @@ -11146,7 +11147,8 @@ This specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, -@samp{vfpv4-d16}, @samp{fpv4-sp-d16} and @samp{neon-vfpv4}. +@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, +@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}. If @option{-msoft-float} is specified this specifies the format of floating-point values. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 02ee623a1b7..57d0be8c7db 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -665,6 +665,22 @@ as follows, having the output control string start with a @samp{@@}: @end group @end smallexample +If you just need a little bit of C code in one (or a few) alternatives, +you can use @samp{*} inside of a @samp{@@} multi-alternative template: + +@smallexample +@group +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=r,<,m") + (const_int 0))] + "" + "@@ + clrreg %0 + * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\"; + clrmem %0") +@end group +@end smallexample + @node Predicates @section Predicates @cindex predicates @@ -5561,7 +5577,9 @@ iterations as a @code{const_int} or @code{const0_rtx} if this cannot be determined until run-time; operand 2 is the actual or estimated maximum number of iterations as a @code{const_int}; operand 3 is the number of enclosed loops as a @code{const_int} (an innermost loop has a value of -1); operand 4 is the label to jump to if the register is nonzero. +1); operand 4 is the label to jump to if the register is nonzero; +operand 5 is const1_rtx if the loop in entered at its top, const0_rtx +otherwise. @xref{Looping Patterns}. This optional instruction pattern should be defined for machines with diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi index 9c004c8cd3f..f6a31f8d4c7 100644 --- a/gcc/doc/options.texi +++ b/gcc/doc/options.texi @@ -343,8 +343,8 @@ for the option. If the option is attached to @samp{target_flags}, the script will set the macro @code{MASK_@var{name}} to the appropriate bitmask. It will also declare a @code{TARGET_@var{name}} macro that has the value 1 when the option is active and 0 otherwise. If you use @code{Var} -to attach the option to a different variable, the associated macros are -called @code{OPTION_MASK_@var{name}} and @code{OPTION_@var{name}} respectively. +to attach the option to a different variable, the bitmask macro with be +called @code{OPTION_MASK_@var{name}}. @item InverseMask(@var{othername}) @itemx InverseMask(@var{othername}, @var{thisname}) @@ -460,14 +460,21 @@ value of @option{-fmath-errno} for languages that do not use @code{errno}. @item EnabledBy(@var{opt}) -If not explicitly set, the option is set to the value of @option{-@var{opt}}. +@itemx EnabledBy(@var{opt} && @var{opt2}) +If not explicitly set, the option is set to the value of +@option{-@var{opt}}. The second form specifies that the option is +only set if both @var{opt} and @var{opt2} are set. @item LangEnabledBy(@var{language}, @var{opt}) +@itemx LangEnabledBy(@var{language}, @var{opt}, @var{posarg}, @var{negarg}) When compiling for the given language, the option is set to the value -of @option{-@var{opt}}, if not explicitly set. It is possible to -specify several different languages. Each @var{language} must have -been declared by an earlier @code{Language} record. @xref{Option file -format}. +of @option{-@var{opt}}, if not explicitly set. In the second form, if +@var{opt} is used in the positive form then @var{posarg} is considered +to be passed to the option, and if @var{opt} is used in the negative +form then @var{negarg} is considered to be passed to the option. It +is possible to specify several different languages. Each +@var{language} must have been declared by an earlier @code{Language} +record. @xref{Option file format}. @item NoDWARFRecord The option is omitted from the producer string written by |