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-rw-r--r--gcc/target.def13
1 files changed, 0 insertions, 13 deletions
diff --git a/gcc/target.def b/gcc/target.def
index 89c2c637621..d27dbea5063 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -5359,19 +5359,6 @@ for the primary source file, immediately after printing\n\
this to be done. The default is false.",
bool, false)
-/* True if the target is allowed to reorder memory accesses unless
- synchronization is explicitly requested. */
-DEFHOOKPOD
-(relaxed_ordering,
- "If set to @code{true}, means that the target's memory model does not\n\
-guarantee that loads which do not depend on one another will access\n\
-main memory in the order of the instruction stream; if ordering is\n\
-important, an explicit memory barrier must be used. This is true of\n\
-many recent processors which implement a policy of ``relaxed,''\n\
-``weak,'' or ``release'' memory consistency, such as Alpha, PowerPC,\n\
-and ia64. The default is @code{false}.",
- bool, false)
-
/* Returns true if we should generate exception tables for use with the
ARM EABI. The effects the encoding of function exception specifications. */
DEFHOOKPOD