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AgeCommit message (Expand)Author
2018-03-28[arm] PR target/85026: Fix ldrsh length estimate in Thumb stateKyrylo Tkachov
2017-06-02PR71607: Fix ICE when loading constantPrakhar Bahuguna
2017-04-10[ARM] Add source mode to coprocessor pattern SETsKyrylo Tkachov
2017-03-23[ARM] PR target/71436: Restrict *load_multiple pattern till after LRAKyrylo Tkachov
2017-01-25[ARM] PR target/79145 Fix xordi3 expander for immediate operands in iWMMXtKyrylo Tkachov
2017-01-06[ARM] Implement support for ACLE Coprocessor MCRR and MRRC intrinsicsAndre Vieira
2017-01-06[ARM] Implement support for ACLE Coprocessor MCR and MRC intrinsicsAndre Vieira
2017-01-06[ARM] Implement support for ACLE Coprocessor LDC and STC intrinsicsAndre Vieira
2017-01-06[ARM] Implement support for ACLE Coprocessor CDP intrinsicsAndre Vieira
2017-01-01 Update copyright years.Jakub Jelinek
2016-12-16The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2Wilco Dijkstra
2016-12-02ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_callAndre Vieira
2016-11-23[Patch 16/17 libgcc ARM] Half to double precision conversionsJames Greenhalgh
2016-11-172016-11-17 Bernd Edlinger <bernd.edlinger@hotmail.de>Bernd Edlinger
2016-11-16Fix ICE on empty FIQ interrupt handler on ARMThomas Preud'homme
2016-11-16[ARM] PR target/78364: Add proper restrictions to zero and sign_extract patte...Kyrylo Tkachov
2016-10-172016-10-17 Bernd Edlinger <bernd.edlinger@hotmail.de>Bernd Edlinger
2016-10-13[ARM] Remove redundant TARGET_VFPRichard Earnshaw
2016-09-29[ARM] Fix new constraints and attributes of SI/HI data movement patternsMatthew Wahab
2016-09-27Commit files missed in revision 240541.Matthew Wahab
2016-09-23[PATCH 7/17][ARM] Add FP16 data movement instructions.Matthew Wahab
2016-09-23[PATCH 5/17][ARM] Enable HI mode moves for floating point values.Matthew Wahab
2016-09-22[ARM] Add support for -mpure-code optionAndre Vieira
2016-08-242016-08-24 Michael Collison <michael.collison@linaro.org>Michael Collison
2016-08-23[ARM] Fix predicable_short_it attribute for arm_movqi_insnChristophe Lyon
2016-07-132016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com>Thomas Preud'homme
2016-07-132016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com>Thomas Preud'homme
2016-07-072016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>Thomas Preud'homme
2016-06-11[ARM] length pop* pattern in epilogue correctlyJiong Wang
2016-06-06[1/3][ARM] Keep ctz expressions together until after reloadKyrylo Tkachov
2016-05-24[ARM][3/4] Cleanup casts from INTVAL to [unsigned] HOST_WIDE_INTKyrylo Tkachov
2016-05-24[ARM][2/4] Replace casts of 1 to HOST_WIDE_INT by HOST_WIDE_INT_1 and HOST_WI...Kyrylo Tkachov
2016-05-16[ARM] Enable __fp16 as a function parameter and return type.Matthew Wahab
2016-05-09[ARM] Add mode to probe_stack set operandsKyrylo Tkachov
2016-05-07Emit vmov.i64 to load 0.0 into FP reg when neon enabled.Jim Wilson
2016-03-032016-03-03 Michael Collison <michael.collison@linaro.org>Michael Collison
2016-02-17[ARM] PR target/69161: Don't ignore mode when matching comparison operator in...Kyrylo Tkachov
2016-01-04 Update copyright years.Jakub Jelinek
2015-12-16[ARM] PR target/68648: Fold NOT of CONST_INT in andsi_iorsi3_notsi splitterKyrylo Tkachov
2015-12-07Add scheduling model for Exynos M1Evandro Menezes
2015-12-04 PR middle-end/65958Eric Botcazou
2015-12-04[ARM] PR target/68214: Delete IP-reg-clobbering call-through-mem patternsKyrylo Tkachov
2015-11-20[AArch64] Add attribute for compatibility with ARM pipeline modelsEvandro Menezes
2015-11-20[ARM] Do not expand movmisalign pattern if not in 32-bit modeKyrylo Tkachov
2015-11-20[ARM] PR 68149 Fix ICE in unaligned_loaddi splitKyrylo Tkachov
2015-11-12[PATCH][ARM]Fix addsi3_compare_op2 pattern.Renlin Li
2015-11-062015-11-06 Michael Collison <michael.collison@linaro.orgMichael Collison
2015-11-06[Patch ARM] Unified assembler in ARM state.Ramana Radhakrishnan
2015-10-09[Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patternsRamana Radhakrishnan
2015-10-06 * config/arm/arm.c (arm_emit_probe_stack_range): Adjust comment.Eric Botcazou
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