From 97985bbf0d1d762b3353c3bececed5d5e2f56969 Mon Sep 17 00:00:00 2001 From: Kelvin Nilsen Date: Tue, 11 Apr 2017 18:23:06 +0000 Subject: working git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/bz80315@246853 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/config/rs6000/rs6000.c | 6 ++--- gcc/testsuite/gcc.target/powerpc/pr80315-1.c | 37 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr80315-2.c | 37 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr80315-3.c | 39 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr80315-4.c | 39 ++++++++++++++++++++++++++++ 5 files changed, 155 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr80315-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr80315-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr80315-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr80315-4.c diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7822a9d4566..ea60be31350 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15669,14 +15669,14 @@ rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (arg1, 2)) { error ("argument 2 must be 0 or 1"); - return const0_rtx; + return CONST0_RTX (tmode); } STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST || wi::geu_p (arg1, 16)) + if (TREE_CODE (arg2) != INTEGER_CST || wi::geu_p (arg2, 16)) { error ("argument 3 must be in the range 0..15"); - return const0_rtx; + return CONST0_RTX (tmode); } } diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c new file mode 100644 index 00000000000..66fabce65ce --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +int +main() +{ + __attribute__((altivec(vector__))) unsigned int test, res; + const int s0 = 0; + int mask; + + /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ + + /* kelvin comments to be removed: + * expands to crypto_vshasegmaw + * + * note from altivec.h: + * #define vec_shasigma_be __builtin_crypto_vshasigma + * (kelvin wonders if this macro is conditional upon be?) + * + * crypto.md (under "TARGET_CRYPTO" support) + * (define_insn "crypto_vshasigma" ... expands to + * "vshasigma %0,%1,%2,%3" + * + * rs6000-builtin.def has: + * BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw); + * BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad); + * BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") + * + * special handling in rs6000.c, if + * icode == (CODE_FOR_crypto_vshasigmaw or CODE_FOR_crypto_vshasigmad) + * within function rs6000_expand_ternop_builtin () + */ + res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error "argument 3 must be in the range 0..15" } */ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c new file mode 100644 index 00000000000..7a7df332248 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +int +main () +{ + __attribute__((altivec(vector__))) unsigned long long test, res; + const int s0 = 0; + int mask; + + /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ + + /* kelvin comments to be removed: + * expands to crypto_vshasegmaw + * + * note from altivec.h: + * #define vec_shasigma_be __builtin_crypto_vshasigma + * (kelvin wonders if this macro is conditional upon be?) + * + * crypto.md (under "TARGET_CRYPTO" support) + * (define_insn "crypto_vshasigma" ... expands to + * "vshasigma %0,%1,%2,%3" + * + * rs6000-builtin.def has: + * BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw); + * BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad); + * BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") + * + * special handling in rs6000.c, if + * icode == (CODE_FOR_crypto_vshasigmaw or CODE_FOR_crypto_vshasigmad) + * within function rs6000_expand_ternop_builtin () + */ + res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error "argument 3 must be in the range 0..15" } */ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c new file mode 100644 index 00000000000..d178d77f783 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include + +vector unsigned int +main () +{ + vector unsigned int test, res; + const int s0 = 0; + int mask; + + /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ + + /* kelvin comments to be removed: + * expands to crypto_vshasegmaw + * + * note from altivec.h: + * #define vec_shasigma_be __builtin_crypto_vshasigma + * (kelvin wonders if this macro is conditional upon be?) + * + * crypto.md (under "TARGET_CRYPTO" support) + * (define_insn "crypto_vshasigma" ... expands to + * "vshasigma %0,%1,%2,%3" + * + * rs6000-builtin.def has: + * BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw); + * BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad); + * BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") + * + * special handling in rs6000.c, if + * icode == (CODE_FOR_crypto_vshasigmaw or CODE_FOR_crypto_vshasigmad) + * within function rs6000_expand_ternop_builtin () + */ + res = vec_shasigma_be (test, 1, 0xff); /* { dg-error "argument 3 must be in the range 0..15" } */ + return res; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c new file mode 100644 index 00000000000..76d01d2cb89 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include + +vector unsigned long long int +main () +{ + vector unsigned long long int test, res; + const int s0 = 0; + int mask; + + /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ + + /* kelvin comments to be removed: + * expands to crypto_vshasegmaw + * + * note from altivec.h: + * #define vec_shasigma_be __builtin_crypto_vshasigma + * (kelvin wonders if this macro is conditional upon be?) + * + * crypto.md (under "TARGET_CRYPTO" support) + * (define_insn "crypto_vshasigma" ... expands to + * "vshasigma %0,%1,%2,%3" + * + * rs6000-builtin.def has: + * BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw); + * BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad); + * BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") + * + * special handling in rs6000.c, if + * icode == (CODE_FOR_crypto_vshasigmaw or CODE_FOR_crypto_vshasigmad) + * within function rs6000_expand_ternop_builtin () + */ + res = vec_shasigma_be (test, 1, 0xff); /* { dg-error "argument 3 must be in the range 0..15" } */ + return res; +} -- cgit v1.2.3