From c0c667a4e2cb1c2c64348d890a2a2d2119c3d103 Mon Sep 17 00:00:00 2001 From: Kelvin Nilsen Date: Wed, 30 Mar 2016 20:16:48 +0000 Subject: gcc/ChangeLog: 2016-03-30 Kelvin Nilsen * doc/extend.texi: Document __builtin_darn (void), __builtin_darn_raw (void), and __builtin_darn_32 (void) built-in functions. * config/rs6000/rs6000.c: Add #define RS6000_BUILTIN_0 and #undef RS6000_BUILTIN_0 directives to surround each occurrence of #include "rs6000-bultin.def". (rs6000_builtin_mask_calculate): Add in the RS6000_BTM_MODULO and RS6000_BTM_64BIT flags to the returned mask, depending on configuration. (def_builtin): Correct an error in the assignments made to the debugging variable attr_string. (rs6000_expand_builtin): Add support for no-operand built-in functions. (builtin_function_type): Remove fatal_error assertion that is no longer valid. (rs6000_common_init_builtins): Add support for no-operand built-in functions. * config/rs6000/altivec.h: Add macro definitions for darn, darn_32, and darn_raw. * config/rs6000/rs6000.h (RS6000_BTM_MODULO): New macro definition. (RS6000_BTC_PURE): Enhance comment associated with this macro definition. (RS6000_BTM_64BIT): New macro definition. * config/rs6000/rs6000-builtin.def (RS6000_BUILTIN_0): Introduce use and documentation of this new macro. (BU_B9_MISC_1): New macro definition. (BU_P9_64BIT_MISC_0): New macro definition. (BU_P9_MISC_0): New macro definition. ("darn_32"): New builtin definition. ("darn_raw"): New builtin definition. ("darn"): New builtin. * config/rs6000/altivec.md (UNSPEC_DARN): New unspec constant. (UNSPEC_DARN_32): New unspec constant. (UNSPEC_DARN_RAW): New unspec constant. ("darn_32): New instruction. ("darn_raw"): New instruction. ("darn"): New instruction. gcc/testsuite/ChangeLog: 2016-03-30 Kelvin Nilsen * gcc.target/powerpc/darn-0.c: New test. * gcc.target/powerpc/darn-1.c: New test. * gcc.target/powerpc/darn-2.c: New test. git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/pre-gcc7@234599 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog.ibm | 41 ++++++++ gcc/REVISION | 2 +- gcc/config/rs6000/altivec.h | 5 + gcc/config/rs6000/altivec.md | 34 +++++++ gcc/config/rs6000/rs6000-builtin.def | 46 +++++++++ gcc/config/rs6000/rs6000.c | 150 ++++++++++++++++++++++++++++-- gcc/config/rs6000/rs6000.h | 13 ++- gcc/doc/extend.texi | 17 ++++ gcc/testsuite/ChangeLog.ibm | 6 ++ gcc/testsuite/gcc.target/powerpc/darn-0.c | 12 +++ gcc/testsuite/gcc.target/powerpc/darn-1.c | 12 +++ gcc/testsuite/gcc.target/powerpc/darn-2.c | 12 +++ 12 files changed, 338 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/darn-0.c create mode 100644 gcc/testsuite/gcc.target/powerpc/darn-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/darn-2.c diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm index 0f53ed38498..8031b4118e2 100644 --- a/gcc/ChangeLog.ibm +++ b/gcc/ChangeLog.ibm @@ -1,3 +1,44 @@ +2016-03-30 Kelvin Nilsen + + * doc/extend.texi: Document __builtin_darn (void), + __builtin_darn_raw (void), and __builtin_darn_32 (void) built-in + functions. + * config/rs6000/rs6000.c: Add #define RS6000_BUILTIN_0 and #undef + RS6000_BUILTIN_0 directives to surround each occurrence of + #include "rs6000-bultin.def". + (rs6000_builtin_mask_calculate): Add in the RS6000_BTM_MODULO and + RS6000_BTM_64BIT flags to the returned mask, depending on + configuration. + (def_builtin): Correct an error in the assignments made to the + debugging variable attr_string. + (rs6000_expand_builtin): Add support for no-operand built-in + functions. + (builtin_function_type): Remove fatal_error assertion that is no + longer valid. + (rs6000_common_init_builtins): Add support for no-operand built-in + functions. + * config/rs6000/altivec.h: Add macro definitions for darn, + darn_32, and darn_raw. + * config/rs6000/rs6000.h (RS6000_BTM_MODULO): New macro + definition. + (RS6000_BTC_PURE): Enhance comment associated with this macro + definition. + (RS6000_BTM_64BIT): New macro definition. + * config/rs6000/rs6000-builtin.def (RS6000_BUILTIN_0): Introduce + use and documentation of this new macro. + (BU_B9_MISC_1): New macro definition. + (BU_P9_64BIT_MISC_0): New macro definition. + (BU_P9_MISC_0): New macro definition. + ("darn_32"): New builtin definition. + ("darn_raw"): New builtin definition. + ("darn"): New builtin. + * config/rs6000/altivec.md (UNSPEC_DARN): New unspec constant. + (UNSPEC_DARN_32): New unspec constant. + (UNSPEC_DARN_RAW): New unspec constant. + ("darn_32): New instruction. + ("darn_raw"): New instruction. + ("darn"): New instruction. + 2016-03-22 Kelvin Nilsen * config/rs6000/altivec.md: (UNSPEC_VPERMR): New unspec constant. diff --git a/gcc/REVISION b/gcc/REVISION index fbaf3c3723f..7cc7ecafd02 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -[ibm/pre-gcc7 revision 234409] +[ibm/pre-gcc7 revision 234598] diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 36bb1347f59..436e9eae847 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -392,6 +392,11 @@ #define vec_vctzd __builtin_vec_vctzd #define vec_vctzh __builtin_vec_vctzh #define vec_vctzw __builtin_vec_vctzw + +/* Non-Vector additions added in ISA 3.0. */ +#define darn __builtin_darn +#define darn_32 __builtin_darn_32 +#define darn_raw __builtin_darn_raw #endif /* Predicates. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index c5eb4abff7d..16b7cb82ebe 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -74,6 +74,9 @@ UNSPEC_VUNPACK_LO_SIGN_DIRECT UNSPEC_VUPKHPX UNSPEC_VUPKLPX + UNSPEC_DARN + UNSPEC_DARN_32 + UNSPEC_DARN_RAW UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST @@ -3587,6 +3590,37 @@ [(set_attr "length" "4") (set_attr "type" "vecsimple")]) +(define_insn "darn_32" + [(set (match_operand:SI 0 "register_operand" "") + (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] + "TARGET_MODULO" + { + return "darn %0,0"; + } + [(set_attr "type" "add") + (set_attr "length" "4")]) + +(define_insn "darn_raw" + [(set (match_operand:DI 0 "register_operand" "") + (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] + "TARGET_MODULO && TARGET_64BIT" + { + return "darn %0,2"; + } + [(set_attr "type" "add") + (set_attr "length" "4")]) + +(define_insn "darn" + [(set (match_operand:DI 0 "register_operand" "") + (unspec:DI [(const_int 0)] UNSPEC_DARN))] + "TARGET_MODULO && TARGET_64BIT" + { + return "darn %0,1"; + } + [(set_attr "type" "add") + (set_attr "length" "4")]) + + (define_expand "bcd_" [(parallel [(set (reg:CCFP 74) (compare:CCFP diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index b9129024b30..ad03251555c 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -24,6 +24,7 @@ . */ /* Before including this file, some macros must be defined: + RS6000_BUILTIN_0 -- 0 arg builtins RS6000_BUILTIN_1 -- 1 arg builtins RS6000_BUILTIN_2 -- 2 arg builtins RS6000_BUILTIN_3 -- 3 arg builtins @@ -43,6 +44,10 @@ ATTR builtin attribute information. ICODE Insn code of the function that implents the builtin. */ +#ifndef RS6000_BUILTIN_0 + #error "RS6000_BUILTIN_0 is not defined." +#endif + #ifndef RS6000_BUILTIN_1 #error "RS6000_BUILTIN_1 is not defined." #endif @@ -647,6 +652,42 @@ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers, + and they require 64-bit addressing. */ +#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO \ + | RS6000_BTM_64BIT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + /* ISA 3.0 (power9) vector convenience macros. */ /* For the instructions that are encoded as altivec instructions use __builtin_altivec_ as the builtin name. */ @@ -1714,6 +1755,11 @@ BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) +/* 0 argument general-purpose register functions added in ISA 3.0 (power9). */ +BU_P9_MISC_0 (DARN_32, "darn_32", MISC, darn_32) +BU_P9_64BIT_MISC_0 (DARN_RAW, "darn_raw", MISC, darn_raw) +BU_P9_64BIT_MISC_0 (DARN, "darn", MISC, darn) + /* 1 argument vector functions added in ISA 3.0 (power9). */ BU_P9V_AV_1 (VCTZB, "vctzb", CONST, ctzv16qi2) BU_P9V_AV_1 (VCTZH, "vctzh", CONST, ctzv8hi2) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 3e8f278153b..411fa101617 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1139,6 +1139,7 @@ struct processor_costs ppca2_cost = { /* Table that classifies rs6000 builtin functions (pure, const, etc.). */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -1151,6 +1152,9 @@ struct processor_costs ppca2_cost = { #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ + { NAME, ICODE, MASK, ATTR }, + #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, @@ -1196,6 +1200,7 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] = #include "rs6000-builtin.def" }; +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -3629,6 +3634,8 @@ rs6000_builtin_mask_calculate (void) | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) + | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) + | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) @@ -12545,7 +12552,7 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code) /* const function, function only depends on the inputs. */ TREE_READONLY (t) = 1; TREE_NOTHROW (t) = 1; - attr_string = ", pure"; + attr_string = ", const"; } else if ((classify & RS6000_BTC_PURE) != 0) { @@ -12553,7 +12560,7 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code) external state. */ DECL_PURE_P (t) = 1; TREE_NOTHROW (t) = 1; - attr_string = ", const"; + attr_string = ", pure"; } else if ((classify & RS6000_BTC_FP) != 0) { @@ -12585,6 +12592,7 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code) /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12597,6 +12605,7 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code) #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \ @@ -12618,6 +12627,7 @@ static const struct builtin_description bdesc_3arg[] = /* DST operations: void foo (void *, const int, const char). */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12630,6 +12640,7 @@ static const struct builtin_description bdesc_3arg[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12651,6 +12662,7 @@ static const struct builtin_description bdesc_dst[] = /* Simple binary operations: VECc = foo (VECa, VECb). */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12663,6 +12675,7 @@ static const struct builtin_description bdesc_dst[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, @@ -12682,6 +12695,7 @@ static const struct builtin_description bdesc_2arg[] = #include "rs6000-builtin.def" }; +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12694,6 +12708,7 @@ static const struct builtin_description bdesc_2arg[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12716,6 +12731,7 @@ static const struct builtin_description bdesc_altivec_preds[] = }; /* SPE predicates. */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12728,6 +12744,7 @@ static const struct builtin_description bdesc_altivec_preds[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12748,6 +12765,7 @@ static const struct builtin_description bdesc_spe_predicates[] = }; /* SPE evsel predicates. */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12760,6 +12778,7 @@ static const struct builtin_description bdesc_spe_predicates[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12780,6 +12799,7 @@ static const struct builtin_description bdesc_spe_evsel[] = }; /* PAIRED predicates. */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12792,6 +12812,7 @@ static const struct builtin_description bdesc_spe_evsel[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12813,6 +12834,7 @@ static const struct builtin_description bdesc_paired_preds[] = /* ABS* operations. */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12825,6 +12847,7 @@ static const struct builtin_description bdesc_paired_preds[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12847,6 +12870,7 @@ static const struct builtin_description bdesc_abs[] = /* Simple unary operations: VECb = foo (unsigned literal) or VECb = foo (VECa). */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12859,6 +12883,7 @@ static const struct builtin_description bdesc_abs[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, @@ -12878,7 +12903,43 @@ static const struct builtin_description bdesc_1arg[] = #include "rs6000-builtin.def" }; +/* Simple no-argument operations: result = __builtin_darn_32 () */ + +#undef RS6000_BUILTIN_0 +#undef RS6000_BUILTIN_1 +#undef RS6000_BUILTIN_2 +#undef RS6000_BUILTIN_3 +#undef RS6000_BUILTIN_A +#undef RS6000_BUILTIN_D +#undef RS6000_BUILTIN_E +#undef RS6000_BUILTIN_H +#undef RS6000_BUILTIN_P +#undef RS6000_BUILTIN_Q +#undef RS6000_BUILTIN_S +#undef RS6000_BUILTIN_X + +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ + { MASK, ICODE, NAME, ENUM }, + +#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) +#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) + +static const struct builtin_description bdesc_0arg[] = +{ +#include "rs6000-builtin.def" +}; + /* HTM builtins. */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12891,6 +12952,7 @@ static const struct builtin_description bdesc_1arg[] = #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) @@ -12910,6 +12972,7 @@ static const struct builtin_description bdesc_htm[] = #include "rs6000-builtin.def" }; +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -12994,7 +13057,6 @@ rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp) return NULL_RTX; } - static rtx rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target) { @@ -15277,10 +15339,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, } unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK; + /* RS6000_BTC_SPECIAL represents no-operand operators. */ gcc_assert (attr == RS6000_BTC_UNARY || attr == RS6000_BTC_BINARY - || attr == RS6000_BTC_TERNARY); - + || attr == RS6000_BTC_TERNARY + || attr == RS6000_BTC_SPECIAL); + /* Handle simple unary operations. */ d = bdesc_1arg; for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) @@ -15299,6 +15363,13 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, if (d->code == fcode) return rs6000_expand_ternop_builtin (d->icode, exp, target); + /* Handle simple no-argument operations. */ + d = bdesc_0arg; + for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_zeroop_builtin (d->icode, target); + + gcc_assert (false); gcc_unreachable (); } @@ -16638,10 +16709,6 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, while (num_args > 0 && h.mode[num_args] == VOIDmode) num_args--; - if (num_args == 0) - fatal_error (input_location, - "internal error: builtin function %s had no type", name); - ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]]; if (!ret_type && h.uns_p[0]) ret_type = builtin_mode_to_type[h.mode[0]][0]; @@ -16693,6 +16760,7 @@ rs6000_common_init_builtins (void) tree opaque_ftype_opaque = NULL_TREE; tree opaque_ftype_opaque_opaque = NULL_TREE; tree opaque_ftype_opaque_opaque_opaque = NULL_TREE; + tree v2si_ftype = NULL_TREE; tree v2si_ftype_qi = NULL_TREE; tree v2si_ftype_v2si_qi = NULL_TREE; tree v2si_ftype_int_qi = NULL_TREE; @@ -16809,7 +16877,6 @@ rs6000_common_init_builtins (void) if (TARGET_DEBUG_BUILTIN) fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n", d->name); - continue; } @@ -16909,6 +16976,69 @@ rs6000_common_init_builtins (void) def_builtin (d->name, type, d->code); } + + /* Add the simple no-argument operators. */ + d = bdesc_0arg; + for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) + { + machine_mode mode0; + tree type; + HOST_WIDE_INT mask = d->mask; + + if ((mask & builtin_mask) != mask) + { + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_builtin, skip no-argumen %s\n", d->name); + continue; + } + + if (rs6000_overloaded_builtin_p (d->code)) + { + if (! (type = opaque_ftype_opaque)) + type = opaque_ftype_opaque + = build_function_type_list (opaque_V4SI_type_node, + NULL_TREE); + } + else + { + enum insn_code icode = d->icode; + if (d->name == 0) + { + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_builtin, bdesc_0arg[%ld] no name\n", + (long unsigned)i); + + continue; + } + + if (icode == CODE_FOR_nothing) + { + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, + "rs6000_builtin, skip no-argument %s (no code)\n", + d->name); + + continue; + } + + mode0 = insn_data[icode].operand[0].mode; + + if (mode0 == V2SImode) + { + /* code for SPE, not well understood or thoroughly tested */ + if (! (type = v2si_ftype)) + type = v2si_ftype + = build_function_type_list (opaque_V2SI_type_node, + NULL_TREE); + } + + else + type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode, + d->code, d->name); + } + + def_builtin (d->name, type, d->code); + } } /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d7c4aa13cd6..e6c02b672a9 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -664,6 +664,11 @@ extern int rs6000_vector_align[]; #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE #endif +#ifdef TARGET_MODULO +#define RS6000_BTM_MODULO OPTION_MASK_MODULO +#endif + + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a @@ -2647,7 +2652,9 @@ extern int frame_pointer_needed; #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ -#define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ +#define RS6000_BTC_PURE 0x00000200 /* reads global + state/mem and does + not modify global state. */ #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ @@ -2683,6 +2690,7 @@ extern int frame_pointer_needed; #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ +#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ @@ -2702,6 +2710,7 @@ extern int frame_pointer_needed; /* Define builtin enum index. */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -2714,6 +2723,7 @@ extern int frame_pointer_needed; #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, @@ -2733,6 +2743,7 @@ enum rs6000_builtins RS6000_BUILTIN_COUNT }; +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 81365724179..7749bcbf257 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -13832,6 +13832,23 @@ The @code{__builtin_divde}, @code{__builtin_divdeo}, @code{__builtin_divdeu}, @code{__builtin_divdeou} functions require a 64-bit environment support ISA 2.06 or later. +The following built-in functions are available for the PowerPC family +of processors, starting with ISA 3.0 or later (@option{-mcpu=power9} +or @option{-mmodulo}): +@smallexample +long long __builtin_darn (void); +long long __builtin_darn_raw (void); +int __builtin_darn_32 (void); +@end smallexample + +The @code{__builtin_darn} and @code{__builtin_darn_raw} +functions require a +64-bit environment supporting ISA 3.0 or later. +The @code{__builtin_darn} function provides a 64-bit conditioned +random number. The @code{__builtin_darn_raw} function provides a +64-bit raw random number. The @code{__builtin_darn_32} function +provides a 32-bit random number. + The following built-in functions are available for the PowerPC family of processors when hardware decimal floating point (@option{-mhard-dfp}) is available: diff --git a/gcc/testsuite/ChangeLog.ibm b/gcc/testsuite/ChangeLog.ibm index 41d5a2ba201..eb65dd14d9f 100644 --- a/gcc/testsuite/ChangeLog.ibm +++ b/gcc/testsuite/ChangeLog.ibm @@ -1,3 +1,9 @@ +2016-03-30 Kelvin Nilsen + + * gcc.target/powerpc/darn-0.c: New test. + * gcc.target/powerpc/darn-1.c: New test. + * gcc.target/powerpc/darn-2.c: New test. + 2016-03-22 Kelvin Nilsen * gcc.target/powerpc/p9-permute.c: Generalize test to run on diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c b/gcc/testsuite/gcc.target/powerpc/darn-0.c new file mode 100644 index 00000000000..00eea3421e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include + +int get_random() +{ + return __builtin_darn_32 (); +} + +/* { dg-final { scan-assembler "darn" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c b/gcc/testsuite/gcc.target/powerpc/darn-1.c new file mode 100644 index 00000000000..1d7c5001262 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-mcpu=power9" } */ +/* { dg-require-effective-target lp64 } */ + +#include + +long long get_conditioned_random() +{ + return __builtin_darn (); +} + +/* { dg-final { scan-assembler "darn" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c b/gcc/testsuite/gcc.target/powerpc/darn-2.c new file mode 100644 index 00000000000..2a9955b5003 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-mcpu=power9" } */ +/* { dg-require-effective-target lp64 } */ + +#include + +long long get_raw_random() +{ + return __builtin_darn_raw (); +} + +/* { dg-final { scan-assembler "darn" } } */ -- cgit v1.2.3