2014-11-14  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r212178..
	2014-06-30  Joseph Myers  <joseph@codesourcery.com>

	* var-tracking.c (add_stores): Return instead of asserting if old
	and new values for conditional store are the same.

2014-11-14  Yvan Roux  <yvan.roux@linaro.org>

	Add Linaro release macros (Linaro only patch.)

	* Makefile.in (LINAROVER, LINAROVER_C, LINAROVER_S): Define.
	(CFLAGS-cppbuiltin.o): Add LINAROVER macro definition.
	(cppbuiltin.o): Depend on $(LINAROVER).
	* cppbuiltin.c (parse_linarover): New.
	(define_GNUC__): Define __LINARO_RELEASE__ and __LINARO_SPIN__ macros.

2014-08-26  venkataramanan-kumar  <venkataramanan.kumar@linaro.org>

	Backport from trunk r205807.
	2013-12-09  Richard Earnshaw  <rearnsha@arm.com>

	* arm.c (mem_ok_for_ldrd_strd): Rename first argument as MEM.  Do
	more address validation checks.

2014-08-15  Yvan Roux  <yvan.roux@linaro.org>

	* LINARO-VERSION: Bump version.

2014-08-14  Yvan Roux  <yvan.roux@linaro.org>

	GCC Linaro 4.8-2014.08 released.
	* LINARO-VERSION: Update.

2014-08-11  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206529, r206530
	2014-01-10  Richard Earnshaw  <rearnsha@arm.com>

	PR target/59744
	* aarch64-modes.def (CC_Zmode): New flags mode.
	* aarch64.c (aarch64_select_cc_mode): Only allow NEG when the condition
	represents an equality.
	(aarch64_get_condition_code): Handle CC_Zmode.
	* aarch64.md (compare_neg<mode>): Restrict to equality operations.

2014-08-11  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204251
	2013-10-31  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
	Yury Gribov  <y.gribov@samsung.com>

	PR sanitizer/58543
	* asan.c (asan_clear_shadow): Allocate a new vreg for temporary
	shadow pointer to avoid clobbering the main one.

2014-04-08  Yvan Roux  <yvan.roux@linaro.org>

	* LINARO-VERSION: Bump version.

2014-04-07  Yvan Roux  <yvan.roux@linaro.org>

	GCC Linaro 4.8-2014.04 released.
	* LINARO-VERSION: Update.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r205105
	2013-11-20  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md: Remove "mode" and "mode2" attributes
	from all insns.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r205050
	2013-11-19  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm.md (zero_extend<mode>di2): Add type attribute.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204852
	2013-11-19  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md: Remove v8type from all insns.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204852
	2013-11-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md: Remove simd_type from all
	patterns.
	* config/aarch64/aarch64.md: Likewise, correct "type" attribute
	where it is incorrect or missing.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204784
	2013-11-14  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-cores.def (example-1): Remove.
	(example-2): Likewise.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* config/aarch64/aarch64.md: Do not include "large.md" or "small.md".
	(generic_sched): Remove "large", "small".
	* config/aarch64/large.md: Delete.
	* config/aarch64/small.md: Delete.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204783
	2013-11-14  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-cores.def (cortex-a57): Tune for cortexa15.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* config/aarch64/aarch64.md: Include cortex-a15 pipeline model.
	(generic_sched): "no" if we are	tuning for cortexa15.
	* config/arm/cortex-a15.md: Include cortex-a15-neon.md by
	relative path.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204782
	2013-11-14  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-arches.def (armv8-a): Tune for cortex-a53.
	* config/aarch64/aarch64.md: Do not include aarch64-generic.md.
	* config/aarch64/aarch64.c (aarch64_tune): Initialize to cortexa53.
	(all_cores): Use cortexa53 when tuning for "generic".
	(aarch64_override_options): Fix comment.
	* config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Set to cortexa53.
	* config/aarch64/aarch64-generic.md: Delete.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r204575
	2013-11-08  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/aarch-common.c
	(search_term): New typedef.
	(shift_rtx_costs): New array.
	(arm_rtx_shift_left_p): New.
	(arm_find_sub_rtx_with_search_term): Likewise.
	(arm_find_sub_rtx_with_code): Likewise.
	(arm_early_load_addr_dep): Add sanity checking.
	(arm_no_early_alu_shift_dep): Likewise.
	(arm_no_early_alu_shift_value_dep): Likewise.
	(arm_no_early_mul_dep): Likewise.
	(arm_no_early_store_addr_dep): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203621
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/neon-schedgen.ml: Remove.
	* config/arm/cortex-a9-neon.md: Remove comment regarding
	neon-schedgen.ml.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203620
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types: Remove old neon types.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203619
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/cortex-a7.md
	(cortex_a7_neon_type): New.
	(cortex_a7_neon_mul): Update for new types.
	(cortex_a7_neon_mla): Likewise.
	(cortex_a7_neon): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203618
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/cortex-a15-neon.md
	(cortex_a15_neon_type): New,

	(cortex_a15_neon_int_1): Remove.
	(cortex_a15_neon_int_2): Likewise.
	(cortex_a15_neon_int_3): Likewise.
	(cortex_a15_neon_int_4): Likewise.
	(cortex_a15_neon_int_5): Likewise.
	(cortex_a15_neon_vqneg_vqabs): Likewise.
	(cortex_a15_neon_vmov): Likewise.
	(cortex_a15_neon_vaba): Likewise.
	(cortex_a15_neon_vaba_qqq): Likewise.
	(cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise.
	(cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
	Likewise.
	(cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a15_neon_mla_qqq_8_16): Likewise.
	(cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar): Likewise.
	(cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise.
	(cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
	(cortex_a15_neon_mul_qqd_32_scalar): Likewise.
	(cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
	(cortex_a15_neon_shift_1): Likewise.
	(cortex_a15_neon_shift_2): Likewise.
	(cortex_a15_neon_shift_3): Likewise.
	(cortex_a15_neon_vshl_ddd): Likewise.
	(cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
	(cortex_a15_neon_vsra_vrsra): Likewise.
	(cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a15_neon_bp_3cycle): Likewise.
	(cortex_a15_neon_ldm_2): Likewise.
	(cortex_a15_neon_stm_2): Likewise.
	(cortex_a15_neon_mcr): Likewise.
	(cortex_a15_neon_mrc): Likewise.
	(cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise.
	(cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise.
	(cortex_a15_neon_fp_vmul_ddd): Likewise.
	(cortex_a15_neon_fp_vmul_qqd): Likewise.
	(cortex_a15_neon_fp_vmla_ddd): Likewise.
	(cortex_a15_neon_fp_vmla_qqq): Likewise.
	(cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise.
	(cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise.
	(cortex_a15_neon_bp_simple): Likewise.
	(cortex_a15_neon_bp_2cycle): Likewise.
	(cortex_a15_neon_bp_3cycle): Likewise.
	(cortex_a15_neon_vld1_1_2_regs): Likewise.
	(cortex_a15_neon_vld1_3_4_regs): Likewise.
	(cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
	(cortex_a15_neon_vld2_4_regs): Likewise.
	(cortex_a15_neon_vld3_vld4): Likewise.
	(cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
	(cortex_a15_neon_vst1_3_4_regs): Likewise.
	(cortex_a15_neon_vst2_4_regs_vst3_vst4): Rename to...
	(cortex_a15_neon_vst2_4_regs_vst3): ...This, update for new attributes.
	(cortex_a15_neon_vst3_vst4): Rename to...
	(cortex_a15_neon_vst4): This, update for new attributes.
	(cortex_a15_neon_vld1_vld2_lane): Update for new attributes.
	(cortex_a15_neon_vld3_vld4_lane): Likewise.
	(cortex_a15_neon_vst1_vst2_lane): Likewise.
	(cortex_a15_neon_vst3_vst4_lane): Likewise.
	(cortex_a15_neon_vld3_vld4_all_lanes): Likewise.
	(cortex_a15_neon_ldm_2): Likewise.
	(cortex_a15_neon_stm_2): Likewise.
	(cortex_a15_neon_mcr): Likewise.
	(cortex_a15_neon_mcr_2_mcrr): Likewise.
	(cortex_a15_neon_mrc): Likewise.
	(cortex_a15_neon_mrrc): Likewise.

	(cortex_a15_neon_abd): New.
	(cortex_a15_neon_abd_q): Likewise.
	(cortex_a15_neon_aba): Likewise.
	(cortex_a15_neon_aba_q): Likewise.
	(cortex_a15_neon_acc): Likewise.
	(cortex_a15_neon_acc_q): Likewise.
	(cortex_a15_neon_arith_basic): Likewise.
	(cortex_a15_neon_arith_complex): Likewise.
	(cortex_a15_neon_multiply): Likewise.
	(cortex_a15_neon_multiply_q): Likewise.
	(cortex_a15_neon_mla): Likewise.
	(cortex_a15_neon_mla_q): Likewise.
	(cortex_a15_neon_sat_mla_long): Likewise.
	(cortex_a15_neon_shift_acc): Likewise.
	(cortex_a15_neon_shift_imm_basic): Likewise.
	(cortex_a15_neon_shift_imm_complex): Likewise.
	(cortex_a15_neon_shift_reg_basic): Likewise.
	(cortex_a15_neon_shift_reg_basic_q): Likewise.
	(cortex_a15_neon_shift_reg_complex): Likewise.
	(cortex_a15_neon_shift_reg_complex_q): Likewise.
	(cortex_a15_neon_fp_negabs): Likewise
	(cortex_a15_neon_fp_arith): Likewise
	(cortex_a15_neon_fp_arith_q): Likewise
	(cortex_a15_neon_fp_cvt_int): Likewise
	(cortex_a15_neon_fp_cvt_int_q): Likewise
	(cortex_a15_neon_fp_cvt_16): Likewise
	(cortex_a15_neon_fp_mul): Likewise
	(cortex_a15_neon_fp_mul_q): Likewise
	(cortex_a15_neon_fp_mla): Likewise
	(cortex_a15_neon_fp_mla_q): Likewise
	(cortex_a15_neon_fp_recps_rsqrte): Likewise.
	(cortex_a15_neon_fp_recps_rsqrte_q): Likewise.
	(cortex_a15_neon_bitops): Likewise.
	(cortex_a15_neon_bitops_q): Likewise.
	(cortex_a15_neon_from_gp): Likewise.
	(cortex_a15_neon_from_gp_q): Likewise.
	(cortex_a15_neon_tbl3_tbl4): Likewise.
	(cortex_a15_neon_zip_q): Likewise.
	(cortex_a15_neon_to_gp): Likewise.
	(cortex_a15_neon_load_a): Likewise.
	(cortex_a15_neon_load_b): Likewise.
	(cortex_a15_neon_load_c): Likewise.
	(cortex_a15_neon_load_d): Likewise.
	(cortex_a15_neon_load_e): Likewise.
	(cortex_a15_neon_load_f): Likewise.
	(cortex_a15_neon_store_a): Likewise.
	(cortex_a15_neon_store_b): Likewise.
	(cortex_a15_neon_store_c): Likewise.
	(cortex_a15_neon_store_d): Likewise.
	(cortex_a15_neon_store_e): Likewise.
	(cortex_a15_neon_store_f): Likewise.
	(cortex_a15_neon_store_g): Likewise.
	(cortex_a15_neon_store_h): Likewise.
	(cortex_a15_vfp_to_from_gp): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203617
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/cortex-a9-neon.md (cortex_a9_neon_type): New.

	(cortex_a9_neon_vshl_ddd): Remove.
	(cortex_a9_neon_vst3_vst4): Likewise.
	(cortex_a9_neon_vld3_vld4_all_lanes): Likewise.

	(cortex_a9_neon_bit_ops_q): New.

	(cortex_a9_neon_int_1): Use cortex_a8_neon_type.
	(cortex_a9_neon_int_2): Likewise.
	(cortex_a9_neon_int_3): Likewise.
	(cortex_a9_neon_int_4): Likewise.
	(cortex_a9_neon_int_5): Likewise.
	(cortex_a9_neon_vqneg_vqabs): Likewise.
	(cortex_a9_neon_vmov): Likewise.
	(cortex_a9_neon_vaba): Likewise.
	(cortex_a9_neon_vaba_qqq): Likewise.
	(cortex_a9_neon_shift_1): Likewise.
	(cortex_a9_neon_shift_2): Likewise.
	(cortex_a9_neon_shift_3): Likewise.
	(cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
	(cortex_a9_neon_vsra_vrsra): Likewise.
	(cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise.
	(cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
	Likewise.
	(cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a9_neon_mla_qqq_8_16): Likewise.
	(cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long):
	Likewise.
	(cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise.
	(cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
	(cortex_a9_neon_mul_qqd_32_scalar): Likewise.
	(cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
	(cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise.
	(cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise.
	(cortex_a9_neon_fp_vsum): Likewise.
	(cortex_a9_neon_fp_vmul_ddd): Likewise.
	(cortex_a9_neon_fp_vmul_qqd): Likewise.
	(cortex_a9_neon_fp_vmla_ddd): Likewise.
	(cortex_a9_neon_fp_vmla_qqq): Likewise.
	(cortex_a9_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a9_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise.
	(cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise.
	(cortex_a9_neon_bp_simple): Likewise.
	(cortex_a9_neon_bp_2cycle): Likewise.
	(cortex_a9_neon_bp_3cycle): Likewise.
	(cortex_a9_neon_ldr): Likewise.
	(cortex_a9_neon_str): Likewise.
	(cortex_a9_neon_vld1_1_2_regs): Likewise.
	(cortex_a9_neon_vld1_3_4_regs): Likewise.
	(cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
	(cortex_a9_neon_vld2_4_regs): Likewise.
	(cortex_a9_neon_vld3_vld4): Likewise.
	(cortex_a9_neon_vld1_vld2_lane): Likewise.
	(cortex_a9_neon_vld3_vld4_lane): Likewise.
	(cortex_a9_neon_vld3_vld4_all_lanes): Likewise.
	(cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
	(cortex_a9_neon_vst1_3_4_regs): Likewise.
	(cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise.
	(cortex_a9_neon_vst1_vst2_lane): Likewise.
	(cortex_a9_neon_vst3_vst4_lane): Likewise.
	(cortex_a9_neon_mcr): Likewise.
	(cortex_a9_neon_mcr_2_mcrr): Likewise.
	(cortex_a9_neon_mrc): Likewise.
	(cortex_a9_neon_mrrc): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203616
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/cortex-a8-neon.md (cortex_a8_neon_type): New.

	(cortex_a8_neon_vshl_ddd): Remove.
	(cortex_a8_neon_vst3_vst4): Likewise.
	(cortex_a8_neon_vld3_vld4_all_lanes): Likewise.

	(cortex_a8_neon_bit_ops_q): New.

	(cortex_a8_neon_int_1): Use cortex_a8_neon_type.
	(cortex_a8_neon_int_2): Likewise..
	(cortex_a8_neon_int_3): Likewise.
	(cortex_a8_neon_int_5): Likewise.
	(cortex_a8_neon_vqneg_vqabs): Likewise.
	(cortex_a8_neon_int_4): Likewise.
	(cortex_a8_neon_vaba): Likewise.
	(cortex_a8_neon_vaba_qqq): Likewise.
	(cortex_a8_neon_shift_1): Likewise.
	(cortex_a8_neon_shift_2): Likewise.
	(cortex_a8_neon_shift_3): Likewise.
	(cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
	(cortex_a8_neon_vsra_vrsra): Likewise.
	(cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise.
	(cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
	Likewise.
	(cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a8_neon_mla_qqq_8_16): Likewise.
	(cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long):
	Likewise.
	(cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise.
	(cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
	(cortex_a8_neon_mul_qqd_32_scalar): Likewise.
	(cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
	(cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise.
	(cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise.
	(cortex_a8_neon_fp_vsum): Likewise.
	(cortex_a8_neon_fp_vmul_ddd): Likewise.
	(cortex_a8_neon_fp_vmul_qqd): Likewise.
	(cortex_a8_neon_fp_vmla_ddd): Likewise.
	(cortex_a8_neon_fp_vmla_qqq): Likewise.
	(cortex_a8_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a8_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise.
	(cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise.
	(cortex_a8_neon_bp_simple): Likewise.
	(cortex_a8_neon_bp_2cycle): Likewise.
	(cortex_a8_neon_bp_3cycle): Likewise.
	(cortex_a8_neon_ldr): Likewise.
	(cortex_a8_neon_str): Likewise.
	(cortex_a8_neon_vld1_1_2_regs): Likewise.
	(cortex_a8_neon_vld1_3_4_regs): Likewise.
	(cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
	(cortex_a8_neon_vld2_4_regs): Likewise.
	(cortex_a8_neon_vld3_vld4): Likewise.
	(cortex_a8_neon_vld1_vld2_lane): Likewise.
	(cortex_a8_neon_vld3_vld4_lane): Likewise.
	(cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
	(cortex_a8_neon_vst1_3_4_regs): Likewise.
	(cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise.
	(cortex_a8_neon_vst1_vst2_lane): Likewise.
	(cortex_a8_neon_vst3_vst4_lane): Likewise.
	(cortex_a8_neon_mcr): Likewise.
	(cortex_a8_neon_mcr_2_mcrr): Likewise.
	(cortex_a8_neon_mrc): Likewise.
	(cortex_a8_neon_mrrc): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203614
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/iterators.md (Vetype): Add SF and DF modes.
	(fp): New.
	* config/aarch64/aarch64-simd.md (neon_type): Remove.
	(aarch64_simd_dup<mode>): Add "type" attribute.
	(aarch64_dup_lane<mode>): Likewise.
	(aarch64_dup_lane_<vswap_width_name><mode>): Likewise.
	(*aarch64_simd_mov<mode>): Likewise.
	(aarch64_simd_mov_from_<mode>low): Likewise.
	(aarch64_simd_mov_from_<mode>high): Likewise.
	(orn<mode>3): Likewise.
	(bic<mode>3): Likewise.
	(add<mode>3): Likewise.
	(sub<mode>3): Likewise.
	(mul<mode>3): Likewise.
	(*aarch64_mul3_elt<mode>): Likewise.
	(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
	(*aarch64_mul3_elt_to_128df): Likewise.
	(*aarch64_mul3_elt_to_64v2df): Likewise.
	(neg<mode>2): Likewise.
	(abs<mode>2): Likewise.
	(abd<mode>_3): Likewise.
	(aba<mode>_3): Likewise.
	(fabd<mode>_3): Likewise.
	(*fabd_scalar<mode>3): Likewise.
	(and<mode>3): Likewise.
	(ior<mode>3): Likewise.
	(xor<mode>3): Likewise.
	(one_cmpl<mode>2): Likewise.
	(aarch64_simd_vec_set<mode>): Likewise.
	(aarch64_simd_lshr<mode>): Likewise.
	(aarch64_simd_ashr<mode>): Likewise.
	(aarch64_simd_imm_shl<mode>): Likewise.
	(aarch64_simd_reg_sshl<mode): Likewise.
	(aarch64_simd_reg_shl<mode>_unsigned): Likewise.
	(aarch64_simd_reg_shl<mode>_signed): Likewise.
	(aarch64_simd_vec_setv2di): Likewise.
	(aarch64_simd_vec_set<mode>): Likewise.
	(aarch64_mla<mode>): Likewise.
	(*aarch64_mla_elt<mode>): Likewise.
	(*aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_mls<mode>): Likewise.
	(*aarch64_mls_elt<mode>): Likewise.
	(*aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
	(<su><maxmin><mode>3): Likewise.
	(move_lo_quad_<mode>): Likewise.
	(aarch64_simd_move_hi_quad_<mode>): Likewise.
	(aarch64_simd_vec_pack_trunc_<mode>): Likewise.
	(vec_pack_trunc_<mode>): Likewise.
	(aarch64_simd_vec_unpack<su>_lo_<mode>): Likewise.
	(aarch64_simd_vec_unpack<su>_hi_<mode>): Likewise.
	(*aarch64_<su>mlal_lo<mode>): Likewise.
	(*aarch64_<su>mlal_hi<mode>): Likewise.
	(*aarch64_<su>mlsl_lo<mode>): Likewise.
	(*aarch64_<su>mlsl_hi<mode>): Likewise.
	(*aarch64_<su>mlal<mode>): Likewise.
	(*aarch64_<su>mlsl<mode>): Likewise.
	(aarch64_simd_vec_<su>mult_lo_<mode>): Likewise.
	(aarch64_simd_vec_<su>mult_hi_<mode>): Likewise.
	(add<mode>3): Likewise.
	(sub<mode>3): Likewise.
	(mul<mode>3): Likewise.
	(div<mode>3): Likewise.
	(neg<mode>2): Likewise.
	(abs<mode>2): Likewise.
	(fma<mode>4): Likewise.
	(*aarch64_fma4_elt<mode>): Likewise.
	(*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
	(*aarch64_fma4_elt_to_128df): Likewise.
	(*aarch64_fma4_elt_to_64v2df): Likewise.
	(fnma<mode>4): Likewise.
	(*aarch64_fnma4_elt<mode>): Likewise.
	(*aarch64_fnma4_elt_<vswap_width_name><mode>
	(*aarch64_fnma4_elt_to_128df): Likewise.
	(*aarch64_fnma4_elt_to_64v2df): Likewise.
	(<frint_pattern><mode>2): Likewise.
	(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): Likewise.
	(<optab><fcvt_target><VDQF:VDQF:mode>2): Likewise.
	(vec_unpacks_lo_v4sf): Likewise.
	(aarch64_float_extend_lo_v2df): Likewise.
	(vec_unpacks_hi_v4sf): Likewise.
	(aarch64_float_truncate_lo_v2sf): Likewise.
	(aarch64_float_truncate_hi_v4sf): Likewise.
	(aarch64_vmls<mode>): Likewise.
	(<su><maxmin><mode>3): Likewise.
	(<maxmin_uns><mode>3): Likewise.
	(reduc_<sur>plus_<mode>): Likewise.
	(reduc_<sur>plus_v2di): Likewise.
	(reduc_<sur>plus_v2si): Likewise.
	(reduc_<sur>plus_<mode>): Likewise.
	(aarch64_addpv4sf): Likewise.
	(clz<mode>2): Likewise.
	(reduc_<maxmin_uns>_<mode>): Likewise.
	(reduc_<maxmin_uns>_v2di): Likewise.
	(reduc_<maxmin_uns>_v2si): Likewise.
	(reduc_<maxmin_uns>_<mode>): Likewise.
	(reduc_<maxmin_uns>_v4sf): Likewise.
	(aarch64_simd_bsl<mode>_internal): Likewise.
	(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
	(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
	(aarch64_get_lane<mode>): Likewise.
	(*aarch64_combinez<mode>): Likewise.
	(aarch64_combine<mode>): Likewise.
	(aarch64_simd_combine<mode>): Likewise.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_hi_internal): Likewise.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_lo_internal): Likewise.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>): Likewise.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>): Likewise.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal): Likewise.
	(aarch64_<sur>h<addsub><mode>): Likewise.
	(aarch64_<sur><addsub>hn<mode>): Likewise.
	(aarch64_<sur><addsub>hn2<mode>): Likewise.
	(aarch64_pmul<mode>): Likewise.
	(aarch64_<su_optab><optab><mode>): Likewise.
	(aarch64_<sur>qadd<mode>): Likewise.
	(aarch64_sqmovun<mode>): Likewise.
	(aarch64_<sur>qmovn<mode>): Likewise.
	(aarch64_s<optab><mode>): Likewise.
	(aarch64_sq<r>dmulh<mode>): Likewise.
	(aarch64_sq<r>dmulh_lane<mode>): Likewise.
	(aarch64_sq<r>dmulh_laneq<mode>): Likewise.
	(aarch64_sq<r>dmulh_lane<mode>): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l<mode>): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l_n<mode>): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2<mode>_internal): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
	(aarch64_sqdmull<mode>): Likewise.
	(aarch64_sqdmull_lane<mode>_internal): Likewise.
	(aarch64_sqdmull_n<mode>): Likewise.
	(aarch64_sqdmull2<mode>_internal): Likewise.
	(aarch64_sqdmull2_lane<mode>_internal): Likewise.
	(aarch64_sqdmull2_n<mode>_internal): Likewise.
	(aarch64_<sur>shl<mode>): Likewise.
	(aarch64_<sur>q<r>shl<mode>
	(aarch64_<sur>shll_n<mode>): Likewise.
	(aarch64_<sur>shll2_n<mode>): Likewise.
	(aarch64_<sur>shr_n<mode>): Likewise.
	(aarch64_<sur>sra_n<mode>): Likewise.
	(aarch64_<sur>s<lr>i_n<mode>): Likewise.
	(aarch64_<sur>qshl<u>_n<mode>): Likewise.
	(aarch64_<sur>q<r>shr<u>n_n<mode>): Likewise.
	(aarch64_cm<optab><mode>): Likewise.
	(aarch64_cm<optab>di): Likewise.
	(aarch64_cm<optab><mode>): Likewise.
	(aarch64_cm<optab>di): Likewise.
	(aarch64_cmtst<mode>): Likewise.
	(aarch64_cmtstdi): Likewise.
	(aarch64_cm<optab><mode>): Likewise.
	(*aarch64_fac<optab><mode>): Likewise.
	(aarch64_addp<mode>): Likewise.
	(aarch64_addpdi): Likewise.
	(sqrt<mode>2): Likewise.
	(vec_load_lanesoi<mode>): Likewise.
	(vec_store_lanesoi<mode>): Likewise.
	(vec_load_lanesci<mode>): Likewise.
	(vec_store_lanesci<mode>): Likewise.
	(vec_load_lanesxi<mode>): Likewise.
	(vec_store_lanesxi<mode>): Likewise.
	(*aarch64_mov<mode>): Likewise.
	(aarch64_ld2<mode>_dreg): Likewise.
	(aarch64_ld2<mode>_dreg): Likewise.
	(aarch64_ld3<mode>_dreg): Likewise.
	(aarch64_ld3<mode>_dreg): Likewise.
	(aarch64_ld4<mode>_dreg): Likewise.
	(aarch64_ld4<mode>_dreg): Likewise.
	(aarch64_tbl1<mode>): Likewise.
	(aarch64_tbl2v16qi): Likewise.
	(aarch64_combinev16qi): Likewise.
	(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): Likewise.
	(aarch64_st2<mode>_dreg): Likewise.
	(aarch64_st2<mode>_dreg): Likewise.
	(aarch64_st3<mode>_dreg): Likewise.
	(aarch64_st3<mode>_dreg): Likewise.
	(aarch64_st4<mode>_dreg): Likewise.
	(aarch64_st4<mode>_dreg): Likewise.
	(*aarch64_simd_ld1r<mode>): Likewise.
	(aarch64_frecpe<mode>): Likewise.
	(aarch64_frecp<FRECP:frecp_suffix><mode>): Likewise.
	(aarch64_frecps<mode>): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203613
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/iterators.md (V_elem_ch): New.
	(q): Likewise.
	(VQH_type): Likewise.
	* config/arm/arm.md (is_neon_type): New.
	(conds): Use is_neon_type.
	(anddi3_insn): Update type attribute.
	(xordi3_insn): Likewise.
	(one_cmpldi2): Likewise.
	* gcc/config/arm/vfp.md (movhf_vfp_neon): Update type attribute.
	* gcc/config/arm/neon.md (neon_mov): Update type attribute.
	(*movmisalign<mode>_neon_store): Likewise.
	(*movmisalign<mode>_neon_load): Likewise.
	(vec_set<mode>_internal): Likewise.
	(vec_set<mode>_internal): Likewise.
	(vec_setv2di_internal): Likewise.
	(vec_extract<mode>): Likewise.
	(vec_extract<mode>): Likewise.
	(vec_extractv2di): Likewise.
	(*add<mode>3_neon): Likewise.
	(adddi3_neon): Likewise.
	(*sub<mode>3_neon): Likewise.
	(subdi3_neon): Likewise.
	(fma<VCVTF:mode>4): Likewise.
	(fma<VCVTF:mode>4_intrinsic): Likewise.
	(*fmsub<VCVTF:mode>4): Likewise.
	(fmsub<VCVTF:mode>4_intrinsic): Likewise.
	(neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>): Likewise.
	(ior<mode>3): Likewise.
	(and<mode>3): Likewise.
	(orn<mode>3_neon): Likewise.
	(orndi3_neon): Likewise.
	(bic<mode>3_neon): Likewise.
	(bicdi3_neon): Likewise.
	(xor<mode>3): Likewise.
	(one_cmpl<mode>2): Likewise.
	(abs<mode>2): Likewise.
	(neg<mode>2): Likewise.
	(negdi2_neon): Likewise.
	(*umin<mode>3_neon): Likewise.
	(*umax<mode>3_neon): Likewise.
	(*smin<mode>3_neon): Likewise.
	(*smax<mode>3_neon): Likewise.
	(vashl<mode>3): Likewise.
	(vashr<mode>3_imm): Likewise.
	(vlshr<mode>3_imm): Likewise.
	(ashl<mode>3_signed): Likewise.
	(ashl<mode>3_unsigned): Likewise.
	(neon_load_count): Likewise.
	(ashldi3_neon_noclobber): Likewise.
	(ashldi3_neon): Likewise.
	(signed_shift_di3_neon): Likewise.
	(unsigned_shift_di3_neon): Likewise.
	(ashrdi3_neon_imm_noclobber): Likewise.
	(lshrdi3_neon_imm_noclobber): Likewise.
	(<shift>di3_neon): Likewise.
	(widen_ssum<mode>3): Likewise.
	(widen_usum<mode>3): Likewise.
	(quad_halves_<code>v4si): Likewise.
	(quad_halves_<code>v4sf): Likewise.
	(quad_halves_<code>v8hi): Likewise.
	(quad_halves_<code>v16qi): Likewise.
	(reduc_splus_v2di): Likewise.
	(neon_vpadd_internal<mode>): Likewise.
	(neon_vpsmin<mode>): Likewise.
	(neon_vpsmax<mode>): Likewise.
	(neon_vpumin<mode>): Likewise.
	(neon_vpumax<mode>): Likewise.
	(*ss_add<mode>_neon): Likewise.
	(*us_add<mode>_neon): Likewise.
	(*ss_sub<mode>_neon): Likewise.
	(*us_sub<mode>_neon): Likewise.
	(neon_vadd<mode>_unspec): Likewise.
	(neon_vaddl<mode>): Likewise.
	(neon_vaddw<mode>): Likewise.
	(neon_vhadd<mode>): Likewise.
	(neon_vqadd<mode>): Likewise.
	(neon_vaddhn<mode>): Likewise.
	(neon_vmul<mode>): Likewise.
	(neon_vfms<VCVTF:mode>): Likewise.
	(neon_vmlal<mode>): Likewise.
	(neon_vmls<mode>): Likewise.
	(neon_vmlsl<mode>): Likewise.
	(neon_vqdmulh<mode>): Likewise.
	(neon_vqdmlal<mode>): Likewise.
	(neon_vqdmlsl<mode>): Likewise.
	(neon_vmull<mode>): Likewise.
	(neon_vqdmull<mode>): Likewise.
	(neon_vsub<mode>_unspec): Likewise.
	(neon_vsubl<mode>): Likewise.
	(neon_vsubw<mode>): Likewise.
	(neon_vqsub<mode>): Likewise.
	(neon_vhsub<mode>): Likewise.
	(neon_vsubhn<mode>): Likewise.
	(neon_vceq<mode>): Likewise.
	(neon_vcge<mode>): Likewise.
	(neon_vcgeu<mode>): Likewise.
	(neon_vcgt<mode>): Likewise.
	(neon_vcgtu<mode>): Likewise.
	(neon_vcle<mode>): Likewise.
	(neon_vclt<mode>): Likewise.
	(neon_vcage<mode>): Likewise.
	(neon_vcagt<mode>): Likewise.
	(neon_vtst<mode>): Likewise.
	(neon_vabd<mode>): Likewise.
	(neon_vabdl<mode>): Likewise.
	(neon_vaba<mode>): Likewise.
	(neon_vabal<mode>): Likewise.
	(neon_vmax<mode>): Likewise.
	(neon_vmin<mode>): Likewise.
	(neon_vpaddl<mode>): Likewise.
	(neon_vpadal<mode>): Likewise.
	(neon_vpmax<mode>): Likewise.
	(neon_vpmin<mode>): Likewise.
	(neon_vrecps<mode>): Likewise.
	(neon_vrsqrts<mode>): Likewise.
	(neon_vqabs<mode>): Likewise.
	(neon_vqneg<mode>): Likewise.
	(neon_vcls<mode>): Likewise.
	(clz<mode>2): Likewise.
	(popcount<mode>2): Likewise.
	(neon_vrecpe<mode>): Likewise.
	(neon_vrsqrte<mode>): Likewise.
	(neon_vget_lane<mode>_sext_internal): Likewise.
	(neon_vget_lane<mode>_zext_internal): Likewise.
	(neon_vdup_n<mode>): Likewise.
	(neon_vdup_n<mode>): Likewise.
	(neon_vdup_nv2di): Likewise.
	(neon_vdup_lane<mode>_interal): Likewise.
	(*neon_vswp<mode>): Likewise.
	(neon_vcombine<mode>): Likewise.
	(float<mode><V_cvtto>2): Likewise.
	(floatuns<mode><V_cvtto>2): Likewise.
	(fix_trunc<mode><V_cvtto>2): Likewise.
	(fixuns_trunc<mode><V_cvtto>2
	(neon_vcvt<mode>): Likewise.
	(neon_vcvt<mode>): Likewise.
	(neon_vcvtv4sfv4hf): Likewise.
	(neon_vcvtv4hfv4sf): Likewise.
	(neon_vcvt_n<mode>): Likewise.
	(neon_vcvt_n<mode>): Likewise.
	(neon_vmovn<mode>): Likewise.
	(neon_vqmovn<mode>): Likewise.
	(neon_vqmovun<mode>): Likewise.
	(neon_vmovl<mode>): Likewise.
	(neon_vmul_lane<mode>): Likewise.
	(neon_vmul_lane<mode>): Likewise.
	(neon_vmull_lane<mode>): Likewise.
	(neon_vqdmull_lane<mode>): Likewise.
	(neon_vqdmulh_lane<mode>): Likewise.
	(neon_vqdmulh_lane<mode>): Likewise.
	(neon_vmla_lane<mode>): Likewise.
	(neon_vmla_lane<mode>): Likewise.
	(neon_vmlal_lane<mode>): Likewise.
	(neon_vqdmlal_lane<mode>): Likewise.
	(neon_vmls_lane<mode>): Likewise.
	(neon_vmls_lane<mode>): Likewise.
	(neon_vmlsl_lane<mode>): Likewise.
	(neon_vqdmlsl_lane<mode>): Likewise.
	(neon_vext<mode>): Likewise.
	(neon_vrev64<mode>): Likewise.
	(neon_vrev32<mode>): Likewise.
	(neon_vrev16<mode>): Likewise.
	(neon_vbsl<mode>_internal): Likewise.
	(neon_vshl<mode>): Likewise.
	(neon_vqshl<mode>): Likewise.
	(neon_vshr_n<mode>): Likewise.
	(neon_vshrn_n<mode>): Likewise.
	(neon_vqshrn_n<mode>): Likewise.
	(neon_vqshrun_n<mode>): Likewise.
	(neon_vshl_n<mode>): Likewise.
	(neon_vqshl_n<mode>): Likewise.
	(neon_vqshlu_n<mode>): Likewise.
	(neon_vshll_n<mode>): Likewise.
	(neon_vsra_n<mode>): Likewise.
	(neon_vsri_n<mode>): Likewise.
	(neon_vsli_n<mode>): Likewise.
	(neon_vtbl1v8qi): Likewise.
	(neon_vtbl2v8qi): Likewise.
	(neon_vtbl3v8qi): Likewise.
	(neon_vtbl4v8qi): Likewise.
	(neon_vtbl1v16qi): Likewise.
	(neon_vtbl2v16qi): Likewise.
	(neon_vcombinev16qi): Likewise.
	(neon_vtbx1v8qi): Likewise.
	(neon_vtbx2v8qi): Likewise.
	(neon_vtbx3v8qi): Likewise.
	(neon_vtbx4v8qi): Likewise.
	(*neon_vtrn<mode>_insn): Likewise.
	(*neon_vzip<mode>_insn): Likewise.
	(*neon_vuzp<mode>_insn): Likewise.
	(neon_vld1<mode>): Likewise.
	(neon_vld1_lane<mode>): Likewise.
	(neon_vld1_lane<mode>): Likewise.
	(neon_vld1_dup<mode>): Likewise.
	(neon_vld1_dup<mode>): Likewise.
	(neon_vld1_dupv2di): Likewise.
	(neon_vst1<mode>): Likewise.
	(neon_vst1_lane<mode>): Likewise.
	(neon_vst1_lane<mode>): Likewise.
	(neon_vld2<mode>): Likewise.
	(neon_vld2<mode>): Likewise.
	(neon_vld2_lane<mode>): Likewise.
	(neon_vld2_lane<mode>): Likewise.
	(neon_vld2_dup<mode>): Likewise.
	(neon_vst2<mode>): Likewise.
	(neon_vst2<mode>): Likewise.
	(neon_vst2_lane<mode>): Likewise.
	(neon_vst2_lane<mode>): Likewise.
	(neon_vld3<mode>): Likewise.
	(neon_vld3qa<mode>): Likewise.
	(neon_vld3qb<mode>): Likewise.
	(neon_vld3_lane<mode>): Likewise.
	(neon_vld3_lane<mode>): Likewise.
	(neon_vld3_dup<mode>): Likewise.
	(neon_vst3<mode>): Likewise.
	(neon_vst3qa<mode>): Likewise.
	(neon_vst3qb<mode>): Likewise.
	(neon_vst3_lane<mode>): Likewise.
	(neon_vst3_lane<mode>): Likewise.
	(neon_vld4<mode>): Likewise.
	(neon_vld4qa<mode>): Likewise.
	(neon_vld4qb<mode>): Likewise.
	(neon_vld4_lane<mode>): Likewise.
	(neon_vld4_lane<mode>): Likewise.
	(neon_vld4_dup<mode>): Likewise.
	(neon_vst4<mode>): Likewise.
	(neon_vst4qa<mode>): Likewise.
	(neon_vst4qb<mode>): Likewise.
	(neon_vst4_lane<mode>): Likewise.
	(neon_vst4_lane<mode>): Likewise.
	(neon_vec_unpack<US>_lo_<mode>): Likewise.
	(neon_vec_unpack<US>_hi_<mode>): Likewise.
	(neon_vec_<US>mult_lo_<mode>): Likewise.
	(neon_vec_<US>mult_hi_<mode>): Likewise.
	(neon_vec_<US>shiftl_<mode>): Likewise.
	(neon_unpack<US>_<mode>): Likewise.
	(neon_vec_<US>mult_<mode>): Likewise.
	(vec_pack_trunc_<mode>): Likewise.
	(neon_vec_pack_trunc_<mode>): Likewise.
	(neon_vabd<mode>_2): Likewise.
	(neon_vabd<mode>_3): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203612
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md (movtf_aarch64): Update type attribute.
	(load_pair): Update type attribute.
	(store_pair): Update type attribute.
	* config/aarch64/iterators.md (q): New.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203611
	2013-10-15  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md: Add new types for Neon insns.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r203241
	2013-10-07  Renlin Li  <Renlin.Li@arm.com>

	* config/arm/arm-cores.def (cortex-a53): Use cortex tuning.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202560
	2013-09-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_cmpsi_insn): Split rI alternative.
	Set type attribute correctly. Set predicable_short_it attribute.
	(cmpsi_shiftsi): Remove %? from output template.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202448
	2013-09-10  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md (generic_sched): New.
	* config/aarch64/aarch64-generic.md (load): Make conditional
	on generic_sched attribute.
	(nonload): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202334
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(*movtf_aarch64): Use neon_<ls>dm_2 as type where v8type
	is fpsimd_<load/store>2.
	(load_pair<mode>): Likewise.
	(store_pair<mode>): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202333
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md (type): Add "mrs" type.
	* config/aarch64/aarch64.md
	(aarch64_load_tp_hard): Make type "mrs".
	* config/arm/arm.md
	(load_tp_hard): Make type "mrs".
	* config/arm/cortex-a15.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4.md: Update with new attributes.
	* config/arm/cortex-r4.md: Update with new attributes.
	* config/arm/fa526.md: Update with new attributes.
	* config/arm/fa606te.md: Update with new attributes.
	* config/arm/fa626te.md: Update with new attributes.
	* config/arm/fa726te.md: Update with new attributes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202332
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(*movti_aarch64): Use "multiple" for type where v8type is "move2".
	(*movtf_aarch64): Likewise.
	* config/arm/arm.md
	(thumb1_movdi_insn): Use "multiple" for type where more than one
	instruction is used for a move.
	(*arm32_movhf): Likewise.
	(*thumb_movdf_insn): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202331
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md (type): Rename fcpys to fmov.
	* config/arm/vfp.md
	(*arm_movsi_vfp): Rename type fcpys as fmov.
	(*thumb2_movsi_vfp): Likewise
	(*movhf_vfp_neon): Likewise
	(*movhf_vfp): Likewise
	(*movsf_vfp): Likewise
	(*thumb2_movsf_vfp): Likewise
	(*movsfcc_vfp): Likewise
	(*thumb2_movsfcc_vfp): Likewise
	* config/aarch64/aarch64-simd.md
	(move_lo_quad_<mode>): Replace type mov_reg with fmovs.
	* config/aarch64/aarch64.md
	(*movsi_aarch64): Replace type mov_reg with fmovs.
	(*movdi_aarch64): Likewise
	(*movsf_aarch64): Likewise
	(*movdf_aarch64): Likewise
	* config/arm/arm.c
	(cortexa7_older_only): Rename TYPE_FCPYS to TYPE_FMOV.
	* config/arm/iwmmxt.md
	(*iwmmxt_movsi_insn): Rename type fcpys as fmov.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202330
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(*madd<mode>): Fix type attribute.
	(*maddsi_uxtw): Likewise.
	(*msub<mode>): Likewise.
	(*msubsi_uxtw): Likewise.
	(<su_optab>maddsidi4): Likewise.
	(<su_optab>msubsidi4): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202329
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>.
	* config/arm/arm.md (core_cycles): Remove fdiv.
	* config/arm/vfp.md:
	(*sqrtsf2_vfp): Update for attribute changes.
	(*sqrtdf2_vfp): Likewise.
	* config/aarch64/aarch64.md:
	(sqrt<mode>2): Update for attribute changes.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202328
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md
	(type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f.
	* config/aarch64/aarch64.md
	(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Update with
	new attributes.
	(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
	(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
	(float<GPI:mode><GPF:mode>2): Likewise.
	* config/arm/vfp.md
	(*truncsisf2_vfp): Update with new attributes.
	(*truncsidf2_vfp): Likewise.
	(fixuns_truncsfsi2): Likewise.
	(fixuns_truncdfsi2): Likewise.
	(*floatsisf2_vfp): Likewise.
	(*floatsidf2_vfp): Likewise.
	(floatunssisf2): Likewise.
	(floatunssidf2): Likewise.
	(*combine_vcvt_f32_<FCVTI32typename>): Likewise.
	(*combine_vcvt_f64_<FCVTI32typename>): Likewise.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202323
	2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
	types.
	* config/arm/arm-fixed.md: Add type attribute to all insn
	patterns.
	(add<mode>3): Add type attribute.
	(add<mode>3): Likewise.
	(usadd<mode>3): Likewise.
	(ssadd<mode>3): Likewise.
	(sub<mode>3): Likewise.
	(sub<mode>3): Likewise.
	(ussub<mode>3): Likewise.
	(sssub<mode>3): Likewise.
	(ssmulsa3): Likewise.
	(usmulusa3): Likewise.
	(arm_usatsihi): Likewise.
	* config/arm/vfp.md
	(*movdi_vfp): Add types for all instructions.
	(*movdi_vfp_cortexa8): Likewise.
	(*movhf_vfp_neon): Likewise.
	(*movhf_vfp): Likewise.
	(*movdf_vfp): Likewise.
	(*thumb2_movdf_vfp): Likewise.
	(*thumb2_movdfcc_vfp): Likewise.
	* config/arm/arm.md: Add type attribute to all insn patterns.
	(*thumb1_adddi3): Add type attribute.
	(*arm_adddi3): Likewise.
	(*adddi_sesidi_di): Likewise.
	(*adddi_zesidi_di): Likewise.
	(*thumb1_addsi3): Likewise.
	(addsi3_compare0): Likewise.
	(*addsi3_compare0_scratch): Likewise.
	(*compare_negsi_si): Likewise.
	(cmpsi2_addneg): Likewise.
	(*addsi3_carryin_<optab>): Likewise.
	(*addsi3_carryin_alt2_<optab>): Likewise.
	(*addsi3_carryin_clobercc_<optab>): Likewise.
	(*subsi3_carryin): Likewise.
	(*subsi3_carryin_const): Likewise.
	(*subsi3_carryin_compare): Likewise.
	(*subsi3_carryin_compare_const): Likewise.
	(*arm_subdi3): Likewise.
	(*thumb_subdi3): Likewise.
	(*subdi_di_zesidi): Likewise.
	(*subdi_di_sesidi): Likewise.
	(*subdi_zesidi_di): Likewise.
	(*subdi_sesidi_di): Likewise.
	(*subdi_zesidi_ze): Likewise.
	(thumb1_subsi3_insn): Likewise.
	(*arm_subsi3_insn): Likewise.
	(*anddi3_insn): Likewise.
	(*anddi_zesidi_di): Likewise.
	(*anddi_sesdi_di): Likewise.
	(*ne_zeroextracts): Likewise.
	(*ne_zeroextracts): Likewise.
	(*ite_ne_zeroextr): Likewise.
	(*ite_ne_zeroextr): Likewise.
	(*anddi_notdi_di): Likewise.
	(*anddi_notzesidi): Likewise.
	(*anddi_notsesidi): Likewise.
	(andsi_notsi_si): Likewise.
	(thumb1_bicsi3): Likewise.
	(*iordi3_insn): Likewise.
	(*iordi_zesidi_di): Likewise.
	(*iordi_sesidi_di): Likewise.
	(*thumb1_iorsi3_insn): Likewise.
	(*xordi3_insn): Likewise.
	(*xordi_zesidi_di): Likewise.
	(*xordi_sesidi_di): Likewise.
	(*arm_xorsi3): Likewise.
	(*andsi_iorsi3_no): Likewise.
	(*smax_0): Likewise.
	(*smax_m1): Likewise.
	(*arm_smax_insn): Likewise.
	(*smin_0): Likewise.
	(*arm_smin_insn): Likewise.
	(*arm_umaxsi3): Likewise.
	(*arm_uminsi3): Likewise.
	(*minmax_arithsi): Likewise.
	(*minmax_arithsi_): Likewise.
	(*satsi_<SAT:code>): Likewise.
	(arm_ashldi3_1bit): Likewise.
	(arm_ashrdi3_1bit): Likewise.
	(arm_lshrdi3_1bit): Likewise.
	(*arm_negdi2): Likewise.
	(*thumb1_negdi2): Likewise.
	(*arm_negsi2): Likewise.
	(*thumb1_negsi2): Likewise.
	(*negdi_extendsid): Likewise.
	(*negdi_zero_extend): Likewise.
	(*arm_abssi2): Likewise.
	(*thumb1_abssi2): Likewise.
	(*arm_neg_abssi2): Likewise.
	(*thumb1_neg_abss): Likewise.
	(one_cmpldi2): Likewise.
	(extend<mode>di2): Likewise.
	(*compareqi_eq0): Likewise.
	(*arm_extendhisi2addsi): Likewise.
	(*arm_movdi): Likewise.
	(*thumb1_movdi_insn): Likewise.
	(*arm_movt): Likewise.
	(*thumb1_movsi_insn): Likewise.
	(pic_add_dot_plus_four): Likewise.
	(pic_add_dot_plus_eight): Likewise.
	(tls_load_dot_plus_eight): Likewise.
	(*thumb1_movhi_insn): Likewise.
	(*thumb1_movsf_insn): Likewise.
	(*movdf_soft_insn): Likewise.
	(*thumb_movdf_insn): Likewise.
	(cbranchsi4_insn): Likewise.
	(cbranchsi4_scratch): Likewise.
	(*negated_cbranchsi4): Likewise.
	(*tbit_cbranch): Likewise.
	(*tlobits_cbranch): Likewise.
	(*tstsi3_cbranch): Likewise.
	(*cbranchne_decr1): Likewise.
	(*addsi3_cbranch): Likewise.
	(*addsi3_cbranch_scratch): Likewise.
	(*arm_cmpdi_insn): Likewise.
	(*arm_cmpdi_unsig): Likewise.
	(*arm_cmpdi_zero): Likewise.
	(*thumb_cmpdi_zero): Likewise.
	(*deleted_compare): Likewise.
	(*mov_scc): Likewise.
	(*mov_negscc): Likewise.
	(*mov_notscc): Likewise.
	(*cstoresi_eq0_thumb1_insn): Likewise.
	(cstoresi_nltu_thumb1): Likewise.
	(cstoresi_ltu_thu): Likewise.
	(thumb1_addsi3_addgeu): Likewise.
	(*arm_jump): Likewise.
	(*thumb_jump): Likewise.
	(*check_arch2): Likewise.
	(arm_casesi_internal): Likewise.
	(thumb1_casesi_dispatch): Likewise.
	(*arm_indirect_jump): Likewise.
	(*thumb1_indirect_jump): Likewise.
	(nop): Likewise.
	(*and_scc): Likewise.
	(*ior_scc): Likewise.
	(*compare_scc): Likewise.
	(*cond_move): Likewise.
	(*cond_arith): Likewise.
	(*cond_sub): Likewise.
	(*cmp_ite0): Likewise.
	(*cmp_ite1): Likewise.
	(*cmp_and): Likewise.
	(*cmp_ior): Likewise.
	(*ior_scc_scc): Likewise.
	(*ior_scc_scc_cmp): Likewise.
	(*and_scc_scc): Likewise.
	(*and_scc_scc_cmp): Likewise.
	(*and_scc_scc_nod): Likewise.
	(*negscc): Likewise.
	(movcond_addsi): Likewise.
	(movcond): Likewise.
	(*ifcompare_plus_move): Likewise.
	(*if_plus_move): Likewise.
	(*ifcompare_move_plus): Likewise.
	(*if_move_plus): Likewise.
	(*ifcompare_arith_arith): Likewise.
	(*if_arith_arith): Likewise.
	(*ifcompare_arith_move): Likewise.
	(*if_arith_move): Likewise.
	(*ifcompare_move_arith): Likewise.
	(*if_move_arith): Likewise.
	(*ifcompare_move_not): Likewise.
	(*if_move_not): Likewise.
	(*ifcompare_not_move): Likewise.
	(*if_not_move): Likewise.
	(*ifcompare_shift_move): Likewise.
	(*if_shift_move): Likewise.
	(*ifcompare_move_shift): Likewise.
	(*if_move_shift): Likewise.
	(*ifcompare_shift_shift): Likewise.
	(*ifcompare_not_arith): Likewise.
	(*ifcompare_arith_not): Likewise.
	(*if_arith_not): Likewise.
	(*ifcompare_neg_move): Likewise.
	(*if_neg_move): Likewise.
	(*ifcompare_move_neg): Likewise.
	(*if_move_neg): Likewise.
	(prologue_thumb1_interwork): Likewise.
	(*cond_move_not): Likewise.
	(*sign_extract_onebit): Likewise.
	(*not_signextract_onebit): Likewise.
	(stack_tie): Likewise.
	(align_4): Likewise.
	(align_8): Likewise.
	(consttable_end): Likewise.
	(consttable_1): Likewise.
	(consttable_2): Likewise.
	(consttable_4): Likewise.
	(consttable_8): Likewise.
	(consttable_16): Likewise.
	(*thumb1_tablejump): Likewise.
	(prefetch): Likewise.
	(force_register_use): Likewise.
	(thumb_eh_return): Likewise.
	(load_tp_hard): Likewise.
	(load_tp_soft): Likewise.
	(tlscall): Likewise.
	(*arm_movtas_ze): Likewise.
	(*arm_rev): Likewise.
	(*arm_revsh): Likewise.
	(*arm_rev16): Likewise.
	* config/arm/thumb2.md
	(*thumb2_smaxsi3): Likewise.
	(*thumb2_sminsi3): Likewise.
	(*thumb32_umaxsi3): Likewise.
	(*thumb2_uminsi3): Likewise.
	(*thumb2_negdi2): Likewise.
	(*thumb2_abssi2): Likewise.
	(*thumb2_neg_abss): Likewise.
	(*thumb2_movsi_insn): Likewise.
	(tls_load_dot_plus_four): Likewise.
	(*thumb2_movhi_insn): Likewise.
	(*thumb2_mov_scc): Likewise.
	(*thumb2_mov_negs): Likewise.
	(*thumb2_mov_negs): Likewise.
	(*thumb2_mov_nots): Likewise.
	(*thumb2_mov_nots): Likewise.
	(*thumb2_movsicc_): Likewise.
	(*thumb2_movsfcc_soft_insn): Likewise.
	(*thumb2_indirect_jump): Likewise.
	(*thumb2_and_scc): Likewise.
	(*thumb2_ior_scc): Likewise.
	(*thumb2_ior_scc_strict_it): Likewise.
	(*thumb2_cond_move): Likewise.
	(*thumb2_cond_arith): Likewise.
	(*thumb2_cond_ari): Likewise.
	(*thumb2_cond_sub): Likewise.
	(*thumb2_negscc): Likewise.
	(*thumb2_movcond): Likewise.
	(thumb2_casesi_internal): Likewise.
	(thumb2_casesi_internal_pic): Likewise.
	(*thumb2_alusi3_short): Likewise.
	(*thumb2_mov<mode>_shortim): Likewise.
	(*thumb2_addsi_short): Likewise.
	(*thumb2_subsi_short): Likewise.
	(thumb2_addsi3_compare0): Likewise.
	(*thumb2_cbz): Likewise.
	(*thumb2_cbnz): Likewise.
	(*thumb2_one_cmplsi2_short): Likewise.
	(*thumb2_negsi2_short): Likewise.
	(*orsi_notsi_si): Likewise.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/arm1026ejs.md: Update with new attributes.
	* config/arm/arm1136jfs.md: Update with new attributes.
	* config/arm/arm926ejs.md: Update with new attributes.
	* config/arm/cortex-a15.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4.md: Update with new attributes.
	* config/arm/cortex-r4.md: Update with new attributes.
	* config/arm/fa526.md: Update with new attributes.
	* config/arm/fa606te.md: Update with new attributes.
	* config/arm/fa626te.md: Update with new attributes.
	* config/arm/fa726te.md: Update with new attributes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202292
	2013-09-05  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(type): Remove frecpe, frecps, frecpx.
	(aarch64_frecp<FRECP:frecp_suffix><mode>): Move to aarch64-simd.md,
	fix to be a TARGET_SIMD instruction.
	(aarch64_frecps): Remove.
	* config/aarch64/aarch64-simd.md
	(aarch64_frecp<FRECP:frecp_suffix><mode>): New, moved from aarch64.md
	(aarch64_frecps<mode>): Handle all float/vector of float modes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202291
	2013-09-05  James Greenhalgh  <james.greenhalgh@arm.com>
	Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/types.md (define_attr "type"):
	Expand "arlo_imm"
	into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
	Expand "arlo_reg"
	into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
	"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
	"logics_reg", "rev".
	Expand "arlo_shift"
	into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
	"logics_shift_imm".
	Expand "arlo_shift_reg"
	into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
	"logics_shift_reg".
	Expand "clz" into "clz, "rbit".
	Rename "shift" to "shift_imm".
	* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
	changes.
	Update for attribute changes all occurrences of arlo_* and
	shift* types.
	* config/arm/arm-fixed.md: Update for attribute changes
	all occurrences of arlo_* types.
	* config/arm/thumb2.md: Update for attribute changes all occurrences
	of arlo_* types.
	* config/arm/arm.c (xscale_sched_adjust_cost):  (rtx insn, rtx
	(cortexa7_older_only): Likewise.
	(cortexa7_younger):  Likewise.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for
	attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for
	attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for
	attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md
	(cortex_a53_alu): Update for attribute changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md
	(cortex_a7_alu_imm): Update for attribute changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md
	(cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	* config/arm/cortex-a9.md
	(cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md
	(cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md
	(cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md
	(526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md
	(606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md
	(626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md
	(726te_alu_op): Update for attribute changes.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/aarch64/aarch64.md: Update for attribute change
	all occurrences of arlo_* and shift* types.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202272
	2013-08-02  James Greenhalgh  <james.greenhalgh@arm.com>
	Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64.md
	(*movti_aarch64): Rename r_2_f and f_2_r.
	(*movsf_aarch64): Likewise.
	(*movdf_aarch64): Likewise.
	(*movtf_aarch64): Likewise.
	(aarch64_movdi_<mode>low): Likewise.
	(aarch64_movdi_<mode>high): Likewise.
	(aarch64_mov<mode>high_di): Likewise.
	(aarch64_mov<mode>low_di): Likewise.
	(aarch64_movtilow_tilow): Likewise.
	* config/arm/arm.md (attribute "neon_type"): Delete.  Move attribute
	values to config/arm/types.md
	(attribute "conds"): Update for attribute change.
	(anddi3_insn): Likewise.
	(iordi3_insn): Likewise.
	(xordi3_insn): Likewise.
	(one_cmpldi2): Likewise.
	* config/arm/types.md (type): Add Neon types.
	* config/arm/neon.md (neon_mov<mode>): Remove "neon_type" attribute,
	use "type" attribute.
	(movmisalign<mode>_neon_store): Likewise.
	(movmisalign<mode>_neon_load): Likewise.
	(vec_set<mode>_internal): Likewise.
	(vec_setv2di_internal): Likewise.
	(vec_extract<mode>): Likewise.
	(vec_extractv2di): Likewise.
	(add<mode>3_neon): Likewise.
	(adddi3_neon): Likewise.
	(sub<mode>3_neon): Likewise.
	(subdi3_neon): Likewise.
	(mul<mode>3_neon): Likewise.
	(mul<mode>3add<mode>_neon): Likewise.
	(mul<mode>3neg<mode>add<mode>_neon): Likewise.
	(fma<VCVTF:mode>4)): Likewise.
	(fma<VCVTF:mode>4_intrinsic): Likewise.
	(fmsub<VCVTF:mode>4)): Likewise.
	(fmsub<VCVTF:mode>4_intrinsic): Likewise.
	(neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>): Likewise.
	(ior<mode>3): Likewise.
	(and<mode>3): Likewise.
	(anddi3_neon): Likewise.
	(orn<mode>3_neon): Likewise.
	(orndi3_neon): Likewise.
	(bic<mode>3_neon): Likewise.
	(bicdi3_neon): Likewise.
	(xor<mode>3): Likewise.
	(one_cmpl<mode>2): Likewise.
	(abs<mode>2): Likewise.
	(neg<mode>2): Likewise.
	(umin<mode>3_neon): Likewise.
	(umax<mode>3_neon): Likewise.
	(smin<mode>3_neon): Likewise.
	(smax<mode>3_neon): Likewise.
	(vashl<mode>3): Likewise.
	(vashr<mode>3_imm): Likewise.
	(vlshr<mode>3_imm): Likewise.
	(ashl<mode>3_signed): Likewise.
	(ashl<mode>3_unsigned): Likewise.
	(neon_load_count): Likewise.
	(ashldi3_neon_noclobber): Likewise.
	(signed_shift_di3_neon): Likewise.
	(unsigned_shift_di3_neon): Likewise.
	(ashrdi3_neon_imm_noclobber): Likewise.
	(lshrdi3_neon_imm_noclobber): Likewise.
	(widen_ssum<mode>3): Likewise.
	(widen_usum<mode>3): Likewise.
	(quad_halves_<code>v4si): Likewise.
	(quad_halves_<code>v4sf): Likewise.
	(quad_halves_<code>v8hi): Likewise.
	(quad_halves_<code>v16qi): Likewise.
	(reduc_splus_v2di): Likewise.
	(neon_vpadd_internal<mode>): Likewise.
	(neon_vpsmin<mode>): Likewise.
	(neon_vpsmax<mode>): Likewise.
	(neon_vpumin<mode>): Likewise.
	(neon_vpumax<mode>): Likewise.
	(ss_add<mode>_neon): Likewise.
	(us_add<mode>_neon): Likewise.
	(ss_sub<mode>_neon): Likewise.
	(us_sub<mode>_neon): Likewise.
	(neon_vadd<mode>_unspec): Likewise.
	(neon_vaddl<mode>): Likewise.
	(neon_vaddw<mode>): Likewise.
	(neon_vhadd<mode>): Likewise.
	(neon_vqadd<mode>): Likewise.
	(neon_vaddhn<mode>): Likewise.
	(neon_vmul<mode>): Likewise.
	(neon_vmla<mode>): Likewise.
	(neon_vmlal<mode>): Likewise.
	(neon_vmls<mode>): Likewise.
	(neon_vmlsl<mode>): Likewise.
	(neon_vqdmulh<mode>): Likewise.
	(neon_vqdmlal<mode>): Likewise.
	(neon_vqdmlsl<mode>): Likewise.
	(neon_vmull<mode>): Likewise.
	(neon_vqdmull<mode>): Likewise.
	(neon_vsub<mode>_unspec): Likewise.
	(neon_vsubl<mode>): Likewise.
	(neon_vsubw<mode>): Likewise.
	(neon_vqsub<mode>): Likewise.
	(neon_vhsub<mode>): Likewise.
	(neon_vsubhn<mode>): Likewise.
	(neon_vceq<mode>): Likewise.
	(neon_vcge<mode>): Likewise.
	(neon_vcgeu<mode>): Likewise.
	(neon_vcgt<mode>): Likewise.
	(neon_vcgtu<mode>): Likewise.
	(neon_vcle<mode>): Likewise.
	(neon_vclt<mode>): Likewise.
	(neon_vcage<mode>): Likewise.
	(neon_vcagt<mode>): Likewise.
	(neon_vtst<mode>): Likewise.
	(neon_vabd<mode>): Likewise.
	(neon_vabdl<mode>): Likewise.
	(neon_vaba<mode>): Likewise.
	(neon_vabal<mode>): Likewise.
	(neon_vmax<mode>): Likewise.
	(neon_vmin<mode>): Likewise.
	(neon_vpaddl<mode>): Likewise.
	(neon_vpadal<mode>): Likewise.
	(neon_vpmax<mode>): Likewise.
	(neon_vpmin<mode>): Likewise.
	(neon_vrecps<mode>): Likewise.
	(neon_vrsqrts<mode>): Likewise.
	(neon_vqabs<mode>): Likewise.
	(neon_vqneg<mode>): Likewise.
	(neon_vcls<mode>): Likewise.
	(clz<mode>2): Likewise.
	(popcount<mode>2): Likewise.
	(neon_vrecpe): Likewise.
	(neon_vrsqrte): Likewise.
	(neon_vget_lane<mode>_sext_internal): Likewise.
	(neon_vget_lane<mode>_zext_internal): Likewise.
	(neon_vdup_n<mode>): Likewise.
	(neon_vdup_nv2di): Likewise.
	(neon_vdpu_lane<mode>_internal): Likewise.
	(neon_vswp<mode>): Likewise.
	(float<mode><V_cvtto>2): Likewise.
	(floatuns<mode><V_cvtto>2): Likewise.
	(fix_trunc<mode><V_cvtto>)2): Likewise
	(fixuns_trunc<mode><V_cvtto)2): Likewise.
	(neon_vcvt<mode>): Likewise.
	(neon_vcvtv4sfv4hf): Likewise.
	(neon_vcvtv4hfv4sf): Likewise.
	(neon_vcvt_n<mode>): Likewise.
	(neon_vmovn<mode>): Likewise.
	(neon_vqmovn<mode>): Likewise.
	(neon_vqmovun<mode>): Likewise.
	(neon_vmovl<mode>): Likewise.
	(neon_vmul_lane<mode>): Likewise.
	(neon_vmull_lane<mode>): Likewise.
	(neon_vqdmull_lane<mode>): Likewise.
	(neon_vqdmulh_lane<mode>): Likewise.
	(neon_vmla_lane<mode>): Likewise.
	(neon_vmlal_lane<mode>): Likewise.
	(neon_vqdmlal_lane<mode>): Likewise.
	(neon_vmls_lane<mode>): Likewise.
	(neon_vmlsl_lane<mode>): Likewise.
	(neon_vqdmlsl_lane<mode>): Likewise.
	(neon_vext<mode>): Likewise.
	(neon_vrev64<mode>): Likewise.
	(neon_vrev32<mode>): Likewise.
	(neon_vrev16<mode>): Likewise.
	(neon_vbsl<mode>_internal): Likewise.
	(neon_vshl<mode>): Likewise.
	(neon_vqshl<mode>): Likewise.
	(neon_vshr_n<mode>): Likewise.
	(neon_vshrn_n<mode>): Likewise.
	(neon_vqshrn_n<mode>): Likewise.
	(neon_vqshrun_n<mode>): Likewise.
	(neon_vshl_n<mode>): Likewise.
	(neon_vqshl_n<mode>): Likewise.
	(neon_vqshlu_n<mode>): Likewise.
	(neon_vshll_n<mode>): Likewise.
	(neon_vsra_n<mode>): Likewise.
	(neon_vsri_n<mode>): Likewise.
	(neon_vsli_n<mode>): Likewise.
	(neon_vtbl1v8qi): Likewise.
	(neon_vtbl2v8qi): Likewise.
	(neon_vtbl3v8qi): Likewise.
	(neon_vtbl4v8qi): Likewise.
	(neon_vtbx1v8qi): Likewise.
	(neon_vtbx2v8qi): Likewise.
	(neon_vtbx3v8qi): Likewise.
	(neon_vtbx4v8qi): Likewise.
	(neon_vtrn<mode>_internal): Likewise.
	(neon_vzip<mode>_internal): Likewise.
	(neon_vuzp<mode>_internal): Likewise.
	(neon_vld1<mode>): Likewise.
	(neon_vld1_lane<mode>): Likewise.
	(neon_vld1_dup<mode>): Likewise.
	(neon_vld1_dupv2di): Likewise.
	(neon_vst1<mode>): Likewise.
	(neon_vst1_lane<mode>): Likewise.
	(neon_vld2<mode>): Likewise.
	(neon_vld2_lane<mode>): Likewise.
	(neon_vld2_dup<mode>): Likewise.
	(neon_vst2<mode>): Likewise.
	(neon_vst2_lane<mode>): Likewise.
	(neon_vld3<mode>): Likewise.
	(neon_vld3qa<mode>): Likewise.
	(neon_vld3qb<mode>): Likewise.
	(neon_vld3_lane<mode>): Likewise.
	(neon_vld3_dup<mode>): Likewise.
	(neon_vst3<mode>): Likewise.
	(neon_vst3qa<mode>): Likewise.
	(neon_vst3qb<mode>): Likewise.
	(neon_vst3_lane<mode>): Likewise.
	(neon_vld4<mode>): Likewise.
	(neon_vld4qa<mode>): Likewise.
	(neon_vld4qb<mode>): Likewise.
	(neon_vld4_lane<mode>): Likewise.
	(neon_vld4_dup<mode>): Likewise.
	(neon_vst4<mode>): Likewise.
	(neon_vst4qa<mode>): Likewise.
	(neon_vst4qb<mode>): Likewise.
	(neon_vst4_lane<mode>): Likewise.
	(neon_vec_unpack<US>_lo_<mode>): Likewise.
	(neon_vec_unpack<US>_hi_<mode>): Likewise.
	(neon_vec_<US>mult_lo_<mode>): Likewise.
	(neon_vec_<US>mult_hi_<mode>): Likewise.
	(neon_vec_<US>shiftl_<mode>): Likewise.
	(neon_unpack<US>_<mode>): Likewise.
	(neon_vec_<US>mult_<mode>): Likewise.
	(vec_pack_trunc_<mode>): Likewise.
	(neon_vec_pack_trunk_<mode>): Likewise.
	(neon_vabd<mode>_2): Likewise.
	(neon_vabd<mode>_3): Likewise.
	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
	(thumb2_movsi_vfp): Likewise.
	(movdi_vfp): Likewise.
	(movdi_vfp_cortexa8): Likewise.
	(movhf_vfp_neon): Likewise.
	(movhf_vfp): Likewiwse.
	(movsf_vfp): Likewiwse.
	(thumb2_movsf_vfp): Likewiwse.
	(movdf_vfp): Likewise.
	(thumb2_movdf_vfp): Likewise.
	(movsfcc_vfp): Likewise.
	(thumb2_movsfcc_vfp): Likewise.
	(movdfcc_vfp): Likewise.
	(thumb2_movdfcc_vfp): Likewise.
	* config/arm/arm.c (cortexa7_older_only): Update for attribute change.
	* config/arm/arm1020e.md (v10_c2v): Update for attribute change.
	(v10_v2c): Likewise.
	* config/arm/cortex-a15-neon.md (cortex_a15_neon_int_1): Update for
	attribute change.
	(cortex_a15_neon_int_2): Likewise.
	(cortex_a15_neon_int_3): Likewise.
	(cortex_a15_neon_int_4): Likewise.
	(cortex_a15_neon_int_5): Likewise.
	(cortex_a15_neon_vqneg_vqabs): Likewise.
	(cortex_a15_neon_vmov): Likewise.
	(cortex_a15_neon_vaba): Likewise.
	(cortex_a15_neon_vaba_qqq): Likewise.
	(cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise.
	(cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_\
	scalar_64_32_long_scalar): Likewise.
	(cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a15_neon_mla_qqq_8_16): Likewise.
	(cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
	lotype_qdd_64_32_long): Likewise.
	(cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise.
	(cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
	(cortex_a15_neon_mul_qqd_32_scalar): Likewise.
	(cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
	(cortex_a15_neon_shift_1): Likewise.
	(cortex_a15_neon_shift_2): Likewise.
	(cortex_a15_neon_shift_3): Likewise.
	(cortex_a15_neon_vshl_ddd): Likewise.
	(cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
	(cortex_a15_neon_vsra_vrsra): Likewise.
	(cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise.
	(cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise.
	(cortex_a15_neon_fp_vmul_ddd): Likewise.
	(cortex_a15_neon_fp_vmul_qqd): Likewise.
	(cortex_a15_neon_fp_vmla_ddd): Likewise.
	(cortex_a15_neon_fp_vmla_qqq): Likewise.
	(cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise.
	(cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise.
	(cortex_a15_neon_bp_simple): Likewise.
	(cortex_a15_neon_bp_2cycle): Likewise.
	(cortex_a15_neon_bp_3cycle): Likewise.
	(cortex_a15_neon_vld1_1_2_regs): Likewise.
	(cortex_a15_neon_vld1_3_4_regs): Likewise.
	(cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
	(cortex_a15_neon_vld2_4_regs): Likewise.
	(cortex_a15_neon_vld3_vld4): Likewise.
	(cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
	(cortex_a15_neon_vst1_3_4_regs): Likewise.
	(cortex_a15_neon_vst2_4_regs_vst3_vst4): Likewise.
	(cortex_a15_neon_vst3_vst4): Likewise.
	(cortex_a15_neon_vld1_vld2_lane): Likewise.
	(cortex_a15_neon_vld3_vld4_lane" 10
	(cortex_a15_neon_vst1_vst2_lane): Likewise.
	(cortex_a15_neon_vst3_vst4_lane): Likewise.
	(cortex_a15_neon_vld3_vld4_all_lanes): Likewise.
	(cortex_a15_neon_ldm_2): Likewise.0
	(cortex_a15_neon_stm_2): Likewise.
	(cortex_a15_neon_mcr): Likewise.
	(cortex_a15_neon_mcr_2_mcrr): Likewise.
	(cortex_a15_neon_mrc): Likewise.
	(cortex_a15_neon_mrrc): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute
	change.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	(cortex_a15_mult32): Likewise.
	(cortex_a15_mult64): Likewise.
	(cortex_a15_block): Likewise.
	(cortex_a15_branch): Likewise.
	(cortex_a15_load1): Likewise.
	(cortex_a15_load3): Likewise.
	(cortex_a15_store1): Likewise.
	(cortex_a15_store3): Likewise.
	(cortex_a15_call): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_r2f): Update for attribute
	change.
	(cortex_a5_f2r): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_r2f): Update for attribute
	change.
	(cortex_a53_f2r): Likewise.
	* config/arm/cortex-a7.md
	(cortex_a7_branch): Update for attribute change.
	(cortex_a7_call): Likewise.
	(cortex_a7_alu_imm): Likewise.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	(cortex_a7_mul): Likewise.
	(cortex_a7_load1): Likewise.
	(cortex_a7_store1): Likewise.
	(cortex_a7_load2): Likewise.
	(cortex_a7_store2): Likewise.
	(cortex_a7_load3): Likewise.
	(cortex_a7_store3): Likewise.
	(cortex_a7_load4): Likewise.
	(cortex_a7_store4): Likewise.
	(cortex_a7_fpalu): Likewise.
	(cortex_a7_fconst): Likewise.
	(cortex_a7_fpmuls): Likewise.
	(cortex_a7_neon_mul): Likewise.
	(cortex_a7_fpmacs): Likewise.
	(cortex_a7_neon_mla: Likewise.
	(cortex_a7_fpmuld: Likewise.
	(cortex_a7_fpmacd: Likewise.
	(cortex_a7_fpfmad: Likewise.
	(cortex_a7_fdivs: Likewise.
	(cortex_a7_fdivd: Likewise.
	(cortex_a7_r2f: Likewise.
	(cortex_a7_f2r: Likewise.
	(cortex_a7_f_flags: Likewise.
	(cortex_a7_f_loads: Likewise.
	(cortex_a7_f_loadd: Likewise.
	(cortex_a7_f_stores: Likewise.
	(cortex_a7_f_stored: Likewise.
	(cortex_a7_neon): Likewise.
	* config/arm/cortex-a8-neon.md
	(cortex_a8_neon_mrc): Update for attribute change.
	(cortex_a8_neon_mrrc): Likewise.
	(cortex_a8_neon_int_1): Likewise.
	(cortex_a8_neon_int_2): Likewise.
	(cortex_a8_neon_int_3): Likewise.
	(cortex_a8_neon_int_4): Likewise.
	(cortex_a8_neon_int_5): Likewise.
	(cortex_a8_neon_vqneg_vqabs): Likewise.
	(cortex_a8_neon_vmov): Likewise.
	(cortex_a8_neon_vaba): Likewise.
	(cortex_a8_neon_vaba_qqq): Likewise.
	(cortex_a8_neon_vsma): Likewise.
	(cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise.
	(cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
	Likewise.
	(cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a8_neon_mla_qqq_8_16): Likewise.
	(cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
	long_scalar_qdd_64_32_long): Likewise.
	(cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise.
	(cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
	(cortex_a8_neon_mul_qqd_32_scalar): Likewise.
	(cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
	(cortex_a8_neon_shift_1): Likewise.
	(cortex_a8_neon_shift_2): Likewise.
	(cortex_a8_neon_shift_3): Likewise.
	(cortex_a8_neon_vshl_ddd): Likewise.
	(cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
	(cortex_a8_neon_vsra_vrsra): Likewise.
	(cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise.
	(cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise.
	(cortex_a8_neon_fp_vsum): Likewise.
	(cortex_a8_neon_fp_vmul_ddd): Likewise.
	(cortex_a8_neon_fp_vmul_qqd): Likewise.
	(cortex_a8_neon_fp_vmla_ddd): Likewise.
	(cortex_a8_neon_fp_vmla_qqq): Likewise.
	(cortex_a8_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a8_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise.
	(cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise.
	(cortex_a8_neon_bp_simple): Likewise.
	(cortex_a8_neon_bp_2cycle): Likewise.
	(cortex_a8_neon_bp_3cycle): Likewise.
	(cortex_a8_neon_ldr): Likewise.
	(cortex_a8_neon_str): Likewise.
	(cortex_a8_neon_vld1_1_2_regs): Likewise.
	(cortex_a8_neon_vld1_3_4_regs): Likewise.
	(cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
	(cortex_a8_neon_vld2_4_regs): Likewise.
	(cortex_a8_neon_vld3_vld4): Likewise.
	(cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
	(cortex_a8_neon_vst1_3_4_regs): Likewise.
	(cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise.
	(cortex_a8_neon_vst3_vst4): Likewise.
	(cortex_a8_neon_vld1_vld2_lane): Likewise.
	(cortex_a8_neon_vld3_vld4_lane): Likewise.
	(cortex_a8_neon_vst1_vst2_lane): Likewise.
	(cortex_a8_neon_vst3_vst4_lane): Likewise.
	(cortex_a8_neon_vld3_vld4_all_lanes): Likewise.
	(cortex_a8_neon_mcr): Likewise.
	(cortex_a8_neon_mcr_2_mcrr): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute
	change.
	* config/arm/cortex-a9-neon.md (ca9_neon_mrc): Update for attribute
	change.
	(ca9_neon_mrrc): Likewise.
	(cortex_a9_neon_int_1): Likewise.
	(cortex_a9_neon_int_2): Likewise.
	(cortex_a9_neon_int_3): Likewise.
	(cortex_a9_neon_int_4): Likewise.
	(cortex_a9_neon_int_5): Likewise.
	(cortex_a9_neon_vqneg_vqabs): Likewise.
	(cortex_a9_neon_vmov): Likewise.
	(cortex_a9_neon_vaba): Likewise.
	(cortex_a9_neon_vaba_qqq): Likewise.
	(cortex_a9_neon_vsma): Likewise.
	(cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise.
	(cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
	Likewise.
	(cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
	(cortex_a9_neon_mla_qqq_8_16): Likewise.
	(cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
	long_scalar_qdd_64_32_long): Likewise.
	(cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise.
	(cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
	(cortex_a9_neon_mul_qqd_32_scalar): Likewise.
	(cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
	(cortex_a9_neon_shift_1): Likewise.
	(cortex_a9_neon_shift_2): Likewise.
	(cortex_a9_neon_shift_3): Likewise.
	(cortex_a9_neon_vshl_ddd): Likewise.
	(cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
	(cortex_a9_neon_vsra_vrsra): Likewise.
	(cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise.
	(cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise.
	(cortex_a9_neon_fp_vsum): Likewise.
	(cortex_a9_neon_fp_vmul_ddd): Likewise.
	(cortex_a9_neon_fp_vmul_qqd): Likewise.
	(cortex_a9_neon_fp_vmla_ddd): Likewise.
	(cortex_a9_neon_fp_vmla_qqq): Likewise.
	(cortex_a9_neon_fp_vmla_ddd_scalar): Likewise.
	(cortex_a9_neon_fp_vmla_qqq_scalar): Likewise.
	(cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise.
	(cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise.
	(cortex_a9_neon_bp_simple): Likewise.
	(cortex_a9_neon_bp_2cycle): Likewise.
	(cortex_a9_neon_bp_3cycle): Likewise.
	(cortex_a9_neon_ldr): Likewise.
	(cortex_a9_neon_str): Likewise.
	(cortex_a9_neon_vld1_1_2_regs): Likewise.
	(cortex_a9_neon_vld1_3_4_regs): Likewise.
	(cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
	(cortex_a9_neon_vld2_4_regs): Likewise.
	(cortex_a9_neon_vld3_vld4): Likewise.
	(cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
	(cortex_a9_neon_vst1_3_4_regs): Likewise.
	(cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise.
	(cortex_a9_neon_vst3_vst4): Likewise.
	(cortex_a9_neon_vld1_vld2_lane): Likewise.
	(cortex_a9_neon_vld3_vld4_lane): Likewise.
	(cortex_a9_neon_vst1_vst2_lane): Likewise.
	(cortex_a9_neon_vst3_vst4_lane): Likewise.
	(cortex_a9_neon_vld3_vld4_all_lanes): Likewise.
	(cortex_a9_neon_mcr): Likewise.
	(cortex_a9_neon_mcr_2_mcrr): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change.
	(cortex_a9_fps): Likewise.
	* config/arm/cortex-m4-fpu.md (cortex_m4_vmov_2): Update for attribute
	change.
	(cortex_m4_fmuls): Likewise.
	* config/arm/cortex-r4f.md (cortex_r4_mcr): Update for attribute
	change.
	(cortex_r4_mrc): Likewise.
	* config/arm/iterators.md: Update comment referring to neon_type.
	* config/arm/iwmmxt.md
	(iwmmxt_arm_movdi): Update for attribute change.
	(iwmmxt_movsi_insn): Likewise.
	* config/arm/marvell-pj4.md
	(pj4_vfp_to_core): Update for attribute change.
	(pj4_core_to_vfp): Likewise.
	* config/arm/neon-schedgen.ml (emit_insn_reservations): Update for
	attribute change.
	* config/arm/vfp11.md (vfp_fload): Update for attribute change.
	(vfp_fstore): Likewise.
	* doc/md.texi: Change references to neon_type to refer to type.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r201436
	2013-08-02  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/types.md (define_attr "type"): Add "load_acq" and "store_rel".
	* config/arm/cortex-a53.md (cortex_a53_load1): Update for attribute
	changes.
	(cortex_a53_store1): Likewise.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r201400
	2013-08-01  Sofiane Naci  <sofiane.naci@arm.com>

	* config.gcc (aarch64*-*-*): Add aarch-common.o to extra_objs.  Add
	aarch-common-protos.h to extra_headers.
	(aarch64*-*-*): Add arm/aarch-common-protos.h to tm_p_file.
	* config/aarch64/aarch64.md: Include "../arm/cortex-a53.md".
	* config/aarch64/t-aarch64 (aarch-common.o): Define.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r201399
	2013-08-01  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64.md (define_attr "type"): Delete.
	Include "../arm/types.md".  Define "type" attribute for all patterns.
	* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>): Update for
	attribute changes.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r201376
	2013-07-31  Sofiane Naci  <sofiane.naci@arm.com>

	* config.gcc (arm*-*-*): Add aarch-common.o to extra_objs.  Add
	aarch-common-protos.h to extra_headers.
	(arm*-*-*): Add arm/aarch-common-protos.h to tm_p_file.
	* config/arm/arm.c (arm_early_load_addr_dep): Move from here to ...
	(arm_early_store_addr_dep): Likewise.
	(arm_no_early_alu_shift_dep: Likewise.
	(arm_no_early_alu_shift_value_dep: Likewise.
	(arm_no_early_mul_dep: Likewise.
	(arm_no_early_store_addr_dep: Likewise.
	(arm_mac_accumulator_is_mul_result: Likewise.
	(arm_mac_accumulator_is_result: Likewise.
	* config/arm/aarch-common.c: ... here.  New file.
	* config/arm/arm-protos.h (arm_early_load_addr_dep): Move from here to ...
	(arm_early_store_addr_dep): Likewise.
	(arm_no_early_alu_shift_dep: Likewise.
	(arm_no_early_alu_shift_value_dep: Likewise.
	(arm_no_early_mul_dep: Likewise.
	(arm_no_early_store_addr_dep: Likewise.
	(arm_mac_accumulator_is_mul_result: Likewise.
	(arm_mac_accumulator_is_result: Likewise.
	* config/arm/aarch-common-protos.h: ... here.  New file.
	* config/arm/t-arm (aarch-common.o): Define.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r201375
	2013-07-31  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/arm.md: Include new file "types.md".
	(define_attr "type"): Move from here to ...
	(define_attr "mul32"): Likewise.
	(define_attr "mul64"): Likewise.
	* config/arm/types.md: ... here.  New file.

2014-04-07  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r202663
	2013-09-17  Cong Hou  <congh@google.com>

	* tree-vect-patterns.c (vect_recog_dot_prod_pattern): Fix a bug
	when checking the dot production pattern. The type of rhs operand
	of multiply is now checked correctly.

2014-04-02  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	Backport from trunk r208511
	2014-03-12  Christian Bruel  <christian.bruel@st.com>

	PR target/60264
	* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Emit a
	REG_CFA_DEF_CFA note.
	(arm_expand_epilogue_apcs_frame): call arm_add_cfa_adjust_cfa_note.
	(arm_unwind_emit): Allow REG_CFA_DEF_CFA.

2014-03-14  Yvan Roux  <yvan.roux@linaro.org>

	* LINARO-VERSION: Bump version.

2014-03-11  Yvan Roux  <yvan.roux@linaro.org>

	GCC Linaro 4.8-2014.03 released.
	* LINARO-VERSION: Update.

2014-02-13  Yvan Roux  <yvan.roux@linaro.org>

	* LINARO-VERSION: Bump version.

2014-02-11  Yvan Roux  <yvan.roux@linaro.org>

	GCC Linaro 4.8-2014.02 released.
	* LINARO-VERSION: Update.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206518
	2014-01-10 Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (arm_init_iwmmxt_builtins): Skip
	non-iwmmxt builtins.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206151
	2013-12-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/neon.ml (crypto_intrinsics): Add vceq_64 and vtst_p64.
	* config/arm/arm_neon.h: Regenerate.
	* config/arm/neon-docgen.ml: Add vceq_p64 and vtst_p64.
	* doc/arm-neon-intrinsics.texi: Regenerate.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206149
	2013-12-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm_acle.h: Add underscores before variables.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206132
	2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/neon-docgen.ml: Add crypto intrinsics documentation.
	* doc/arm-neon-intrinsics.texi: Regenerate.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206131
	2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/neon-testgen.ml (effective_target): Handle "CRYPTO".

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206130
	2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	 * config/arm/arm.c (enum arm_builtins): Add crypto builtins.
	 (arm_init_neon_builtins): Handle crypto builtins.
	 (bdesc_2arg): Likewise.
	 (bdesc_1arg): Likewise.
	 (bdesc_3arg): New table.
	 (arm_expand_ternop_builtin): New function.
	 (arm_expand_unop_builtin): Handle sha1h explicitly.
	 (arm_expand_builtin): Handle ternary builtins.
	 * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
	 Define __ARM_FEATURE_CRYPTO.
	 * config/arm/arm.md: Include crypto.md.
	 (is_neon_type): Add crypto types.
	 * config/arm/arm_neon_builtins.def: Add TImode reinterprets.
	 * config/arm/crypto.def: New.
	 * config/arm/crypto.md: Likewise.
	 * config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
	 (CRYPTO_BINARY): Likewise.
	 (CRYPTO_TERNARY): Likewise.
	 (CRYPTO_SELECTING): Likewise.
	 (crypto_pattern): New int attribute.
	 (crypto_size_sfx): Likewise.
	 (crypto_mode): Likewise.
	 (crypto_type): Likewise.
	 * config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
	 Handle crypto intrinsics.
	 * config/arm/neon.ml: Add support for poly64 and polt128 types
	 and intrinsics. Define crypto intrinsics.
	 * config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
	 (neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
	 (neon_vreinterpretv8hi<mode>): Likewise.
	 (neon_vreinterpretv4si<mode>): Likewise.
	 (neon_vreinterpretv4sf<mode>): Likewise.
	 (neon_vreinterpretv2di<mode>): Likewise.
	 * config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
	 UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
	 UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
	 UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
	 * config/arm/arm_neon.h: Regenerate.

	Modifications needed to backport into linaro-4_8-branch:
	* config/arm/arm.md (attribute neon_type): neon_crypto_aes,
	neon_crypto_sha1_xor, neon_crypto_sha1_fast,
	neon_crypto_sha1_slow, neon_crypto_sha256_fast,
	neon_crypto_sha256_slow, neon_mul_d_long: New.
	instead of:
	* config/arm/arm.md: Include crypto.md.
	(is_neon_type): Add crypto types.


2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206128
	2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* Makefile.in (TEXI_GCC_FILES): Add arm-acle-intrinsics.texi.
	* config.gcc (extra_headers): Add arm_acle.h.
	* config/arm/arm.c (FL_CRC32): Define.
	(arm_have_crc): Likewise.
	(arm_option_override): Set arm_have_crc.
	(arm_builtins): Add CRC32 builtins.
	(bdesc_2arg): Likewise.
	(arm_init_crc32_builtins): New function.
	(arm_init_builtins): Initialise CRC32 builtins.
	(arm_file_start): Handle architecture extensions.
	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FEATURE_CRC32.
	Define __ARM_32BIT_STATE.
	(TARGET_CRC32): Define.
	* config/arm/arm-arches.def: Add armv8-a+crc.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.md (type): Add crc.
	(<crc_variant>): New insn.
	* config/arm/arm_acle.h: New file.
	* config/arm/iterators.md (CRC): New int iterator.
	(crc_variant, crc_mode): New int attributes.
	* confg/arm/unspecs.md (UNSPEC_CRC32B, UNSPEC_CRC32H, UNSPEC_CRC32W,
	UNSPEC_CRC32CB, UNSPEC_CRC32CH, UNSPEC_CRC32CW): New unspecs.
	* doc/invoke.texi: Document -march=armv8-a+crc option.
	* doc/extend.texi: Document ACLE intrinsics.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206120
	2013-12-19  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
	Define builtin types for poly64_t poly128_t.
	(TYPES_BINOPP, aarch64_types_binopp_qualifiers): New.
	* aarch64/aarch64-simd-builtins.def: Update builtins table.
	* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi,
	aarch64_crypto_pmullv2di): New.
	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for
	poly64x2_t mangler.
	* config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define.
	(vmull_p64, vmull_high_p64): New.
	* config/aarch64/iterators.md (UNSPEC_PMULL<2>): New.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206119
	2013-12-19  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
	* config/aarch64/aarch64-simd.md (aarch64_crypto_sha256h<sha256_op>v4si,
	aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New.
	* config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32,
	vsha256su0q_u32, vsha256su1q_u32): New.
	* config/aarch64/iterators.md (UNSPEC_SHA256H<2>, UNSPEC_SHA256SU<01>):
	New.
	(CRYPTO_SHA256): New int iterator.
	(sha256_op): New int attribute.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206118
	2013-12-19  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
	* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
	TYPES_TERNOPU): New.
	* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
	aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
	aarch64_crypto_sha1su0v4si): New.
	* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
	vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
	* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
	New.
	(CRYPTO_SHA1): New int iterator.
	(sha1_op): New int attribute.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206117
	2013-12-19  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
	* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
	TYPES_BINOPU): New.
	* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
	aarch64_crypto_aes<aesmc_op>v16qi): New.
	* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
	vaesimcq_u8): New.
	* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
	UNSPEC_AESIMC): New.
	(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
	(aes_op, aesmc_op): New int attributes.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206115
	2013-12-19  Tejas Belagod  <tejas.belagod@arm.com>

	* config/arm/types.md (neon_mul_d_long, crypto_aes, crypto_sha1_xor,
	crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast,
	crypto_sha256_slow): New.

	Modifications needed to backport into linaro-4_8-branch:
	* config/aarch64/aarch64-simd.md (attribute simd_type):
	(simd_mul_d_long, simd_crypto_aes, simd_crypto_sha1_xor,
	simd_crypto_sha1_fast, simd_crypto_sha1_slow, simd_crypto_sha256_fast,
	simd_crypto_sha256_slow) : New.
	instead of the above change.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r206114
	2013-12-19  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64.h (TARGET_CRYPTO): New.
	(__ARM_FEATURE_CRYPTO): Define if TARGET_CRYPTO is true.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r205384.
	2013-11-26  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_type_qualifiers): Add qualifier_poly.
	(aarch64_build_scalar_type): Also build Poly types.
	(aarch64_build_vector_type): Likewise.
	(aarch64_build_type): Likewise.
	(aarch64_build_signed_type): New.
	(aarch64_build_unsigned_type): Likewise.
	(aarch64_build_poly_type): Likewise.
	(aarch64_init_simd_builtins): Also handle Poly types.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r205383.
	2013-11-26  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(VAR1): Use new naming scheme for aarch64_builtins.
	(aarch64_builtin_vectorized_function): Use new
	aarch64_builtins names.

2014-02-10  Michael Collison  <michael.collison@linaro.org>

	Backport from trunk r205092.
	2013-11-20  James Greenhalgh  <james.greenhalgh@arm.com>

	* gcc/config/aarch64/aarch64-builtins.c
	(aarch64_simd_itype): Remove.
	(aarch64_simd_builtin_datum): Remove itype, add
	qualifiers pointer.
	(VAR1): Use qualifiers.
	(aarch64_build_scalar_type): New.
	(aarch64_build_vector_type): Likewise.
	(aarch64_build_type): Likewise.
	(aarch64_init_simd_builtins): Refactor, remove special cases,
	consolidate main loop.
	(aarch64_simd_expand_args): Likewise.

2014-02-01  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r202875,202980.
	2013-09-24  Xinliang David Li <davidxl@google.com>

	* tree-vect-data-refs.c (vect_enhance_data_refs_alignment):
	Check max peel iterations parameter.
	* param.def: New parameter.
	* doc/invoke.texi: Document New parameter.

	2013-09-27  Xinliang David Li  <davidxl@google.com>

	* opts.c (finish_options): Adjust parameters
	according to vect cost model.
	(common_handle_option): Set dynamic vect cost
	model for FDO.
	targhooks.c (default_add_stmt_cost): Compute stmt cost
	unconditionally.
	* tree-vect-loop.c (vect_estimate_min_profitable_iters):
	Use helper function.
	* tree-vectorizer.h (unlimited_cost_model): New function.
	* tree-vect-slp.c (vect_slp_analyze_bb_1): Use helper function.
	* tree-vect-data-refs.c (vect_peeling_hash_insert): Use helper
	function.
	(vect_enhance_data_refs_alignment): Ditto.
	* flag-types.h: New enum.
	* common/config/i386/i386-common.c (ix86_option_init_struct):
	No need to initialize vect_cost_model flag.
	* config/i386/i386.c (ix86_add_stmt_cost): Compute stmt cost
	unconditionally.

2014-01-21  Zhenqiang Chen <zhenqiang.chen@linaro.org>

	Backport from trunk r200103
	2013-06-15  Jeff Law  <law@redhat.com>

	* gimple.h (gimple_can_coalesce_p): Prototype.
	* tree-ssa-coalesce.c (gimple_can_coalesce_p): New function.
	(create_outofssa_var_map, coalesce_partitions): Use it.
	* tree-ssa-uncprop.c (uncprop_into_successor_phis): Similarly.
	* tree-ssa-live.c (var_map_base_init): Use TYPE_CANONICAL
	if it's available.

2014-01-21  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2014-01-17  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2014.01 released.
	* LINARO-VERSION: Update.

2014-01-16  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	Linaro local patch for armv4t multilib support.
	* gcc/config/arm/t-mlibs: New file.
	* config.gcc: Add t-mlibs.
	* incpath.c (add_standard_paths): Try multilib path first.
	* gcc.c (for_each_path): Likewise.

2013-12-21  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2013-12-21  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2013.12 released.
	* LINARO-VERSION: Update.

2013-12-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r204737.
	2013-11-13  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/aarch64/aarch64.h (FRAME_GROWS_DOWNWARD): Define to 1.
	* config/aarch64/aarch64.c (aarch64_initial_elimination_offset):
	Update offset calculations.

2013-12-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r203327.
	2013-10-09  Zhenqiang Chen  <zhenqiang.chen@arm.com>

	* tree-ssa-phiopts.c (rhs_is_fed_for_value_replacement): New function.
	(operand_equal_for_value_replacement): New function, extracted from
	value_replacement and enhanced to catch more cases.
	(value_replacement): Use operand_equal_for_value_replacement.

2013-11-18  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2013-11-14  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2013.11 released.
	* LINARO-VERSION: Update.

2013-11-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Revert backport from trunk r197526.
	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (negdi_extendsidi): New pattern.
	(negdi_zero_extendsidi): Likewise.

2013-11-05  Zhenqiang Chen <zhenqiang.chen@linaro.org>

	Backport from trunk r203267, r203603 and r204247.
	2013-10-08  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	PR target/58423
	* config/arm/arm.c (arm_emit_ldrd_pop): Attach
	RTX_FRAME_RELATED_P on INSN.

	2013-10-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/t-aprofile: New file.
	* config.gcc: Handle --with-multilib-list option.

	2013-10-31  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* lower-subreg.c (resolve_simple_move): Copy REG_INC note.

2013-10-17  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r200956
	2013-07-15  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64-protos.h (aarch64_symbol_type):
	Define SYMBOL_TINY_GOT, update comment.
	* config/aarch64/aarch64.c
	(aarch64_load_symref_appropriately): Handle SYMBOL_TINY_GOT.
	(aarch64_expand_mov_immediate): Likewise.
	(aarch64_print_operand): Likewise.
	(aarch64_classify_symbol): Likewise.
	* config/aarch64/aarch64.md (UNSPEC_GOTTINYPIC): Define.
	(ldr_got_tiny): Define.

2013-10-16  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2013-10-15  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2013.10 released.
	* LINARO-VERSION: Update.

2013-10-09  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198526,198527,200020,200595.
	2013-05-02  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (*and_one_cmpl<mode>3_compare0):
	New pattern.
	(*and_one_cmplsi3_compare0_uxtw): Likewise.
	(*and_one_cmpl_<SHIFT:optab><mode>3_compare0): Likewise.
	(*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw): Likewise.

	2013-05-02  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (movsi_aarch64): Only allow to/from
	S reg when fp attribute set.
	(movdi_aarch64): Only allow to/from D reg when fp attribute set.

	2013-06-12  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): convert to split.
	(aarch64_simd_combine<mode>): New instruction expansion.
	* config/aarch64/aarch64-protos.h (aarch64_split_simd_combine): New
	function prototype.
	* config/aarch64/aarch64.c (aarch64_split_combine): New function.
	* config/aarch64/iterators.md (Vdbl): Add entry for DF.

	2013-07-02  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (*extr_insv_reg<mode>): New pattern.

2013-10-09  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201879.
	2013-08-20  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	* config/arm/linux-elf.h (MULTILIB_DEFAULTS): Remove definition.
	* config/arm/t-linux-eabi (MULTILIB_OPTIONS): Document association
	with MULTLIB_DEFAULTS.

2013-10-09  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201871.
	2013-08-20  Pavel Chupin  <pavel.v.chupin@intel.com>

	Fix LIB_SPEC for systems without libpthread.

	* config/gnu-user.h: Introduce GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC.
	* config/arm/linux-eabi.h: Use GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC
	for Android.
	* config/i386/linux-common.h: Likewise.
	* config/mips/linux-common.h: Likewise.

2013-10-08  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r202702.
	2013-09-18  Richard Earnshaw  <rearnsha@arm.com>

	* arm.c (arm_get_frame_offsets): Validate architecture supports
	LDRD/STRD before accepting the tuning preference.
	(arm_expand_prologue): Likewise.
	(arm_expand_epilogue): Likewise.

2013-10-04  Venkataramanan.Kumar  <venkataramanan.kumar@linaro.org>

	Backport from trunk r203028.
	2013-09-30  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>

	* config/aarch64/aarch64.h (MCOUNT_NAME): Define.
	(NO_PROFILE_COUNTERS): Likewise.
	(PROFILE_HOOK): Likewise.
	(FUNCTION_PROFILER): Likewise.
	* config/aarch64/aarch64.c (aarch64_function_profiler): Remove.

2013-10-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201923,201927.
	2013-08-22  Julian Brown  <julian@codesourcery.com>

	* configure.ac: Add aarch64 to list of arches which use "nop" in
	debug_line test.
	* configure: Regenerate.

	2013-08-22  Paolo Carlini  <paolo.carlini@oracle.com>

	* configure.ac: Add backslashes missing from the last change.
	* configure: Regenerate.

2013-10-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r202023,202108.
	2013-08-27  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/arm_neon.h: Replace all inline asm implementations
	of vget_low_* with implementations in terms of other intrinsics.

	2013-08-30  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/arm_neon.h (__AARCH64_UINT64_C, __AARCH64_INT64_C): New
	arm_neon.h's internal macros to specify 64-bit constants. Avoid using
	stdint.h's macros.

2013-10-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201260,202400.
	2013-07-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
	    Richard Earnshaw  <richard.earnshaw@arm.com>

	* combine.c (simplify_comparison): Re-canonicalize operands
	where appropriate.
	* config/arm/arm.md (movcond_addsi): New splitter.

	2013-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
	comparison with negated operand.
	* config/aarch64/aarch64.md (compare_neg<mode>): Match canonical
	RTL form.

2013-10-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r202164.
	2013-09-02  Bin Cheng  <bin.cheng@arm.com>

	* tree-ssa-loop-ivopts.c (set_autoinc_for_original_candidates):
	Find auto-increment use both before and after candidate.

2013-10-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r202279.
	2013-09-05  Richard Earnshaw  <rearnsha@arm.com>

	* arm.c (thumb2_emit_strd_push): Rewrite to use pre-decrement on
	initial store.
	* thumb2.md (thumb2_storewb_parisi): New pattern.

2013-10-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r202275.
	2013-09-05  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/aarch64-option-extensions.def: Add
	AARCH64_OPT_EXTENSION of 'crc'.
	* config/aarch64/aarch64.h (AARCH64_FL_CRC): New define.
	(AARCH64_ISA_CRC): Ditto.
	* doc/invoke.texi (-march and -mcpu feature modifiers): Add
	description of the CRC extension.

2013-10-01  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201250.
	2013-07-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_addsi3, addsi3_carryin_<optab>,
	addsi3_carryin_alt2_<optab>): Correct output template.

2013-10-01  Kugan Vivekanandarajah  <kuganv@linaro.org>

	Backport from trunk r203059,203116.
	2013-10-01  Kugan Vivekanandarajah  <kuganv@linaro.org>

	PR target/58578
	Revert
	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>
	* config/arm/arm.md (arm_ashldi3_1bit):  define_insn into
	define_insn_and_split.
	(arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise.
	(shiftsi3_compare): New pattern.
	(rrx): New pattern.
	* config/arm/unspecs.md (UNSPEC_RRX): New.

2013-09-11  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2013-09-10  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2013.09 released.
	* LINARO-VERSION: Update.

2013-09-10  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>

	Backport from trunk r200197, 201411.
	2013-06-19  Richard Earnshaw  <rearnsha@arm.com>

	arm.md (split for eq(reg, 0)): Add variants for ARMv5 and Thumb2.
	(peepholes for eq(reg, not-0)): Ensure condition register is dead after
	pattern.  Use more efficient sequences on ARMv5 and Thumb2.

	2013-08-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)):
	Generate canonical plus rtx with negated immediate instead of minus
	where appropriate.
	* config/arm/arm.c (thumb2_reorg): Handle ADCS <Rd>, <Rn> case.

2013-09-10  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r200593,201024,201025,201122,201124,201126.
	2013-07-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_andsi3_insn): Add alternatives for 16-bit
	encoding.
	(iorsi3_insn): Likewise.
	(arm_xorsi3): Likewise.

	2013-07-18  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
	"arlo_imm".  Rename "alu_reg" to "arlo_reg".  Rename "simple_alu_shift" to
	"extend".  Split "alu_shift" into "shift" and "arlo_shift".  Split
	"alu_shift_reg" into "shift_reg" and "arlo_shift_reg".  List types
	in alphabetical order.
	(attribute "core_cycles"): Update for attribute changes.
	(arm_addsi3): Likewise.
	(addsi3_compare0): Likewise.
	(addsi3_compare0_scratch): Likewise.
	(addsi3_compare_op1): Likewise.
	(addsi3_compare_op2): Likewise.
	(compare_addsi2_op0): Likewise.
	(compare_addsi2_op1): Likewise.
	(addsi3_carryin_shift_<optab>): Likewise.
	(subsi3_carryin_shift): Likewise.
	(rsbsi3_carryin_shift): Likewise.
	(arm_subsi3_insn): Likewise.
	(subsi3_compare0): Likewise.
	(subsi3_compare): Likewise.
	(arm_andsi3_insn): Likewise.
	(thumb1_andsi3_insn): Likewise.
	(andsi3_compare0): Likewise.
	(andsi3_compare0_scratch): Likewise.
	(zeroextractsi_compare0_scratch
	(andsi_not_shiftsi_si): Likewise.
	(iorsi3_insn): Likewise.
	(iorsi3_compare0): Likewise.
	(iorsi3_compare0_scratch): Likewise.
	(arm_xorsi3): Likewise.
	(thumb1_xorsi3_insn): Likewise.
	(xorsi3_compare0): Likewise.
	(xorsi3_compare0_scratch): Likewise.
	(satsi_<SAT:code>_shift): Likewise.
	(rrx): Likewise.
	(arm_shiftsi3): Likewise.
	(shiftsi3_compare0): Likewise.
	(not_shiftsi): Likewise.
	(not_shiftsi_compare0): Likewise.
	(not_shiftsi_compare0_scratch): Likewise.
	(arm_one_cmplsi2): Likewise.
	(thumb_one_complsi2): Likewise.
	(notsi_compare0): Likewise.
	(notsi_compare0_scratch): Likewise.
	(thumb1_zero_extendhisi2): Likewise.
	(arm_zero_extendhisi2): Likewise.
	(arm_zero_extendhisi2_v6): Likewise.
	(arm_zero_extendhisi2addsi): Likewise.
	(thumb1_zero_extendqisi2): Likewise.
	(thumb1_zero_extendqisi2_v6): Likewise.
	(arm_zero_extendqisi2): Likewise.
	(arm_zero_extendqisi2_v6): Likewise.
	(arm_zero_extendqisi2addsi): Likewise.
	(thumb1_extendhisi2): Likewise.
	(arm_extendhisi2): Likewise.
	(arm_extendhisi2_v6): Likewise.
	(arm_extendqisi): Likewise.
	(arm_extendqisi_v6): Likewise.
	(arm_extendqisi2addsi): Likewise.
	(thumb1_extendqisi2): Likewise.
	(thumb1_movdi_insn): Likewise.
	(arm_movsi_insn): Likewise.
	(movsi_compare0): Likewise.
	(movhi_insn_arch4): Likewise.
	(movhi_bytes): Likewise.
	(arm_movqi_insn): Likewise.
	(thumb1_movqi_insn): Likewise.
	(arm32_movhf): Likewise.
	(thumb1_movhf): Likewise.
	(arm_movsf_soft_insn): Likewise.
	(thumb1_movsf_insn): Likewise.
	(movdf_soft_insn): Likewise.
	(thumb_movdf_insn): Likewise.
	(arm_cmpsi_insn): Likewise.
	(cmpsi_shiftsi): Likewise.
	(cmpsi_shiftsi_swp): Likewise.
	(arm_cmpsi_negshiftsi_si): Likewise.
	(movsicc_insn): Likewise.
	(movsfcc_soft_insn): Likewise.
	(arith_shiftsi): Likewise.
	(arith_shiftsi_compare0
	(arith_shiftsi_compare0_scratch
	(sub_shiftsi): Likewise.
	(sub_shiftsi_compare0
	(sub_shiftsi_compare0_scratch
	(and_scc): Likewise.
	(cond_move): Likewise.
	(if_plus_move): Likewise.
	(if_move_plus): Likewise.
	(if_move_not): Likewise.
	(if_not_move): Likewise.
	(if_shift_move): Likewise.
	(if_move_shift): Likewise.
	(if_shift_shift): Likewise.
	(if_not_arith): Likewise.
	(if_arith_not): Likewise.
	(cond_move_not): Likewise.
	(thumb1_ashlsi3): Set type attribute.
	(thumb1_ashrsi3): Likewise.
	(thumb1_lshrsi3): Likewise.
	(thumb1_rotrsi3): Likewise.
	(shiftsi3_compare0_scratch): Likewise.
	* config/arm/neon.md (neon_mov<mode>): Update for attribute changes.
	(neon_mov<mode>): Likewise.
	* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute
	changes.
	(thumb2_movsi_insn): Likewise.
	(thumb2_cmpsi_neg_shiftsi): Likewise.
	(thumb2_extendqisi_v6): Likewise.
	(thumb2_zero_extendhisi2_v6): Likewise.
	(thumb2_zero_extendqisi2_v6): Likewise.
	(thumb2_shiftsi3_short): Likewise.
	(thumb2_addsi3_compare0_scratch): Likewise.
	(orsi_not_shiftsi_si): Likewise.
	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
	* config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute
	changes.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute
	changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute
	changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	(cortex_a8_mov): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md (526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md (626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md (726te_shift_op): Update for attribute changes.
	(726te_alu_op): Likewise.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes.
	(pj4_alu_e1_conds): Likewise.
	(pj4_alu): Likewise.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes.
	(cortexa7_older_only): Likewise.
	(cortexa7_younger): Likewise.

	2013-07-18  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr",
	"xtab" and "sat".  Move value "clz" from here to ...
	(attriubte "type"): ... here.
	(satsi_<SAT:code>): Delete "insn" attribute.
	(satsi_<SAT:code>_shift): Likewise.
	(arm_zero_extendqisi2addsi): Likewise.
	(arm_extendqisi2addsi): Likewise.
	(clzsi2): Update for attribute changes.
	(rbitsi2): Likewise.
	* config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute.
	(arm_usatsihi): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change.

	2013-07-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/predicates.md (shiftable_operator_strict_it):
	New predicate.
	* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si):
	Disable cond_exec version for arm_restrict_it.
	(thumb2_smaxsi3): Convert to generate cond_exec.
	(thumb2_sminsi3): Likewise.
	(thumb32_umaxsi3): Likewise.
	(thumb2_uminsi3): Likewise.
	(thumb2_abssi2): Adjust constraints for arm_restrict_it.
	(thumb2_neg_abssi2): Likewise.
	(thumb2_mov_scc): Add alternative for 16-bit encoding.
	(thumb2_movsicc_insn): Adjust alternatives.
	(thumb2_mov_negscc): Disable for arm_restrict_it.
	(thumb2_mov_negscc_strict_it): New pattern.
	(thumb2_mov_notscc_strict_it): New pattern.
	(thumb2_mov_notscc): Disable for arm_restrict_it.
	(thumb2_ior_scc): Likewise.
	(thumb2_ior_scc_strict_it): New pattern.
	(thumb2_cond_move): Adjust for arm_restrict_it.
	(thumb2_cond_arith): Disable for arm_restrict_it.
	(thumb2_cond_arith_strict_it): New pattern.
	(thumb2_cond_sub): Adjust for arm_restrict_it.
	(thumb2_movcond): Likewise.
	(thumb2_extendqisi_v6): Disable cond_exec variant for arm_restrict_it.
	(thumb2_zero_extendhisi2_v6): Likewise.
	(thumb2_zero_extendqisi2_v6): Likewise.
	(orsi_notsi_si): Likewise.
	(orsi_not_shiftsi_si): Likewise.

	2013-07-22  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/arm.md (attribute "insn"): Delete.
	(attribute "type"): Add "mov_imm", "mov_reg", "mov_shift",
	"mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg".
	(not_shiftsi): Update for attribute change.
	(not_shiftsi_compare0): Likewise.
	(not_shiftsi_compare0_scratch): Likewise.
	(arm_one_cmplsi2): Likewise.
	(thumb1_one_cmplsi2): Likewise.
	(notsi_compare0): Likewise.
	(notsi_compare0_scratch): Likewise.
	(thumb1_movdi_insn): Likewise.
	(arm_movsi_insn): Likewise.
	(movhi_insn_arch4): Likewise.
	(movhi_bytes): Likewise.
	(arm_movqi_insn): Likewise.
	(thumb1_movqi_insn): Likewise.
	(arm32_movhf): Likewise.
	(thumb1_movhf): Likewise.
	(arm_movsf_soft_insn): Likewise.
	(thumb1_movsf_insn): Likewise.
	(thumb_movdf_insn): Likewise.
	(movsicc_insn): Likewise.
	(movsfcc_soft_insn): Likewise.
	(and_scc): Likewise.
	(cond_move): Likewise.
	(if_move_not): Likewise.
	(if_not_move): Likewise.
	(if_shift_move): Likewise.
	(if_move_shift): Likewise.
	(if_shift_shift): Likewise.
	(if_not_arith): Likewise.
	(if_arith_not): Likewise.
	(cond_move_not): Likewise.
	* config/arm/neon.md (neon_mov<mode>): Update for attribute change.
	(neon_mov<mode>): Likewise.
	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute change.
	(thumb2_movsi_vfp): Likewise.
	(movsf_vfp): Likewise.
	(thumb2_movsf_vfp): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change.
	(cortexa7_older_only): Likewise.
	(cortexa7_younger): Likewise.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute change.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute change.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for attribute change.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute change.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	(cortex_a8_mov): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change.
	* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md (526_alu_op): Update for attribute change.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Update for attribute change.
	* config/arm/fa626te.md (626te_alu_op): Update for attribute change.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md (726te_shift_op): Update for attribute change.
	(726te_alu_op): Likewise.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute change.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change.
	(pj4_alu_e1_conds): Likewise.
	(pj4_alu): Likewise.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.

	2013-07-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/constraints.md (Pd): Allow TARGET_THUMB
	instead of TARGET_THUMB1.
	(Pz): New constraint.
	* config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit
	encodings.
	(compare_negsi_si): Likewise.
	(compare_addsi2_op0): Likewise.
	(compare_addsi2_op1): Likewise.
	(addsi3_carryin_<optab>): Likewise.
	(addsi3_carryin_alt2_<optab>): Likewise.
	(addsi3_carryin_shift_<optab>): Disable cond_exec variant
	for arm_restrict_it.
	(subsi3_carryin): Likewise.
	(arm_subsi3_insn): Add alternatives for 16-bit encoding.
	(minmax_arithsi): Disable for arm_restrict_it.
	(minmax_arithsi_non_canon): Adjust for arm_restrict_it.
	(satsi_<SAT:code>): Disable cond_exec variant for arm_restrict_it.
	(satsi_<SAT:code>_shift): Likewise.
	(arm_shiftsi3): Add alternative for 16-bit encoding.
	(arm32_movhf): Disable for arm_restrict_it.
	(arm_cmpdi_unsigned): Add alternatives for 16-bit encoding.
	(arm_movtas_ze): Disable cond_exec variant for arm_restrict_it.

2013-09-09  Kugan Vivekanandarajah  <kuganv@linaro.org>

	Backport from trunk r201412.
	2013-08-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (minmax_arithsi_non_canon): Emit canonical RTL form
	when subtracting a constant.

2013-09-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r201249.
	2013-07-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-fixed.md (ssmulsa3, usmulusa3):
	Adjust for arm_restrict_it.
	Remove trailing whitespace.

2013-09-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r201342.
	2013-07-30  Richard Earnshaw  <rearnsha@arm.com>

	* config.gcc (arm): Require 64-bit host-wide-int for all ARM target
	configs.

2013-09-05  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r199527,199792,199814.
	2013-05-31  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/56315
	* config/arm/arm.c (const_ok_for_dimode_op): Handle IOR.
	* config/arm/arm.md (*iordi3_insn): Change to insn_and_split.
	* config/arm/neon.md (iordi3_neon): Remove.
	(neon_vorr<mode>): Generate iordi3 instead of iordi3_neon.
	* config/arm/predicates.md (imm_for_neon_logic_operand):
	Move to earlier in the file.
	(neon_logic_op2): Likewise.
	(arm_iordi_operand_neon): New predicate.

	2013-06-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/constraints.md (Df): New constraint.
	* config/arm/arm.md (iordi3_insn): Use Df constraint instead of De.
	Correct length attribute for last two alternatives.

	2013-06-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/56315
	* config/arm/arm.md (*xordi3_insn): Change to insn_and_split.
	(xordi3): Change operand 2 constraint to arm_xordi_operand.
	* config/arm/arm.c (const_ok_for_dimode_op): Handle XOR.
	* config/arm/constraints.md (Dg): New constraint.
	* config/arm/neon.md (xordi3_neon): Remove.
	(neon_veor<mode>): Generate xordi3 instead of xordi3_neon.
	* config/arm/predicates.md (arm_xordi_operand): New predicate.

2013-09-05  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201599.
	2013-08-08  Richard Earnshaw  <rearnsha@arm.com>

	PR target/57431
	* arm/neon.md (neon_vld1_dupdi): New expand pattern.
	(neon_vld1_dup<mode> VD iterator): Iterate over VD not VDX.

2013-09-05  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201589.
	2013-08-08  Bernd Edlinger  <bernd.edlinger@hotmail.de>

	PR target/58065
	* config/arm/arm.h (MALLOC_ABI_ALIGNMENT): Define.

2013-09-03  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>

	Backport from trunk
	r201624, r201666.
	2013-08-09  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd-builtins.def (get_lane_signed): Remove.
	(get_lane_unsigned): Likewise.
	(dup_lane_scalar): Likewise.
	(get_lane): enable for VALL.
	* config/aarch64/aarch64-simd.md
	(aarch64_dup_lane_scalar<mode>): Remove.
	(aarch64_get_lane_signed<mode>): Likewise.
	(aarch64_get_lane_unsigned<mode>): Likewise.
	(aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): New.
	(aarch64_get_lane_zero_extendsi<mode>): Likewise.
	(aarch64_get_lane<mode>): Enable for all vector modes.
	(aarch64_get_lanedi): Remove misleading constraints.
	* config/aarch64/arm_neon.h
	(__aarch64_vget_lane_any): Define.
	(__aarch64_vget<q>_lane_<fpsu><8,16,32,64>): Likewise.
	(vget<q>_lane_<fpsu><8,16,32,64>): Use __aarch64_vget_lane macros.
	(vdup<bhsd>_lane_<su><8,16,32,64>): Likewise.
	 * config/aarch64/iterators.md (VDQQH): New.
	(VDQQHS): Likewise.
	(vwcore): Likewise.

	2013-08-12  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/arm_none.h
	(vdup<bhsd>_lane_<su><8,16,32,64>): Fix macro call.

2013-08-26  Kugan Vivekanandarajah  <kuganv@linaro.org>

	Backport from trunk r201341.
	2013-07-30  Richard Earnshaw  <rearnsha@arm.com>

	* arm.md (mulhi3): New expand pattern.

2013-08-16  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2013-08-14  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2013.08 released.
	* LINARO-VERSION: Update.

2013-08-08  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk
	r198489,200167,200199,200510,200513,200515,200576.
	2013-05-01  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/thumb2.md (thumb2_smaxsi3,thumb2_sminsi3): Convert
	define_insn to define_insn_and_split.
	(thumb32_umaxsi3,thumb2_uminsi3): Likewise.
	(thumb2_negdi2,thumb2_abssi2,thumb2_neg_abssi2): Likewise.
	(thumb2_mov_scc,thumb2_mov_negscc,thumb2_mov_notscc): Likewise.
	(thumb2_movsicc_insn,thumb2_and_scc,thumb2_ior_scc): Likewise.
	(thumb2_negscc): Likewise.

	2013-06-18  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/arm.md (attribute "insn"): Move multiplication and division
	attributes to...
	(attribute "type"): ... here.  Remove mult.
	(attribute "mul32"): New attribute.
	(attribute "mul64"): Add umaal.
	(*arm_mulsi3): Update attributes.
	(*arm_mulsi3_v6): Likewise.
	(*thumb_mulsi3): Likewise.
	(*thumb_mulsi3_v6): Likewise.
	(*mulsi3_compare0): Likewise.
	(*mulsi3_compare0_v6): Likewise.
	(*mulsi_compare0_scratch): Likewise.
	(*mulsi_compare0_scratch_v6): Likewise.
	(*mulsi3addsi): Likewise.
	(*mulsi3addsi_v6): Likewise.
	(*mulsi3addsi_compare0): Likewise.
	(*mulsi3addsi_compare0_v6): Likewise.
	(*mulsi3addsi_compare0_scratch): Likewise.
	(*mulsi3addsi_compare0_scratch_v6): Likewise.
	(*mulsi3subsi): Likewise.
	(*mulsidi3adddi): Likewise.
	(*mulsi3addsi_v6): Likewise.
	(*mulsidi3adddi_v6): Likewise.
	(*mulsidi3_nov6): Likewise.
	(*mulsidi3_v6): Likewise.
	(*umulsidi3_nov6): Likewise.
	(*umulsidi3_v6): Likewise.
	(*umulsidi3adddi): Likewise.
	(*umulsidi3adddi_v6): Likewise.
	(*smulsi3_highpart_nov6): Likewise.
	(*smulsi3_highpart_v6): Likewise.
	(*umulsi3_highpart_nov6): Likewise.
	(*umulsi3_highpart_v6): Likewise.
	(mulhisi3): Likewise.
	(*mulhisi3tb): Likewise.
	(*mulhisi3bt): Likewise.
	(*mulhisi3tt): Likewise.
	(maddhisi4): Likewise.
	(*maddhisi4tb): Likewise.
	(*maddhisi4tt): Likewise.
	(maddhidi4): Likewise.
	(*maddhidi4tb): Likewise.
	(*maddhidi4tt): Likewise.
	(divsi3): Likewise.
	(udivsi3): Likewise.
	* config/arm/thumb2.md (thumb2_mulsi_short): Update attributes.
	(thumb2_mulsi_short_compare0): Likewise.
	(thumb2_mulsi_short_compare0_scratch): Likewise.
	* config/arm/arm1020e.md (1020mult1): Update attribute change.
	(1020mult2): Likewise.
	(1020mult3): Likewise.
	(1020mult4): Likewise.
	(1020mult5): Likewise.
	(1020mult6): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_mult32): Update attribute change.
	(cortex_a15_mult64): Likewise.
	(cortex_a15_sdiv): Likewise.
	(cortex_a15_udiv): Likewise.
	* config/arm/arm1026ejs.md (mult1): Update attribute change.
	(mult2): Likewise.
	(mult3): Likewise.
	(mult4): Likewise.
	(mult5): Likewise.
	(mult6): Likewise.
	* config/arm/marvell-pj4.md (pj4_ir_mul): Update attribute change.
	(pj4_ir_div): Likewise.
	* config/arm/arm1136jfs.md (11_mult1): Update attribute change.
	(11_mult2): Likewise.
	(11_mult3): Likewise.
	(11_mult4): Likewise.
	(11_mult5): Likewise.
	(11_mult6): Likewise.
	(11_mult7): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_mul): Update attribute change.
	(cortex_a8_mla): Likewise.
	(cortex_a8_mull): Likewise.
	(cortex_a8_smulwy): Likewise.
	(cortex_a8_smlald): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update attribute change.
	* config/arm/cortex-r4.md (cortex_r4_mul_4): Update attribute change.
	(cortex_r4_mul_3): Likewise.
	(cortex_r4_mla_4): Likewise.
	(cortex_r4_mla_3): Likewise.
	(cortex_r4_smlald): Likewise.
	(cortex_r4_mull): Likewise.
	(cortex_r4_sdiv): Likewise.
	(cortex_r4_udiv): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_mul): Update attribute change.
	(cortex_a7_idiv): Likewise.
	* config/arm/arm926ejs.md (9_mult1): Update attribute change.
	(9_mult2): Likewise.
	(9_mult3): Likewise.
	(9_mult4): Likewise.
	(9_mult5): Likewise.
	(9_mult6): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_mul): Update attribute change.
	(cortex_a53_sdiv): Likewise.
	(cortex_a53_udiv): Likewise.
	* config/arm/fa726te.md (726te_mult_op): Update attribute change.
	* config/arm/fmp626.md (mp626_mult1): Update attribute change.
	(mp626_mult2): Likewise.
	(mp626_mult3): Likewise.
	(mp626_mult4): Likewise.
	* config/arm/fa526.md (526_mult1): Update attribute change.
	(526_mult2): Likewise.
	* config/arm/arm-generic.md (mult): Update attribute change.
	(mult_ldsched_strongarm): Likewise.
	(mult_ldsched): Likewise.
	(multi_cycle): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_mul): Update attribute change.
	* config/arm/fa606te.md (606te_mult1): Update attribute change.
	(606te_mult2): Likewise.
	(606te_mult3): Likewise.
	(606te_mult4): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_mult16): Update attribute change.
	(cortex_a9_mac16): Likewise.
	(cortex_a9_multiply): Likewise.
	(cortex_a9_mac): Likewise.
	(cortex_a9_multiply_long): Likewise.
	* config/arm/fa626te.md (626te_mult1): Update attribute change.
	(626te_mult2): Likewise.
	(626te_mult3): Likewise.
	(626te_mult4): Likewise.

	2013-06-19  Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/vfp.md: Move VFP instruction classification documentation
	to ...
	* config/arm/arm.md: ... here.  Update instruction classification
	documentation.

	2013-06-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/predicates.md (arm_cond_move_operator): New predicate.
	* config/arm/arm.md (movsfcc): Use arm_cond_move_operator predicate.
	(movdfcc): Likewise.
	* config/arm/vfp.md (*thumb2_movsf_vfp):
	Disable predication for arm_restrict_it.
	(*thumb2_movsfcc_vfp): Disable for arm_restrict_it.
	(*thumb2_movdfcc_vfp): Likewise.
	(*abssf2_vfp, *absdf2_vfp, *negsf2_vfp, *negdf2_vfp,*addsf3_vfp,
	*adddf3_vfp, *subsf3_vfp, *subdf3_vfpc, *divsf3_vfp,*divdf3_vfp,
	*mulsf3_vfp, *muldf3_vfp, *mulsf3negsf_vfp, *muldf3negdf_vfp,
	*mulsf3addsf_vfp, *muldf3adddf_vfp, *mulsf3subsf_vfp,
	*muldf3subdf_vfp, *mulsf3negsfaddsf_vfp, *fmuldf3negdfadddf_vfp,
	*mulsf3negsfsubsf_vfp, *muldf3negdfsubdf_vfp, *fma<SDF:mode>4,
	*fmsub<SDF:mode>4, *fnmsub<SDF:mode>4, *fnmadd<SDF:mode>4,
	*extendsfdf2_vfp, *truncdfsf2_vfp, *extendhfsf2, *truncsfhf2,
	*truncsisf2_vfp, *truncsidf2_vfp, fixuns_truncsfsi2, fixuns_truncdfsi2,
	*floatsisf2_vfp, *floatsidf2_vfp, floatunssisf2, floatunssidf2,
	*sqrtsf2_vfp, *sqrtdf2_vfp, *cmpsf_vfp, *cmpsf_trap_vfp, *cmpdf_vfp,
	*cmpdf_trap_vfp, <vrint_pattern><SDF:mode>2):
	Disable predication for arm_restrict_it.

	2013-06-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_mulsi3_v6): Add alternative for 16-bit
	encoding.
	(mulsi3addsi_v6): Disable predicable variant for arm_restrict_it.
	(mulsi3subsi): Likewise.
	(mulsidi3adddi): Likewise.
	(mulsidi3_v6): Likewise.
	(umulsidi3_v6): Likewise.
	(umulsidi3adddi_v6): Likewise.
	(smulsi3_highpart_v6): Likewise.
	(umulsi3_highpart_v6): Likewise.
	(mulhisi3tb): Likewise.
	(mulhisi3bt): Likewise.
	(mulhisi3tt): Likewise.
	(maddhisi4): Likewise.
	(maddhisi4tb): Likewise.
	(maddhisi4tt): Likewise.
	(maddhidi4): Likewise.
	(maddhidi4tb): Likewise.
	(maddhidi4tt): Likewise.
	(zeroextractsi_compare0_scratch): Likewise.
	(insv_zero): Likewise.
	(insv_t2): Likewise.
	(anddi_notzesidi_di): Likewise.
	(anddi_notsesidi_di): Likewise.
	(andsi_notsi_si): Likewise.
	(iordi_zesidi_di): Likewise.
	(xordi_zesidi_di): Likewise.
	(andsi_iorsi3_notsi): Likewise.
	(smax_0): Likewise.
	(smax_m1): Likewise.
	(smin_0): Likewise.
	(not_shiftsi): Likewise.
	(unaligned_loadsi): Likewise.
	(unaligned_loadhis): Likewise.
	(unaligned_loadhiu): Likewise.
	(unaligned_storesi): Likewise.
	(unaligned_storehi): Likewise.
	(extv_reg): Likewise.
	(extzv_t2): Likewise.
	(divsi3): Likewise.
	(udivsi3): Likewise.
	(arm_zero_extendhisi2addsi): Likewise.
	(arm_zero_extendqisi2addsi): Likewise.
	(compareqi_eq0): Likewise.
	(arm_extendhisi2_v6): Likewise.
	(arm_extendqisi2addsi): Likewise.
	(arm_movt): Likewise.
	(thumb2_ldrd): Likewise.
	(thumb2_ldrd_base): Likewise.
	(thumb2_ldrd_base_neg): Likewise.
	(thumb2_strd): Likewise.
	(thumb2_strd_base): Likewise.
	(thumb2_strd_base_neg): Likewise.
	(arm_negsi2): Add alternative for 16-bit encoding.
	(arm_one_cmplsi2): Likewise.

	2013-06-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/constraints.md (Ts): New constraint.
	* config/arm/arm.md (arm_movqi_insn): Add alternatives for
	16-bit encodings.
	(compare_scc): Use "Ts" constraint for operand 0.
	(ior_scc_scc): Likewise.
	(and_scc_scc): Likewise.
	(and_scc_scc_nodom): Likewise.
	(ior_scc_scc_cmp): Likewise for operand 7.
	(and_scc_scc_cmp): Likewise.
	* config/arm/thumb2.md (thumb2_movsi_insn):
	Add alternatives for 16-bit encodings.
	(thumb2_movhi_insn): Likewise.
	(thumb2_movsicc_insn): Likewise.
	(thumb2_and_scc): Take 'and' outside cond_exec.  Use "Ts" constraint.
	(thumb2_negscc): Use "Ts" constraint.
	Move mvn instruction outside cond_exec block.
	* config/arm/vfp.md (thumb2_movsi_vfp): Add alternatives
	for 16-bit encodings.

	2013-07-01  Sofiane Naci  <sofiane.naci@arm.com>

	* arm.md (attribute "wtype"): Delete.  Move attribute values from here
	to ...
	(attribute "type"): ... here, and prefix with "wmmx_".
	(attribute "core_cycles"): Update for attribute changes.
	* iwmmxt.md (tbcstv8qi): Update for attribute changes.
	(tbcstv4hi): Likewise.
	(tbcstv2si): Likewise.
	(iwmmxt_iordi3): Likewise.
	(iwmmxt_xordi3): Likewise.
	(iwmmxt_anddi3): Likewise.
	(iwmmxt_nanddi3): Likewise.
	(iwmmxt_arm_movdi): Likewise.
	(iwmmxt_movsi_insn): Likewise.
	(mov<mode>_internal): Likewise.
	(and<mode>3_iwmmxt): Likewise.
	(ior<mode>3_iwmmxt): Likewise.
	(xor<mode>3_iwmmxt): Likewise.
	(add<mode>3_iwmmxt): Likewise.
	(ssaddv8qi3): Likewise.
	(ssaddv4hi3): Likewise.
	(ssaddv2si3): Likewise.
	(usaddv8qi3): Likewise.
	(usaddv4hi3): Likewise.
	(usaddv2si3): Likewise.
	(sub<mode>3_iwmmxt): Likewise.
	(sssubv8qi3): Likewise.
	(sssubv4hi3): Likewise.
	(sssubv2si3): Likewise.
	(ussubv8qi3): Likewise.
	(ussubv4hi3): Likewise.
	(ussubv2si3): Likewise.
	(mulv4hi3_iwmmxt): Likewise.
	(smulv4hi3_highpart): Likewise.
	(umulv4hi3_highpart): Likewise.
	(iwmmxt_wmacs): Likewise.
	(iwmmxt_wmacsz): Likewise.
	(iwmmxt_wmacu): Likewise.
	(iwmmxt_wmacuz): Likewise.
	(iwmmxt_clrdi): Likewise.
	(iwmmxt_clrv8qi): Likewise.
	(iwmmxt_clr4hi): Likewise.
	(iwmmxt_clr2si): Likewise.
	(iwmmxt_uavgrndv8qi3): Likewise.
	(iwmmxt_uavgrndv4hi3): Likewise.
	(iwmmxt_uavgv8qi3): Likewise.
	(iwmmxt_uavgv4hi3): Likewise.
	(iwmmxt_tinsrb): Likewise.
	(iwmmxt_tinsrh): Likewise.
	(iwmmxt_tinsrw): Likewise.
	(iwmmxt_textrmub): Likewise.
	(iwmmxt_textrmsb): Likewise.
	(iwmmxt_textrmuh): Likewise.
	(iwmmxt_textrmsh): Likewise.
	(iwmmxt_textrmw): Likewise.
	(iwmxxt_wshufh): Likewise.
	(eqv8qi3): Likewise.
	(eqv4hi3): Likewise.
	(eqv2si3): Likewise.
	(gtuv8qi3): Likewise.
	(gtuv4hi3): Likewise.
	(gtuv2si3): Likewise.
	(gtv8qi3): Likewise.
	(gtv4hi3): Likewise.
	(gtv2si3): Likewise.
	(smax<mode>3_iwmmxt): Likewise.
	(umax<mode>3_iwmmxt): Likewise.
	(smin<mode>3_iwmmxt): Likewise.
	(umin<mode>3_iwmmxt): Likewise.
	(iwmmxt_wpackhss): Likewise.
	(iwmmxt_wpackwss): Likewise.
	(iwmmxt_wpackdss): Likewise.
	(iwmmxt_wpackhus): Likewise.
	(iwmmxt_wpackwus): Likewise.
	(iwmmxt_wpackdus): Likewise.
	(iwmmxt_wunpckihb): Likewise.
	(iwmmxt_wunpckihh): Likewise.
	(iwmmxt_wunpckihw): Likewise.
	(iwmmxt_wunpckilb): Likewise.
	(iwmmxt_wunpckilh): Likewise.
	(iwmmxt_wunpckilw): Likewise.
	(iwmmxt_wunpckehub): Likewise.
	(iwmmxt_wunpckehuh): Likewise.
	(iwmmxt_wunpckehuw): Likewise.
	(iwmmxt_wunpckehsb): Likewise.
	(iwmmxt_wunpckehsh): Likewise.
	(iwmmxt_wunpckehsw): Likewise.
	(iwmmxt_wunpckelub): Likewise.
	(iwmmxt_wunpckeluh): Likewise.
	(iwmmxt_wunpckeluw): Likewise.
	(iwmmxt_wunpckelsb): Likewise.
	(iwmmxt_wunpckelsh): Likewise.
	(iwmmxt_wunpckelsw): Likewise.
	(ror<mode>3): Likewise.
	(ashr<mode>3_iwmmxt): Likewise.
	(lshr<mode>3_iwmmxt): Likewise.
	(ashl<mode>3_iwmmxt): Likewise.
	(ror<mode>3_di): Likewise.
	(ashr<mode>3_di): Likewise.
	(lshr<mode>3_di): Likewise.
	(ashl<mode>3_di): Likewise.
	(iwmmxt_wmadds): Likewise.
	(iwmmxt_wmaddu): Likewise.
	(iwmmxt_tmia): Likewise.
	(iwmmxt_tmiaph): Likewise.
	(iwmmxt_tmiabb): Likewise.
	(iwmmxt_tmiatb): Likewise.
	(iwmmxt_tmiabt): Likewise.
	(iwmmxt_tmiatt): Likewise.
	(iwmmxt_tmovmskb): Likewise.
	(iwmmxt_tmovmskh): Likewise.
	(iwmmxt_tmovmskw): Likewise.
	(iwmmxt_waccb): Likewise.
	(iwmmxt_wacch): Likewise.
	(iwmmxt_waccw): Likewise.
	(iwmmxt_waligni): Likewise.
	(iwmmxt_walignr): Likewise.
	(iwmmxt_walignr0): Likewise.
	(iwmmxt_walignr1): Likewise.
	(iwmmxt_walignr2): Likewise.
	(iwmmxt_walignr3): Likewise.
	(iwmmxt_wsadb): Likewise.
	(iwmmxt_wsadh): Likewise.
	(iwmmxt_wsadbz): Likewise.
	(iwmmxt_wsadhz): Likewise.
	* iwmmxt2.md (iwmmxt_wabs<mode>3): Update for attribute changes.
	(iwmmxt_wabsdiffb): Likewise.
	(iwmmxt_wabsdiffh): Likewise.
	(iwmmxt_wabsdiffw): Likewise.
	(iwmmxt_waddsubhx): Likewise
	(iwmmxt_wsubaddhx): Likewise.
	(addc<mode>3): Likewise.
	(iwmmxt_avg4): Likewise.
	(iwmmxt_avg4r): Likewise.
	(iwmmxt_wmaddsx): Likewise.
	(iwmmxt_wmaddux): Likewise.
	(iwmmxt_wmaddsn): Likewise.
	(iwmmxt_wmaddun): Likewise.
	(iwmmxt_wmulwsm): Likewise.
	(iwmmxt_wmulwum): Likewise.
	(iwmmxt_wmulsmr): Likewise.
	(iwmmxt_wmulumr): Likewise.
	(iwmmxt_wmulwsmr): Likewise.
	(iwmmxt_wmulwumr): Likewise.
	(iwmmxt_wmulwl): Likewise.
	(iwmmxt_wqmulm): Likewise.
	(iwmmxt_wqmulwm): Likewise.
	(iwmmxt_wqmulmr): Likewise.
	(iwmmxt_wqmulwmr): Likewise.
	(iwmmxt_waddbhusm): Likewise.
	(iwmmxt_waddbhusl): Likewise.
	(iwmmxt_wqmiabb): Likewise.
	(iwmmxt_wqmiabt): Likewise.
	(iwmmxt_wqmiatb): Likewise.
	(iwmmxt_wqmiatt): Likewise.
	(iwmmxt_wqmiabbn): Likewise.
	(iwmmxt_wqmiabtn): Likewise.
	(iwmmxt_wqmiatbn): Likewise.
	(iwmmxt_wqmiattn): Likewise.
	(iwmmxt_wmiabb): Likewise.
	(iwmmxt_wmiabt): Likewise.
	(iwmmxt_wmiatb): Likewise.
	(iwmmxt_wmiatt): Likewise.
	(iwmmxt_wmiabbn): Likewise.
	(iwmmxt_wmiabtn): Likewise.
	(iwmmxt_wmiatbn): Likewise.
	(iwmmxt_wmiattn): Likewise.
	(iwmmxt_wmiawbb): Likewise.
	(iwmmxt_wmiawbt): Likewise.
	(iwmmxt_wmiawtb): Likewise.
	(iwmmxt_wmiawtt): Likewise.
	(iwmmxt_wmiawbbn): Likewise.
	(iwmmxt_wmiawbtn): Likewise.
	(iwmmxt_wmiawtbn): Likewise.
	(iwmmxt_wmiawttn): Likewise.
	(iwmmxt_wmerge): Likewise.
	(iwmmxt_tandc<mode>3): Likewise.
	(iwmmxt_torc<mode>3): Likewise.
	(iwmmxt_torvsc<mode>3): Likewise.
	(iwmmxt_textrc<mode>3): Likewise.
	* marvell-f-iwmmxt.md (wmmxt_shift): Update for attribute changes.
	(wmmxt_pack): Likewise.
	(wmmxt_mult_c1): Likewise.
	(wmmxt_mult_c2): Likewise.
	(wmmxt_alu_c1): Likewise.
	(wmmxt_alu_c2): Likewise.
	(wmmxt_alu_c3): Likewise.
	(wmmxt_transfer_c1): Likewise.
	(wmmxt_transfer_c2): Likewise.
	(wmmxt_transfer_c3): Likewise.
	(marvell_f_iwmmxt_wstr): Likewise.
	(marvell_f_iwmmxt_wldr): Likewise.

2013-08-07  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r201237.
	2013-07-25  Terry Guo  <terry.guo@arm.com>

	* config/arm/arm.c (thumb1_size_rtx_costs): Assign proper cost for
	shift_add/shift_sub0/shift_sub1 RTXs.

2013-08-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r200596,201067,201083.
	2013-07-02  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64-simd.md (absdi2): Support abs for
	DI mode.

	2013-07-19  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/arm_neon.h (vabs_s64): New function

	2013-07-20  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_fold_builtin): Fold abs in all modes.
	* config/aarch64/aarch64-simd-builtins.def
	(abs): Enable for all modes.
	* config/aarch64/arm_neon.h
	(vabs<q>_s<8,16,32,64): Rewrite using builtins.
	(vabs_f64): Add missing intrinsic.

2013-08-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198735,198831,199959.
	2013-05-09  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64.md: New movtf split.
	(*movtf_aarch64): Update.
	(aarch64_movdi_tilow): Handle TF modes and rename to
	aarch64_movdi_<mode>low.
	(aarch64_movdi_tihigh): Handle TF modes and rename to
	aarch64_movdi_<mode>high
	(aarch64_movtihigh_di): Handle TF modes and rename to
	aarch64_mov<mode>high_di
	(aarch64_movtilow_di): Handle TF modes and rename to
	aarch64_mov<mode>low_di
	(aarch64_movtilow_tilow): Remove spurious whitespace.
	* config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TFmode
	splits.
	(aarch64_print_operand): Update.

	2013-05-13  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_simd_mov<mode>): Group
	similar switch cases.
	(aarch64_simd_mov): Rename to aarch64_split_simd_mov. Update.
	(aarch64_simd_mov_to_<mode>low): Delete.
	(aarch64_simd_mov_to_<mode>high): Delete.
	(move_lo_quad_<mode>): Add w<-r alternative.
	(aarch64_simd_move_hi_quad_<mode>): Likewise.
	(aarch64_simd_mov_from_*): Update type attribute.
	* config/aarch64/aarch64.c (aarch64_split_simd_move): Refacror switch
	statement.

	2013-06-11  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>): Update.

2013-08-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r199438,199439,201326.

	2013-05-30  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added.
	(arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes.
	(arm_emit_vfp_multi_reg_pop): Likewise.
	(thumb2_emit_ldrd_pop): Likewise.
	(arm_expand_epilogue): Add misc REG_CFA notes.
	(arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE.

	2013-05-30  Bernd Schmidt  <bernds@codesourcery.com>
	    Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/arm/arm-protos.h: Add and update function protos.
	* config/arm/arm.c (use_simple_return_p): New added.
	(thumb2_expand_return): Check simple_return flag.
	* config/arm/arm.md: Add simple_return and conditional simple_return.
	* config/arm/iterators.md: Add iterator for return and simple_return.

	2013-07-30  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	PR rtl-optimization/57637
	* function.c (move_insn_for_shrink_wrap): Also check the
	GEN set of the LIVE problem for the liveness analysis
	if it exists, otherwise give up.

2013-08-06  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198928,198973,199203,201240,201241,201307.
	2013-05-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	* config/arm/predicates.md (call_insn_operand): New predicate.
	* config/arm/constraints.md ("Cs", "Ss"):  New constraints.
	* config/arm/arm.md (*call_insn, *call_value_insn): Match only
	if insn is not a tail call.
	(*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through
	registers.
	* config/arm/arm.h (enum reg_class): New caller save register class.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	* config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling
	without decls.

	2013-05-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	* config/arm/arm.c (arm_function_ok_for_sibcall): Add check
	for NULL decl.

	2013-05-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	PR target/57340
	* config/arm/arm.c (any_sibcall_uses_r3): Rename to ..
	(any_sibcall_could_use_r3): this and handle indirect calls.
	(arm_get_frame_offsets): Rename use of any_sibcall_uses_r3.

	2013-07-25  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	PR target/57731
	PR target/57748
	* config/arm/arm.md ("*sibcall_value_insn): Replace use of
	Ss with US. Adjust output for v5 and v4t.
	(*sibcall_value_insn): Likewise and loosen predicate on
	operand0.
	* config/arm/constraints.md ("Ss"): Rename to US.

	2013-07-25  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/arm.md (*sibcall_insn): Remove unnecessary space.

	2013-07-29  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
	Fix incorrect changelog entry.

	Replace
	PR target/57748
	with
	PR target/57837

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200922.
	2013-07-12  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-protos.h
	(aarch64_simd_immediate_valid_for_move): Remove.
	* config/aarch64/aarch64.c (simd_immediate_info): New member.
	(aarch64_simd_valid_immediate): Recognize idioms for shifting ones
	cases.
	(aarch64_output_simd_mov_immediate): Print the correct shift specifier.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200670.
	2013-07-04  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-protos.h (cpu_vector_cost): New.
	(tune_params): New member 'const vec_costs'.
	* config/aarch64/aarch64.c (generic_vector_cost): New.
	(generic_tunings): New member 'generic_vector_cost'.
	(aarch64_builtin_vectorization_cost): New.
	(aarch64_add_stmt_cost): New.
	(TARGET_VECTORIZE_ADD_STMT_COST): New.
	(TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200637.
	2013-07-03  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/aarch64.h (enum arm_abi_type): Remove.
	(ARM_ABI_AAPCS64): Ditto.
	(arm_abi): Ditto.
	(ARM_DEFAULT_ABI): Ditto.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200532, r200565.
	2013-06-28  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64.c (aarch64_cannot_force_const_mem): Adjust
	layout.

	2013-06-29  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/aarch64.c: Remove junk from the beginning of the
	file.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200531.
	2013-06-28  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64-protos.h (aarch64_symbol_type):
	Update comment w.r.t SYMBOL_TINY_ABSOLUTE.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200519.
	2013-06-28  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64-protos.h
	aarch64_classify_symbol_expression): Define.
	(aarch64_symbolic_constant_p): Remove.
	* config/aarch64/aarch64.c (aarch64_classify_symbol_expression): Remove
	static.  Fix line length and white space.
	(aarch64_symbolic_constant_p): Remove.
	* config/aarch64/predicates.md (aarch64_valid_symref):
	Use aarch64_classify_symbol_expression.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200466, r200467.
	2013-06-27  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/aarch64.c (aarch64_force_temporary): Add an extra
	parameter 'mode' of type 'enum machine_mode mode'; change to pass
	'mode' to force_reg.
	(aarch64_add_offset): Update calls to aarch64_force_temporary.
	(aarch64_expand_mov_immediate): Likewise.

	2013-06-27  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/aarch64.c (aarch64_add_offset): Change to pass
	'mode' to aarch64_plus_immediate and gen_rtx_PLUS.

2013-08-05  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r200419.
	2013-06-26  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.h (MAX_CONDITIONAL_EXECUTE): Define macro.
	* config/arm/arm-protos.h (arm_max_conditional_execute): New
	declaration.
	(tune_params): Update comment.
	* config/arm/arm.c (arm_cortex_a15_tune): Set max_cond_insns to 2.
	(arm_max_conditional_execute): New function.
	(thumb2_final_prescan_insn): Use max_insn_skipped and
	MAX_INSN_PER_IT_BLOCK to compute maximum instructions in a block.

2013-07-24  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	* LINARO-VERSION: Bump version.

2013-07-19  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	GCC Linaro 4.8-2013.07-1 released.
	* LINARO-VERSION: Update.

2013-07-19  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r201005.
	2013-07-17  Yvan Roux  <yvan.roux@linaro.org>

	PR target/57909
	* config/arm/arm.c (gen_movmem_ldrd_strd): Fix unaligned load/store
	usage in HI mode.

2013-07-09  Christophe Lyon  <christophe.lyon@linaro.org>

	* LINARO-VERSION: Bump version.

2013-07-05  Christophe Lyon  <christophe.lyon@linaro.org>

	GCC Linaro 4.8-2013.07 released.
	* LINARO-VERSION: Update.

2013-07-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Revert backport from trunk r198928,198973,199203.
	2013-05-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	PR target/57340
	* config/arm/arm.c (any_sibcall_uses_r3): Rename to ..
	(any_sibcall_could_use_r3): this and handle indirect calls.
	(arm_get_frame_offsets): Rename use of any_sibcall_uses_r3.

	2013-05-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	* config/arm/arm.c (arm_function_ok_for_sibcall): Add check
	for NULL decl.

	2013-05-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	* config/arm/predicates.md (call_insn_operand): New predicate.
	* config/arm/constraints.md ("Cs", "Ss"):  New constraints.
	* config/arm/arm.md (*call_insn, *call_value_insn): Match only
	if insn is not a tail call.
	(*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through
	registers.
	* config/arm/arm.h (enum reg_class): New caller save register class.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	* config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling
	without decls.

2013-07-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Revert backport from mainline (r199438, r199439)
	2013-05-30  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added.
	(arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes.
	(arm_emit_vfp_multi_reg_pop): Likewise.
	(thumb2_emit_ldrd_pop): Likewise.
	(arm_expand_epilogue): Add misc REG_CFA notes.
	(arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE.

	2013-05-30  Bernd Schmidt  <bernds@codesourcery.com>
		    Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/arm/arm-protos.h: Add and update function protos.
	* config/arm/arm.c (use_simple_return_p): New added.
	(thumb2_expand_return): Check simple_return flag.
	* config/arm/arm.md: Add simple_return and conditional simple_return.
	* config/arm/iterators.md: Add iterator for return and simple_return.
	* gcc.dg/shrink-wrap-alloca.c: New added.
	* gcc.dg/shrink-wrap-pretend.c: New added.
	* gcc.dg/shrink-wrap-sibcall.c: New added.

2013-07-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r199640, 199705, 199733, 199734, 199739.
	2013-06-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* rtl.def: Add extra fourth optional field to define_cond_exec.
	* gensupport.c (process_one_cond_exec): Process attributes from
	define_cond_exec.
	* doc/md.texi: Document fourth field in define_cond_exec.

	2013-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (enabled_for_depr_it): New attribute.
	(predicable_short_it): Likewise.
	(predicated): Likewise.
	(enabled): Handle above.
	(define_cond_exec): Set predicated attribute to yes.

	2013-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/sync.md (atomic_loaddi_1):
	Disable predication for arm_restrict_it.
	(arm_load_exclusive<mode>): Likewise.
	(arm_load_exclusivesi): Likewise.
	(arm_load_exclusivedi): Likewise.
	(arm_load_acquire_exclusive<mode>): Likewise.
	(arm_load_acquire_exclusivesi): Likewise.
	(arm_load_acquire_exclusivedi): Likewise.
	(arm_store_exclusive<mode>): Likewise.
	(arm_store_exclusive<mode>): Likewise.
	(arm_store_release_exclusivedi): Likewise.
	(arm_store_release_exclusive<mode>): Likewise.

	2013-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no"
	where appropriate.
	* config/arm/ldmstm.md: Regenerate.

	2013-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3,
	sub<mode>3, ussub<mode>3, sssub<mode>3, arm_ssatsihi_shift,
	arm_usatsihi): Adjust alternatives for arm_restrict_it.

2013-07-02  Rob Savoye  <rob.savoye@linaro.org>

	Backport from trunk 200096

	2013-06-14  Vidya Praveen <vidyapraveen@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_<su>mlal_lo<mode>):
	New pattern.
	(aarch64_<su>mlal_hi<mode>, aarch64_<su>mlsl_lo<mode>): Likewise.
	(aarch64_<su>mlsl_hi<mode>, aarch64_<su>mlal<mode>): Likewise.
	(aarch64_<su>mlsl<mode>): Likewise.

2013-07-02  Rob Savoye  <rob.savoye@linaro.org>

	Backport from trunk 200062

	2013-06-13  Bin Cheng  <bin.cheng@arm.com>
	* fold-const.c (operand_equal_p): Consider NOP_EXPR and
	CONVERT_EXPR as equal nodes.

2013-07-02  Rob Savoye  <rob.savoye@linaro.org>
	Backport from trunk 199810

	2013-06-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (anddi3_insn): Remove duplicate alternatives.
	Clean up alternatives.

2013-06-20  Rob Savoye  <rob.savoye@linaro.org>

	Backport from trunk 200152
	2013-06-17  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w
	alternative and update.
	(aarch64_dup_lanedi): Delete.
	* config/aarch64/arm_neon.h (vdup<bhsd>_lane_*): Update.
	* config/aarch64/aarch64-simd-builtins.def: Update.

2013-06-20  Rob Savoye  <rob.savoye@linaro.org>

	Backport from trunk 200061
	2013-06-13  Bin Cheng  <bin.cheng@arm.com>

	* rtlanal.c (noop_move_p): Check the code to be executed for
	COND_EXEC.

2013-06-20  Rob Savoye  <rob.savoye@linaro.org>

	Backport from trunk 199694
	2013-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro.
	(arm_option_override): Override arm_restrict_it where appropriate.
	(thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK.
	* config/arm/arm.opt (mrestrict-it): New command-line option.
	* doc/invoke.texi: Document -mrestrict-it.

2013-06-20  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198683.
	2013-05-07  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/arm/arm.c (arm_asan_shadow_offset): New function.
	(TARGET_ASAN_SHADOW_OFFSET): Define.
	* config/arm/linux-eabi.h (ASAN_CC1_SPEC): Define.
	(LINUX_OR_ANDROID_CC): Add ASAN_CC1_SPEC.

2013-06-18  Rob Savoye  <rob.savoye@linaro.org>

	* LINARO-VERSION: Bump version.

2013-06-11  Rob Savoye  <rob.savoye@linaro.org>

	GCC Linaro gcc-linaro-4.8-2013.06 released.
	* LINARO-VERSION: Update.

2013-06-06  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	Backport from mainline (r199438, r199439)
	2013-05-30  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added.
	(arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes.
	(arm_emit_vfp_multi_reg_pop): Likewise.
	(thumb2_emit_ldrd_pop): Likewise.
	(arm_expand_epilogue): Add misc REG_CFA notes.
	(arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE.

	2013-05-30  Bernd Schmidt  <bernds@codesourcery.com>
		    Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/arm/arm-protos.h: Add and update function protos.
	* config/arm/arm.c (use_simple_return_p): New added.
	(thumb2_expand_return): Check simple_return flag.
	* config/arm/arm.md: Add simple_return and conditional simple_return.
	* config/arm/iterators.md: Add iterator for return and simple_return.
	* gcc.dg/shrink-wrap-alloca.c: New added.
	* gcc.dg/shrink-wrap-pretend.c: New added.
	* gcc.dg/shrink-wrap-sibcall.c: New added.

2013-06-06  Kugan Vivekanandarajah  <kuganv@linaro.org>

	Backport from mainline r198879:

	2013-05-14  Chung-Lin Tang  <cltang@codesourcery.com>
	PR target/42017
	* config/arm/arm.h (EPILOGUE_USES): Only return true
	for LR_REGNUM after epilogue_completed.

2013-06-05  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r199652,199653,199656,199657,199658.

	2013-06-04  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Call
	into function to generate MOVI instruction.
	* config/aarch64/aarch64.c (aarch64_simd_container_mode):
	New function.
	(aarch64_preferred_simd_mode): Turn into wrapper.
	(aarch64_output_scalar_simd_mov_immediate): New function.
	* config/aarch64/aarch64-protos.h: Add prototype for above.

	2013-06-04  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.c (simd_immediate_info): Remove
	element_char member.
	(sizetochar): Return signed char.
	(aarch64_simd_valid_immediate): Remove elchar and other
	unnecessary variables.
	(aarch64_output_simd_mov_immediate): Take rtx instead of &rtx.
	Calculate element_char as required.
	* config/aarch64/aarch64-protos.h: Update and move prototype
	for aarch64_output_simd_mov_immediate.
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>):
	Update arguments.

	2013-06-04  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.c (simd_immediate_info): Struct to hold
	information completed by aarch64_simd_valid_immediate.
	(aarch64_legitimate_constant_p): Update arguments.
	(aarch64_simd_valid_immediate): Work with struct rather than many
	pointers.
	(aarch64_simd_scalar_immediate_valid_for_move): Update arguments.
	(aarch64_simd_make_constant): Update arguments.
	(aarch64_output_simd_mov_immediate): Work with struct rather than
	many pointers.  Output immediate directly rather than as operand.
	* config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate):
	Update prototype.
	* config/aarch64/constraints.md (Dn): Update arguments.

	2013-06-04  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No
	longer static.
	(aarch64_simd_immediate_valid_for_move): Remove.
	(aarch64_simd_scalar_immediate_valid_for_move): Update call.
	(aarch64_simd_make_constant): Update call.
	(aarch64_output_simd_mov_immediate): Update call.
	* config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate):
	Add prototype.
	* config/aarch64/constraints.md (Dn): Update call.

	2013-06-04  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change
	return type to bool for prototype.
	(aarch64_legitimate_constant_p): Check for true instead of not -1.
	(aarch64_simd_valid_immediate): Fix up each return to return a bool.
	(aarch64_simd_immediate_valid_for_move): Update retval for bool.

2013-06-04  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r199261.
	2013-05-23  Christian Bruel  <christian.bruel@st.com>

	PR debug/57351
	* config/arm/arm.c (arm_dwarf_register_span): Do not use dbx number.

2013-06-03  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk
	r198890,199254,199259,199260,199293,199407,199408,199454,199544,199545.

	2013-05-31  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
	Remove un-necessary braces.

	2013-05-31  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64.c (aarch64_classify_symbol):
	Use SYMBOL_TINY_ABSOLUTE for AARCH64_CMODEL_TINY_PIC.

	2013-05-30  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (insv<mode>): New define_expand.
	(*insv_reg<mode>): New define_insn.

	2012-05-29  Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
	    Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64-protos.h (aarch64_symbol_type): Define
	SYMBOL_TINY_ABSOLUTE.
	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Handle
	SYMBOL_TINY_ABSOLUTE.
	(aarch64_expand_mov_immediate): Likewise.
	(aarch64_classify_symbol): Likewise.
	(aarch64_mov_operand_p): Remove ATTRIBUTE_UNUSED.
	Permit SYMBOL_TINY_ABSOLUTE.
	* config/aarch64/predicates.md (aarch64_mov_operand): Permit CONST.

	2013-05-29  Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
	    Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64.c (aarch64_classify_symbol): Remove comment.
	Refactor if/switch.  Replace gcc_assert with if.

	2013-05-24  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.c (aarch64_print_operand): Change the
	X format specifier to only display bottom 16 bits.
	* config/aarch64/aarch64.md (insv_imm<mode>): Allow any size of
	immediate to match for operand 2, since it will be masked.

	2013-05-23  Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
	    Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64.md (*movdi_aarch64): Replace Usa with S.
	* config/aarch64/constraints.md (Usa): Remove.
	* doc/md.texi (AArch64 Usa): Remove.

	2013-05-23  Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
	    Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64-protos.h (aarch64_mov_operand_p): Define.
	* config/aarch64/aarch64.c (aarch64_mov_operand_p): Define.
	* config/aarch64/predicates.md (aarch64_const_address): Remove.
	(aarch64_mov_operand): Use aarch64_mov_operand_p.

	2013-05-23  Vidya Praveen <vidyapraveen@arm.com>

	* config/aarch64/aarch64-simd.md (clzv4si2): Support for CLZ
	instruction (AdvSIMD).
	* config/aarch64/aarch64-builtins.c
	(aarch64_builtin_vectorized_function): Handler for BUILT_IN_CLZ.
	* config/aarch64/aarch-simd-builtins.def: Entry for CLZ.

	2013-05-14  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_vcond_internal<mode>): Rename to...
	(aarch64_vcond_internal<mode><mode>): ...This, for integer modes.
	(aarch64_vcond_internal<VDQF_COND:mode><VDQF:mode>): ...This for
	float modes. Clarify all iterator modes.
	(vcond<mode><mode>): Use new name for vcond expanders.
	(vcond<v_cmp_result><mode>): Likewise.
	(vcondu<mode><mode>: Likewise.
	* config/aarch64/iterators.md (VDQF_COND): New.

2013-05-29  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198928,198973,199203.
	2013-05-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	PR target/57340
	* config/arm/arm.c (any_sibcall_uses_r3): Rename to ..
	(any_sibcall_could_use_r3): this and handle indirect calls.
	(arm_get_frame_offsets): Rename use of any_sibcall_uses_r3.

	2013-05-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	* config/arm/arm.c (arm_function_ok_for_sibcall): Add check
	for NULL decl.

	2013-05-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	* config/arm/predicates.md (call_insn_operand): New predicate.
	* config/arm/constraints.md ("Cs", "Ss"):  New constraints.
	* config/arm/arm.md (*call_insn, *call_value_insn): Match only
	if insn is not a tail call.
	(*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through
	registers.
	* config/arm/arm.h (enum reg_class): New caller save register class.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	* config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling
	without decls.

2013-05-28  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198680.
	2013-05-07  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): call splitter.
	(aarch64_simd_mov<mode>): New expander.
	(aarch64_simd_mov_to_<mode>low): New instruction pattern.
	(aarch64_simd_mov_to_<mode>high): Likewise.
	(aarch64_simd_mov_from_<mode>low): Likewise.
	(aarch64_simd_mov_from_<mode>high): Likewise.
	(aarch64_dup_lane<mode>): Update.
	(aarch64_dup_lanedi): New instruction pattern.
	* config/aarch64/aarch64-protos.h (aarch64_split_simd_move): New prototype.
	* config/aarch64/aarch64.c (aarch64_split_simd_move): New function.

2013-05-28  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198497-198500.
	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_.
	* config/aarch64/aarch64-simd-builtins.def
	(reduc_splus_): Add new modes.
	(reduc_uplus_): New.
	* config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove.
	(reduc_uplus_v4sf): Likewise.
	(reduc_splus_v4sf): Likewise.
	(aarch64_addv<mode>): Likewise.
	(reduc_uplus_<mode>): Likewise.
	(reduc_splus_<mode>): Likewise.
	(aarch64_addvv2di): Likewise.
	(reduc_uplus_v2di): Likewise.
	(reduc_splus_v2di): Likewise.
	(aarch64_addvv2si): Likewise.
	(reduc_uplus_v2si): Likewise.
	(reduc_splus_v2si): Likewise.
	(reduc_<sur>plus_<mode>): New.
	(reduc_<sur>plus_v2di): Likewise.
	(reduc_<sur>plus_v2si): Likewise.
	(reduc_<sur>plus_v4sf): Likewise.
	(aarch64_addpv4sf): Likewise.
	* config/aarch64/arm_neon.h
	(vaddv<q>_<s,u,f><8, 16, 32, 64): Rewrite using builtins.
	* config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV,
	add UNSPEC_SADDV, UNSPEC_UADDV.
	(SUADDV): New.
	(sur): Add UNSPEC_SADDV, UNSPEC_UADDV.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/arm_neon.h
	(v<max,min><nm><q><v>_<sfu><8, 16, 32, 64>): Rewrite using builtins.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins
	(aarch64_gimple_fold_builtin): Fold reduc_<su><maxmin>_ builtins.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd-builtins.def
	(reduc_smax_): New.
	(reduc_smin_): Likewise.
	(reduc_umax_): Likewise.
	(reduc_umin_): Likewise.
	(reduc_smax_nan_): Likewise.
	(reduc_smin_nan_): Likewise.
	(fmax): Remove.
	(fmin): Likewise.
	(smax): Update for V2SF, V4SF and V2DF modes.
	(smin): Likewise.
	(smax_nan): New.
	(smin_nan): Likewise.
	* config/aarch64/aarch64-simd.md (<maxmin><mode>3): Rename to...
	(<su><maxmin><mode>3): ...This, refactor.
	(s<maxmin><mode>3): New.
	(<maxmin_uns><mode>3): Likewise.
	(reduc_<maxmin_uns>_<mode>): Refactor.
	(reduc_<maxmin_uns>_v4sf): Likewise.
	(reduc_<maxmin_uns>_v2si): Likewise.
	(aarch64_<fmaxmin><mode>: Remove.
	* config/aarch64/arm_neon.h (vmax<q>_f<32,64>): Rewrite to use
	new builtin names.
	(vmin<q>_f<32,64>): Likewise.
	* config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV.
	(FMAXMIN): New.
	(su): Add mappings for smax, smin, umax, umin.
	(maxmin): New.
	(FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV.
	(FMAXMIN): Rename as...
	(FMAXMIN_UNS): ...This.
	(maxminv): Remove.
	(fmaxminv): Likewise.
	(fmaxmin): Likewise.
	(maxmin_uns): New.
	(maxmin_uns_op): Likewise.

2013-05-28  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r199241.
	2013-05-23  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_cm<optab>di): Add clobber of CC_REGNUM to unsplit pattern.

2013-05-23  Christophe Lyon  <christophe.lyon@linaro.org>

	Backport from trunk r198970.
	2013-05-16  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm-protos.h (gen_movmem_ldrd_strd): New declaration.
	* config/arm/arm.c (next_consecutive_mem): New function.
	(gen_movmem_ldrd_strd): Likewise.
	* config/arm/arm.md (movmemqi): Update condition and code.
	(unaligned_loaddi, unaligned_storedi): New patterns.

2013-05-19  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	* LINARO-VERSION: Bump version number.

2013-05-14  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	GCC Linaro 4.8-2013.05 released.
	* LINARO-VERSION: Update.

2013-05-14  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198677.
	2013-05-07  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md
	(cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Restrict the
	shift value between 0-4.

2013-05-14  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198574-198575.
	2013-05-03  Vidya Praveen  <vidyapraveen@arm.com>

	* config/aarch64/aarch64-simd.md (simd_fabd): Correct the description.

	2013-05-03  Vidya Praveen  <vidyapraveen@arm.com>

	* config/aarch64/aarch64-simd.md (*fabd_scalar<mode>3): Support
	scalar form of FABD instruction.

2013-05-14  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198490-198496
	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/arm_neon.h
	(vac<ge, gt><sd>_f<32, 64>): Rename to...
	(vca<ge, gt><sd>_f<32, 64>): ...this, reimpliment in C.
	(vca<ge, gt, lt, le><q>_f<32, 64>): Reimpliment in C.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New.
	* config/aarch64/iterators.md (FAC_COMPARISONS): New.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(vcond<mode>_internal): Handle special cases for constant masks.
	(vcond<mode><mode>): Allow nonmemory_operands for outcome vectors.
	(vcondu<mode><mode>): Likewise.
	(vcond<v_cmp_result><mode>): New.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c (BUILTIN_VALLDI): Define.
	(aarch64_fold_builtin): Add folding for cm<eq,ge,gt,tst>.
	* config/aarch64/aarch64-simd-builtins.def
	(cmeq): Update to BUILTIN_VALLDI.
	(cmgt): Likewise.
	(cmge): Likewise.
	(cmle): Likewise.
	(cmlt): Likewise.
	* config/aarch64/arm_neon.h
	(vc<eq, lt, le, gt, ge, tst><z><qsd>_<fpsu><8,16,32,64>): Remap
	to builtins or C as appropriate.

	2013-05-01  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...
	(cmgeu): ...This.
	(cmhi): Rename to...
	(cmgtu): ...This.
	* config/aarch64/aarch64-simd.md
	(simd_mode): Add SF.
	(aarch64_vcond_internal): Use new names for unsigned comparison insns.
	(aarch64_cm<optab><mode>): Rewrite to not use UNSPECs.
	* config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to...
	(cstore<mode>_neg): ...This.
	* config/aarch64/iterators.md
	(VALLF): new.
	(unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>.
	(COMPARISONS): New.
	(UCOMPARISONS): Likewise.
	(optab): Add missing comparisons.
	(n_optab): New.
	(cmp_1): Likewise.
	(cmp_2): Likewise.
	(CMP): Likewise.
	(cmp): Remove.
	(VCMP_S): Likewise.
	(VCMP_U): Likewise.
	(V_cmp_result): Add DF, SF modes.
	(v_cmp_result): Likewise.
	(v): Likewise.
	(vmtype): Likewise.
	* config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.

2013-05-14  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198191.
	2013-04-23  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Add simd attribute.

2013-05-14  Matthew Gretton-Dann  <matthew.gretton-dann@lianro.org>

	Backport from trunk r197838.
	2013-04-11   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Allow NEG
	code in CC_NZ mode.
	* config/aarch64/aarch64.md (*neg_<shift><mode>3_compare0): New
	pattern.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198019.
	2013-04-16   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*adds_mul_imm_<mode>): New pattern.
	(*subs_mul_imm_<mode>): New pattern.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198424-198425.
	2013-04-29  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (movsi_aarch64): Support LDR/STR
	from/to S register.
	(movdi_aarch64): Support LDR/STR from/to D register.

	2013-04-29  Ian Bolton  <ian.bolton@arm.com>

	* common/config/aarch64/aarch64-common.c: Enable REE pass at O2
	or higher by default.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198412.
	2013-04-29  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (store_minmaxsi): Use only when
	optimize_insn_for_size_p.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk 198394,198396-198400,198402-198404.
	2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/arm_neon.h
	(vcvt<sd>_f<32,64>_s<32,64>): Rewrite in C.
	(vcvt<q>_f<32,64>_s<32,64>): Rewrite using builtins.
	(vcvt_<high_>_f<32,64>_f<32,64>): Likewise.
	(vcvt<qsd>_<su><32,64>_f<32,64>): Likewise.
	(vcvta<qsd>_<su><32,64>_f<32,64>): Likewise.
	(vcvtm<qsd>_<su><32,64>_f<32,64>): Likewise.
	(vcvtn<qsd>_<su><32,64>_f<32,64>): Likewise.
	(vcvtp<qsd>_<su><32,64>_f<32,64>): Likewise.

	2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(<optab><VDQF:mode><fcvt_target>2): New, maps to fix, fixuns.
	(<fix_trunc_optab><VDQF:mode><fcvt_target>2): New, maps to
	fix_trunc, fixuns_trunc.
	(ftrunc<VDQF:mode>2): New.
	* config/aarch64/iterators.md (optab): Add fix, fixuns.
	(fix_trunc_optab): New.

	2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_builtin_vectorized_function): Vectorize over ifloorf,
	iceilf, lround, iroundf.

	2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi_): New.
	(float_truncate_hi_): Likewise.
	(float_extend_lo_): Likewise.
	(float_truncate_lo_): Likewise.
	* config/aarch64/aarch64-simd.md (vec_unpacks_lo_v4sf): New.
	(aarch64_float_extend_lo_v2df): Likewise.
	(vec_unpacks_hi_v4sf): Likewise.
	(aarch64_float_truncate_lo_v2sf): Likewise.
	(aarch64_float_truncate_hi_v4sf): Likewise.
	(vec_pack_trunc_v2df): Likewise.
	(vec_pack_trunc_df): Likewise.

	2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_fold_builtin): Fold float conversions.
	* config/aarch64/aarch64-simd-builtins.def
	(floatv2si, floatv4si, floatv2di): New.
	(floatunsv2si, floatunsv4si, floatunsv2di): Likewise.
	* config/aarch64/aarch64-simd.md
	(<optab><fcvt_target><VDQF:mode>2): New, expands to float and floatuns.
	* config/aarch64/iterators.md (FLOATUORS): New.
	(optab): Add float, floatuns.
	(su_optab): Likewise.

	2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_builtin_vectorized_function): Fold to standard pattern names.
	* config/aarch64/aarch64-simd-builtins.def (frintn): New.
	(frintz): Rename to...
	(btrunc): ...this.
	(frintp): Rename to...
	(ceil): ...this.
	(frintm): Rename to...
	(floor): ...this.
	(frinti): Rename to...
	(nearbyint): ...this.
	(frintx): Rename to...
	(rint): ...this.
	(frinta): Rename to...
	(round): ...this.
	* config/aarch64/aarch64-simd.md
	(aarch64_frint<frint_suffix><mode>): Delete.
	(<frint_pattern><mode>2): Convert to insn.
	* config/aarch64/aarch64.md (unspec): Add UNSPEC_FRINTN.
	* config/aarch64/iterators.md (FRINT): Add UNSPEC_FRINTN.
	(frint_pattern): Likewise.
	(frint_suffix): Likewise.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198302-198306,198316.
	2013-04-25  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_simd_bsl<mode>_internal): Rewrite RTL to not use UNSPEC_BSL.
	(aarch64_simd_bsl<mode>): Likewise.
	* config/aarch64/iterators.md (unspec): Remove UNSPEC_BSL.

	2013-04-25  James Greenhalgh  <jame.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md (neg<mode>2): Use VDQ iterator.

	2013-04-25  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_fold_builtin): New.
	* config/aarch64/aarch64-protos.h (aarch64_fold_builtin): New.
	* config/aarch64/aarch64.c (TARGET_FOLD_BUILTIN): Define.
	* config/aarch64/aarch64-simd-builtins.def (abs): New.
	* config/aarch64/arm_neon.h
	(vabs<q>_<f32, 64>): Implement using __builtin_aarch64_fabs.

	2013-04-25  James Greenhalgh  <james.greenhalgh@arm.com>
	    Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_gimple_fold_builtin): New.
	* config/aarch64/aarch64-protos.h (aarch64_gimple_fold_builtin): New.
	* config/aarch64/aarch64-simd-builtins.def (addv): New.
	* config/aarch64/aarch64-simd.md (addpv4sf): New.
	(addvv4sf): Update.
	* config/aarch64/aarch64.c (TARGET_GIMPLE_FOLD_BUILTIN): Define.

	2013-04-25  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md 
	(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): New pattern.

	2013-04-25  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*ngc<mode>): New pattern.
	(*ngcsi_uxtw): New pattern.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk 198298.
	2013-04-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
	    Julian Brown  <julian@codesourcery.com>

	* config/arm/arm.c (neon_builtin_type_mode): Add T_V4HF.
	(TB_DREG): Add T_V4HF.
	(v4hf_UP): New macro.
	(neon_itype): Add NEON_FLOAT_WIDEN, NEON_FLOAT_NARROW.
	(arm_init_neon_builtins): Handle NEON_FLOAT_WIDEN,
	NEON_FLOAT_NARROW.
	Handle initialisation of V4HF. Adjust initialisation of reinterpret
	built-ins.
	(arm_expand_neon_builtin): Handle NEON_FLOAT_WIDEN,
	NEON_FLOAT_NARROW.
	(arm_vector_mode_supported_p): Handle V4HF.
	(arm_mangle_map): Handle V4HFmode.
	* config/arm/arm.h (VALID_NEON_DREG_MODE): Add V4HF.
	* config/arm/arm_neon_builtins.def: Add entries for
	vcvtv4hfv4sf, vcvtv4sfv4hf.
	* config/arm/neon.md (neon_vcvtv4sfv4hf): New pattern.
	(neon_vcvtv4hfv4sf): Likewise.
	* config/arm/neon-gen.ml: Handle half-precision floating point
	features.
	* config/arm/neon-testgen.ml: Handle Requires_FP_bit feature.
	* config/arm/arm_neon.h: Regenerate.
	* config/arm/neon.ml (type elts): Add F16.
	(type vectype): Add T_float16x4, T_floatHF.
	(type vecmode): Add V4HF.
	(type features): Add Requires_FP_bit feature.
	(elt_width): Handle F16.
	(elt_class): Likewise.
	(elt_of_class_width): Likewise.
	(mode_of_elt): Refactor.
	(type_for_elt): Handle F16, fix error messages.
	(vectype_size): Handle T_float16x4.
	(vcvt_sh): New function.
	(ops): Add entries for vcvt_f16_f32, vcvt_f32_f16.
	(string_of_vectype): Handle T_floatHF, T_float16, T_float16x4.
	(string_of_mode): Handle V4HF.
	* doc/arm-neon-intrinsics.texi: Regenerate.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198136-198137,198142,198176.
	2013-04-23  Andreas Schwab  <schwab@linux-m68k.org>

	* coretypes.h (gimple_stmt_iterator): Add struct to make
	compatible with C.

	2013-04-22  James Greenhalgh  <james.greenhalgh@arm.com>

	* coretypes.h (gimple_stmt_iterator_d): Forward declare.
	(gimple_stmt_iterator): New typedef.
	* gimple.h (gimple_stmt_iterator): Rename to...
	(gimple_stmt_iterator_d): ... This.
	* doc/tm.texi.in (TARGET_FOLD_BUILTIN): Detail restriction that
	trees be valid for GIMPLE and GENERIC.
	(TARGET_GIMPLE_FOLD_BUILTIN): New.
	* gimple-fold.c (gimple_fold_call): Call target hook
	gimple_fold_builtin.
	* hooks.c (hook_bool_gsiptr_false): New.
	* hooks.h (hook_bool_gsiptr_false): New.
	* target.def (fold_stmt): New.
	* doc/tm.texi: Regenerate.

	2013-04-22  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(CF): Remove.
	(CF0, CF1, CF2, CF3, CF4, CF10): New.
	(VAR<1-12>): Add MAP parameter.
	(BUILTIN_*): Likewise.
	* config/aarch64/aarch64-simd-builtins.def: Set MAP parameter.
	* config/aarch64/aarch64-simd.md (aarch64_sshl_n<mode>): Remove.
	(aarch64_ushl_n<mode>): Likewise.
	(aarch64_sshr_n<mode>): Likewise.
	(aarch64_ushr_n<mode>): Likewise.
	(aarch64_<maxmin><mode>): Likewise.
	(aarch64_sqrt<mode>): Likewise.
	* config/aarch64/arm_neon.h (vshl<q>_n_*): Use new builtin names.
	(vshr<q>_n_*): Likewise.

	2013-04-22  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_simd_builtin_type_mode): Handle SF types.
	(sf_UP): Define.
	(BUILTIN_GPF): Define.
	(aarch64_init_simd_builtins): Handle SF types.
	* config/aarch64/aarch64-simd-builtins.def (frecpe): Add support.
	(frecps): Likewise.
	(frecpx): Likewise.
	* config/aarch64/aarch64-simd.md
	(simd_types): Update simd_frcp<esx> to simd_frecp<esx>.
	(aarch64_frecpe<mode>): New.
	(aarch64_frecps<mode>): Likewise.
	* config/aarch64/aarch64.md (unspec): Add UNSPEC_FRECP<ESX>.
	(v8type): Add frecp<esx>.
	(aarch64_frecp<FRECP:frecp_suffix><mode>): New.
	(aarch64_frecps<mode>): Likewise.
	* config/aarch64/iterators.md (FRECP): New.
	(frecp_suffix): Likewise.
	* config/aarch64/arm_neon.h
	(vrecp<esx><qsd>_<fd><32, 64>): Convert to using builtins.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198030.
	2013-04-17  Greta Yorsh  <Greta.Yorsh at arm.com>

	* config/arm/arm.md (movsicc_insn): Convert define_insn into
	define_insn_and_split.
	(and_scc,ior_scc,negscc): Likewise.
	(cmpsi2_addneg, subsi3_compare): Convert to named patterns.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198020.
	2013-04-16   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*adds_<optab><mode>_multp2):
	New pattern.
	(*subs_<optab><mode>_multp2): New pattern.
	(*adds_<optab><ALLX:mode>_<GPI:mode>): New pattern.
	(*subs_<optab><ALLX:mode>_<GPI:mode>): New pattern.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r198004,198029.
	2013-04-17  Greta Yorsh  <Greta.Yorsh at arm.com>

	* config/arm/arm.c (use_return_insn): Return 0 for targets that
	can benefit from using a sequence of LDRD instructions in epilogue
	instead of a single LDM instruction.

	2013-04-16  Greta Yorsh  <Greta.Yorsh at arm.com>

	* config/arm/arm.c (emit_multi_reg_push): New declaration
	for an existing function.
	(arm_emit_strd_push): New function.
	(arm_expand_prologue): Used here.
	(arm_emit_ldrd_pop): New function.
	(arm_expand_epilogue): Used here.
	(arm_get_frame_offsets): Update condition.
	(arm_emit_multi_reg_pop): Add a special case for load of a single
	register with writeback.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197965.
	2013-04-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (const_ok_for_dimode_op): Handle AND case.
	* config/arm/arm.md (*anddi3_insn): Change to insn_and_split.
	* config/arm/constraints.md (De): New constraint.
	* config/arm/neon.md (anddi3_neon): Delete.
	(neon_vand<mode>): Expand to standard anddi3 pattern.
	* config/arm/predicates.md (imm_for_neon_inv_logic_operand):
	Move earlier in the file.
	(neon_inv_logic_op2): Likewise.
	(arm_anddi_operand_neon): New predicate.

2013-05-02  Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>

	Backport from trunk r197925.
	2013-04-12  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (mov_scc,mov_negscc,mov_notscc): Convert
	define_insn into define_insn_and_split and emit movsicc patterns.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197807.
	2013-04-11   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Define.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197642.
	2013-04-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (minmax_arithsi_non_canon): New pattern.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197530,197921.
	2013-04-12  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.c (gen_operands_ldrd_strd): Initialize "base".

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/constraints.md (q): New constraint.
	* config/arm/ldrdstrd.md: New file.
	* config/arm/arm.md (ldrdstrd.md) New include.
	(arm_movdi): Use "q" instead of "r" constraint
	for double-word memory access.
	(movdf_soft_insn): Likewise.
	* config/arm/vfp.md (movdi_vfp): Likewise.
	* config/arm/t-arm (MD_INCLUDES): Add ldrdstrd.md.
	* config/arm/arm-protos.h (gen_operands_ldrd_strd): New declaration.
	* config/arm/arm.c (gen_operands_ldrd_strd): New function.
	(mem_ok_for_ldrd_strd): Likewise.
	(output_move_double): Update assertion.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197518-197522,197526-197528.
	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (arm_smax_insn): Convert define_insn into
	define_insn_and_split.
	(arm_smin_insn,arm_umaxsi3,arm_uminsi3): Likewise.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (arm_ashldi3_1bit): Convert define_insn into
	define_insn_and_split.
	(arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise.
	(shiftsi3_compare): New pattern.
	(rrx): New pattern.
	* config/arm/unspecs.md (UNSPEC_RRX): New.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (negdi_extendsidi): New pattern.
	(negdi_zero_extendsidi): Likewise.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into
	define_insn_and_split.
	(arm_negdi2,arm_abssi2,arm_neg_abssi2): Likewise.
	(arm_cmpdi_insn,arm_cmpdi_unsigned): Likewise.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (arm_subdi3): Convert define_insn into
	define_insn_and_split.
	(subdi_di_zesidi,subdi_di_sesidi): Likewise.
	(subdi_zesidi_di,subdi_sesidi_di,subdi_zesidi_zesidi): Likewise.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (subsi3_carryin): New pattern.
	(subsi3_carryin_const): Likewise.
	(subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise.
	(subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (incscc,arm_incscc,decscc,arm_decscc): Delete.

	2013-04-05  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.md (addsi3_carryin_<optab>): Set attribute predicable.
	(addsi3_carryin_alt2_<optab>,addsi3_carryin_shift_<optab>): Likewise.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197517.
	2013-04-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (arm_expand_builtin): Change fcode
	type to unsigned int.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197513.
	2013-04-05  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* doc/invoke.texi (ARM Options): Document cortex-a53 support.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197489-197491.
	2013-04-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-protos.h (arm_builtin_vectorized_function):
	New function prototype.
	* config/arm/arm.c (TARGET_VECTORIZE_BUILTINS): Define.
	(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
	(arm_builtin_vectorized_function): New function.

	2013-04-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm_neon_builtins.def: New file.
	* config/arm/arm.c (neon_builtin_data): Move contents to
	arm_neon_builtins.def.
	(enum arm_builtins): Include neon builtin definitions.
	(ARM_BUILTIN_NEON_BASE): Move from enum to macro.
	* config/arm/t-arm (arm.o): Add dependency on
	arm_neon_builtins.def.

2013-05-02  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk 196795-196797,196957
	2013-03-19  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (*sub<mode>3_carryin): New pattern.
	(*subsi3_carryin_uxtw): Likewise.

	2013-03-19  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (*ror<mode>3_insn): New pattern.
	(*rorsi3_insn_uxtw): Likewise.

	2013-03-19  Ian Bolton  <ian.bolton@arm.com>

	* config/aarch64/aarch64.md (*extr<mode>5_insn): New pattern.
	(*extrsi5_insn_uxtw): Likewise.

2013-04-10  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	* LINARO-VERSION: Bump version number.

2013-04-09  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	GCC Linaro 4.8-2013.04 released.
	* LINARO-VERSION: New file.
	* configure.ac: Add Linaro version string.
	* configure: Regenerate.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197346.
	2013-04-02  Ian Caulfield  <ian.caulfield@arm.com>
	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/arm-arches.def (armv8-a): Default to cortex-a53.
	* config/arm/t-arm (MD_INCLUDES): Depend on cortex-a53.md.
	* config/arm/cortex-a53.md: New file.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Handle cortex-a53.
	* config/arm/arm.md (generic_sched, generic_vfp): Handle cortex-a53.
	* config/arm/arm.c (arm_issue_rate): Likewise.
	* config/arm/arm-tune.md: Regenerate
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-cores.def: Add cortex-a53.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197342.
	2013-04-02  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Add variants for
	scalar load/store operations using B/H registers.
	(*zero_extend<SHORT:mode><GPI:mode>2_aarch64): Likewise.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport of trunk r197341.
	2013-04-02  Sofiane Naci  <sofiane.naci@arm.com>

	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Add alternatives for
	scalar move.
	* config/aarch64/aarch64.c
	(aarch64_simd_scalar_immediate_valid_for_move): New.
	* config/aarch64/aarch64-protos.h
	(aarch64_simd_scalar_immediate_valid_for_move): New.
	* config/aarch64/constraints.md (Dh, Dq): New.
	* config/aarch64/iterators.md (hq): New.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197207.
	2013-03-28   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern.
	(*andsi3_compare0_uxtw): New pattern.
	(*and_<SHIFT:optab><mode>3_compare0): New pattern.
	(*and_<SHIFT:optab>si3_compare0_uxtw): New pattern.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197153.
	2013-03-27  Terry Guo  <terry.guo@arm.com>

	* config/arm/arm-cores.def: Added core cortex-r7.
	* config/arm/arm-tune.md: Regenerated.
	* config/arm/arm-tables.opt: Regenerated.
	* doc/invoke.texi: Added entry for core cortex-r7.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197052.
	2013-03-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (f_sels, f_seld): New types.
	(*cmov<mode>): New pattern.
	* config/arm/predicates.md (arm_vsel_comparison_operator): New
	predicate.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r197046.
	2013-03-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (arm_emit_load_exclusive): Add acq parameter.
	Emit load-acquire versions when acq is true.
	(arm_emit_store_exclusive): Add rel parameter.
	Emit store-release versions when rel is true.
	(arm_split_compare_and_swap): Use acquire-release instructions
	instead.
	of barriers when appropriate.
	(arm_split_atomic_op): Likewise.
	* config/arm/arm.h (TARGET_HAVE_LDACQ): New macro.
	* config/arm/unspecs.md (VUNSPEC_LAX): New unspec.
	(VUNSPEC_SLX): Likewise.
	(VUNSPEC_LDA): Likewise.
	(VUNSPEC_STL): Likewise.
	* config/arm/sync.md (atomic_load<mode>): New pattern.
	(atomic_store<mode>): Likewise.
	(arm_load_acquire_exclusive<mode>): Likewise.
	(arm_load_acquire_exclusivesi): Likewise.
	(arm_load_acquire_exclusivedi): Likewise.
	(arm_store_release_exclusive<mode>): Likewise.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r196876.
	2013-03-21  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/arm/arm-protos.h (tune_params): Add
	prefer_neon_for_64bits field.
	* config/arm/arm.c (prefer_neon_for_64bits): New variable.
	(arm_slowmul_tune): Default prefer_neon_for_64bits to false.
	(arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto.
	(arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto.
	(arm_cortex_a15_tune, arm_cortex_a5_tune): Ditto.
	(arm_cortex_a9_tune, arm_v6m_tune, arm_fa726te_tune): Ditto.
	(arm_option_override): Handle -mneon-for-64bits new option.
	* config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro.
	(prefer_neon_for_64bits): Declare new variable.
	* config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to
	avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and
	nota8.
	(arch_enabled): Handle new arch types. Remove support for onlya8
	and nota8.
	(one_cmpldi2): Use new arch names.
	* config/arm/arm.opt (mneon-for-64bits): Add option.
	* config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon)
	(anddi3_neon, xordi3_neon, ashldi3_neon, <shift>di3_neon): Use
	neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead
	of onlya8.
	* doc/invoke.texi (-mneon-for-64bits): Document.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r196858.
	2013-03-21   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64-simd.md (simd_fabd): New Attribute.
	(abd<mode>_3): New pattern.
	(aba<mode>_3): New pattern.
	(fabd<mode>_3): New pattern.

2013-04-08  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	Backport from trunk r196856.
	2013-03-21   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64-elf.h (REGISTER_PREFIX): Remove.
	* config/aarch64/aarch64.c (aarch64_print_operand): Remove all
	occurrence of REGISTER_PREFIX as its empty string.