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|
2013-01-18 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h: Map scalar types to standard types.
2013-01-14 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
* config/aarch64/iterators.md (VALLDI): New.
2013-01-10 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Handle sqrt, sqrtf.
2013-01-09 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/aarch64/aarch64.c (aarch64_print_operand): Replace %r
in asm_fprintf with reg_names.
(aarch64_print_operand_address): Likewise.
(aarch64_return_addr): Likewise.
* config/aarch64/aarch64.h (ASM_FPRINTF_EXTENSIONS): Remove.
2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (vec_init<mode>): New.
* config/aarch64/aarch64-protos.h (aarch64_expand_vector_init): Declare.
* config/aarch64/aarch64.c (aarch64_simd_dup_constant,
aarch64_simd_make_constant, aarch64_expand_vector_init): New.
2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>,
aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand
with tab instead of space.
2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2013-01-07 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/arm_neon.h (vld1_dup_*): Make argument const.
(vld1q_dup_*): Likewise.
(vld1_*): Likewise.
(vld1q_*): Likewise.
(vld1_lane_*): Likewise.
(vld1q_lane_*): Likewise.
2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2013-01-07 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h
(aarch64_const_double_zero_rtx_p): Rename to...
(aarch64_float_const_zero_rtx_p): ...this.
(aarch64_float_const_representable_p): New.
(aarch64_output_simd_mov_immediate): Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Refactor
move immediate case.
* config/aarch64/aarch64.c
(aarch64_const_double_zero_rtx_p): Rename to...
(aarch64_float_const_zero_rtx_p): ...this.
(aarch64_print_operand): Allow printing of new constants.
(aarch64_valid_floating_const): New.
(aarch64_legitimate_constant_p): Check for valid floating-point
constants.
(aarch64_simd_valid_immediate): Likewise.
(aarch64_vect_float_const_representable_p): New.
(aarch64_float_const_representable_p): Likewise.
(aarch64_simd_imm_zero_p): Also allow for floating-point 0.0.
(aarch64_output_simd_mov_immediate): New.
* config/aarch64/aarch64.md (*movsf_aarch64): Add new alternative.
(*movdf_aarch64): Likewise.
* config/aarch64/constraints.md (Ufc): New.
(Y): call aarch64_float_const_zero_rtx.
* config/aarch64/predicates.md (aarch64_fp_compare_operand): New.
2013-01-07 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vmovn_high_is16, vmovn_high_s32,
vmovn_high_s64, vmovn_high_u16, vmovn_high_u32, vmovn_high_u64,
vqmovn_high_s16, vqmovn_high_s32, vqmovn_high_s64, vqmovn_high_u16,
vqmovn_high_u32, vqmovn_high_u64, vqmovun_high_s16, vqmovun_high_s32,
vqmovun_high_s64): Fix source operand number and update copyright.
2013-01-02 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-12-18 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_simd_attr_length_move):
Remove unused variables.
(aarch64_split_compare_and_swap): Likewise.
2012-12-20 Ian Bolton <ian.bolton@arm.com>
Backport from mainline
2012-12-20 Ian Bolton <ian.bolton@arm.com>
* gcc/config/aarch64/aarch64.md
(*addsi3_aarch64_uxtw): New pattern.
(*addsi3_compare0_uxtw): New pattern.
(*add_<shift>_si_uxtw): New pattern.
(*add_<optab><SHORT:mode>_si_uxtw): New pattern.
(*add_<optab><SHORT:mode>_shft_si_uxtw): New pattern.
(*add_<optab><SHORT:mode>_mult_si_uxtw): New pattern.
(*add_<optab>si_multp2_uxtw): New pattern.
(*addsi3_carryin_uxtw): New pattern.
(*addsi3_carryin_alt1_uxtw): New pattern.
(*addsi3_carryin_alt2_uxtw): New pattern.
(*addsi3_carryin_alt3_uxtw): New pattern.
(*add_uxtsi_multp2_uxtw): New pattern.
(*subsi3_uxtw): New pattern.
(*subsi3_compare0_uxtw): New pattern.
(*sub_<shift>_si_uxtw): New pattern.
(*sub_mul_imm_si_uxtw): New pattern.
(*sub_<optab><SHORT:mode>_si_uxtw): New pattern.
(*sub_<optab><SHORT:mode>_shft_si_uxtw): New pattern.
(*sub_<optab>si_multp2_uxtw): New pattern.
(*sub_uxtsi_multp2_uxtw): New pattern.
(*negsi2_uxtw): New pattern.
(*negsi2_compare0_uxtw): New pattern.
(*neg_<shift>_si2_uxtw): New pattern.
(*neg_mul_imm_si2_uxtw): New pattern.
(*mulsi3_uxtw): New pattern.
(*maddsi_uxtw): New pattern.
(*msubsi_uxtw): New pattern.
(*mulsi_neg_uxtw): New pattern.
(*<su_optab>divsi3_uxtw): New pattern.
2012-12-17 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-12-17 James Greenhalgh <james.greenhalgh@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.c
(aarch64_autovectorize_vector_sizes): New.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
2012-12-06 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-12-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add new builtins.
* config/aarch64/aarch64-simd.md (simd_type): Add uzp.
(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): New.
* config/aarch64/aarch64.c (aarch64_evpc_trn): New.
(aarch64_evpc_uzp): Likewise.
(aarch64_evpc_zip): Likewise.
(aarch64_expand_vec_perm_const_1): Check for trn, zip, uzp patterns.
* config/aarch64/iterators.md (unspec): Add neccessary unspecs.
(PERMUTE): New.
(perm_insn): Likewise.
(perm_hilo): Likewise.
2012-12-06 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-12-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h
(aarch64_split_combinev16qi): New.
(aarch64_expand_vec_perm): Likewise.
(aarch64_expand_vec_perm_const): Likewise.
* config/aarch64/aarch64-simd.md (vec_perm_const<mode>): New.
(vec_perm<mode>): Likewise.
(aarch64_tbl1<mode>): Likewise.
(aarch64_tbl2v16qi): Likewise.
(aarch64_combinev16qi): New.
* config/aarch64/aarch64.c
(aarch64_vectorize_vec_perm_const_ok): New.
(aarch64_split_combinev16qi): Likewise.
(MAX_VECT_LEN): Define.
(expand_vec_perm_d): New.
(aarch64_expand_vec_perm_1): Likewise.
(aarch64_expand_vec_perm): Likewise.
(aarch64_evpc_tbl): Likewise.
(aarch64_expand_vec_perm_const_1): Likewise.
(aarch64_expand_vec_perm_const): Likewise.
(aarch64_vectorize_vec_perm_const_ok): Likewise.
(TARGET_VECTORIZE_VEC_PERM_CONST_OK): Likewise.
* config/aarch64/iterators.md
(unspec): Add UNSPEC_TBL, UNSPEC_CONCAT.
(V_cmp_result): Add mapping for V2DF.
2012-12-06 Yufeng Zhang <yufeng.zhang@arm.com>
Backport from mainline
2012-12-05 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_simd_mangle_map_entry): New
typedef.
(aarch64_simd_mangle_map): New table.
(aarch64_mangle_type): Locate and return the mangled name for
a given AdvSIMD vector type.
2012-12-05 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-12-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
2012-12-05 Yufeng Zhang <yufeng.zhang@arm.com>
Backport from mainline
2012-12-05 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_mangle_type): New function.
(TARGET_MANGLE_TYPE): Define.
2012-12-04 Marcus Shawcroft <marcus.shawcroft@arm.com>
Backport from mainline
2012-12-04 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_build_builtin_va_list): Set
TYPE_STUB_DECL.
2012-12-04 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.c (aarch64_simd_vector_alignment,
aarch64_simd_vector_alignment_reachable): New.
(TARGET_VECTOR_ALIGNMENT, TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE):
Define.
2012-12-03 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-10-30 James Greenhalgh <james.greenhalgh@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_simd_bsl<mode>_internal): New pattern.
(aarch64_simd_bsl<mode>): Likewise.
(aarch64_vcond_internal<mode>): Likewise.
(vcondu<mode><mode>): Likewise.
(vcond<mode><mode>): Likewise.
* config/aarch64/iterators.md (UNSPEC_BSL): Add to define_constants.
2012-12-03 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.c (aarch64_build_constant): Update prototype.
Call emit_move_insn instead of printing movi/movn/movz instructions.
Call gen_insv_immdi instead of printing movk instruction.
(aarch64_add_constant): Update prototype.
Generate RTL instead of printing add/sub instructions.
(aarch64_output_mi_thunk): Update calls to aarch64_build_constant
and aarch64_add_constant.
2012-11-30 Ian Bolton <ian.bolton@arm.com>
Backport from mainline
2012-09-26 Christophe Lyon <christophe.lyon@linaro.org>
* tree-ssa-math-opts.c (bswap_stats): Add found_16bit field.
(execute_optimize_bswap): Add support for builtin_bswap16.
2012-11-30 Ian Bolton <ian.bolton@arm.com>
Backport from mainline
2012-04-11 Eric Botcazou <ebotcazou@adacore.com>
PR target/52624
* doc/extend.texi (Other Builtins): Document __builtin_bswap16.
(PowerPC AltiVec/VSX Built-in Functions): Remove it.
* doc/md.texi (Standard Names): Add bswap.
* builtin-types.def (BT_UINT16): New primitive type.
(BT_FN_UINT16_UINT16): New function type.
* builtins.def (BUILT_IN_BSWAP16): New.
* builtins.c (expand_builtin_bswap): Add TARGET_MODE argument.
(expand_builtin) <BUILT_IN_BSWAP16>: New case. Pass TARGET_MODE to
expand_builtin_bswap.
(fold_builtin_bswap): Add BUILT_IN_BSWAP16 case.
(fold_builtin_1): Likewise.
(is_inexpensive_builtin): Likewise.
* optabs.c (expand_unop): Deal with bswap in HImode specially. Add
missing bits for bswap to libcall code.
* tree.c (build_common_tree_nodes): Build uint16_type_node.
* tree.h (enum tree_index): Add TI_UINT16_TYPE.
(uint16_type_node): New define.
* config/rs6000/rs6000-builtin.def (RS6000_BUILTIN_BSWAP_HI): Delete.
* config/rs6000/rs6000.c (rs6000_expand_builtin): Remove handling of
above builtin.
(rs6000_init_builtins): Likewise.
* config/rs6000/rs6000.md (bswaphi2): Add TARGET_POWERPC predicate.
2012-11-29 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-11-26 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_builtin_decls): New.
(aarch64_init_simd_builtins): Store declaration after builtin
initialisation.
(aarch64_init_builtins): Likewise.
(aarch64_builtin_decl): New.
* config/aarch64/aarch64-protos.h (aarch64_builtin_decl): New.
* config/aarch64/aarch64.c (TARGET_BUILTIN_DECL): Define.
2012-11-29 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2012-11-20 James Greenhalgh <james.greenhalgh@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_simd_builtin_type_bits): Rename to...
(aarch64_simd_builtin_type_mode): ...this, make sequential.
(aarch64_simd_builtin_datum): Refactor members.
(VAR1, VAR2, ..., VAR12): Update accordingly.
(aarch64_simd_builtin_data): Include from aarch64-simd-builtins.def.
(aarch64_builtins): Update accordingly.
(init_aarch64_simd_builtins): Refactor, rename to...
(aarch64_init_simd_builtins): ...this.
(aarch64_simd_builtin_compare): Remove.
(locate_simd_builtin_icode): Likewise.
* config/aarch64/aarch64-protos.h (aarch64_init_builtins): New.
(aarch64_expand_builtin): Likewise.
(aarch64_load_tp): Likewise.
* config/aarch64/aarch64-simd-builtins.def: New file.
* config/aarch64/aarch64.c (aarch64_init_builtins):
Move to aarch64-builtins.c.
(aarch64_expand_builtin): Likewise.
(aarch64_load_tp): Remove static designation.
* config/aarch64/aarch64.h
(aarch64_builtins): Move to aarch64-builtins.c.
2012-11-22 Marcus Shawcroft <marcus.shawcroft@arm.com>
* doc/md.texi (AArch64 family): Remove Utf.
2012-11-22 Ian Bolton <ian.bolton@arm.com>
Backport from mainline
2012-11-22 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (bswaphi2): New pattern.
2012-11-21 Marcus Shawcroft <marcus.shawcroft@arm.com>
* Makefile.in (gengtype-lex.o): Add dependency on $(BCONFIG_H).
2012-11-21 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c
(aarch64_output_mi_thunk): Use 4.7 API for plus_constant.
2012-11-20 Sofiane Naci <sofiane.naci@arm.com>
Backport from mainline
2012-11-20 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md
(define_attr "sync_*"): Remove.
(define_attr "length"): Update.
Include atomics.md.
* config/aarch64/aarch64-protos.h
(aarch64_expand_compare_and_swap): Add function prototype.
(aarch64_split_compare_and_swap): Likewise.
(aarch64_split_atomic_op): Likewise.
(aarch64_expand_sync): Remove function prototype.
(aarch64_output_sync_insn): Likewise.
(aarch64_output_sync_lock_release): Likewise.
(aarch64_sync_loop_insns): Likewise.
(struct aarch64_sync_generator): Remove.
(enum aarch64_sync_generator_tag): Likewise.
* config/aarch64/aarch64.c
(aarch64_legitimize_sync_memory): Remove function.
(aarch64_emit): Likewise.
(aarch64_insn_count): Likewise.
(aarch64_output_asm_insn): Likewise.
(aarch64_load_store_suffix): Likewise.
(aarch64_output_sync_load): Likewise.
(aarch64_output_sync_store): Likewise.
(aarch64_output_op2): Likewise.
(aarch64_output_op3): Likewise.
(aarch64_output_sync_loop): Likewise.
(aarch64_get_sync_operand): Likewise.
(aarch64_process_output_sync_insn): Likewise.
(aarch64_output_sync_insn): Likewise.
(aarch64_output_sync_lock_release): Likewise.
(aarch64_sync_loop_insns): Likewise.
(aarch64_call_generator): Likewise.
(aarch64_expand_sync): Likewise.
(* emit_f): Remove variable.
(aarch64_insn_count): Likewise.
(FETCH_SYNC_OPERAND): Likewise.
(aarch64_emit_load_exclusive): New function.
(aarch64_emit_store_exclusive): Likewise.
(aarch64_emit_unlikely_jump): Likewise.
(aarch64_expand_compare_and_swap): Likewise.
(aarch64_split_compare_and_swap): Likewise.
(aarch64_split_atomic_op): Likewise.
* config/aarch64/iterators.md
(atomic_sfx): New mode attribute.
(atomic_optab): New code attribute.
(atomic_op_operand): Likewise.
(atomic_op_str): Likewise.
(syncop): Rename to atomic_op.
* config/aarch64/sync.md: Delete.
* config/aarch64/atomics.md: New file.
2012-11-19 Sofiane Naci <sofiane.naci@arm.com>
Backport from mainline
2012-11-19 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.c
(aarch64_output_mi_thunk): Refactor to generate RTL patterns.
2012-11-13 Ian Bolton <ian.bolton@arm.com>
Backport from mainline
2012-11-12 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (cmov<mode>_insn): Emit CSINC when
one of the alternatives is constant 1.
* config/aarch64/constraints.md: New constraint.
* config/aarch64/predicates.md: Rename predicate
aarch64_reg_zero_or_m1 to aarch64_reg_zero_or_m1_or_1.
2012-11-13 Ian Bolton <ian.bolton@arm.com>
Backport from mainline
2012-11-12 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (*compare_neg<mode>): New pattern.
2012-11-08 Yufeng Zhang <yufeng.zhang@arm.com>
Revert:
2012-11-07 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue): add the missing
argument 'Pmode' to the 'plus_constant' call.
2012-11-07 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue): add the missing
argument 'Pmode' to the 'plus_constant' call.
2012-11-07 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue): For the
load-pair with writeback instruction, replace
aarch64_set_frame_expr with add_reg_note (REG_CFA_ADJUST_CFA);
add new local variable 'cfa_reg' and use it.
2012-10-17 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md (<optab><mode>3): Update constraint
for operand 0.
Update scheduling attribute for the second alternative.
2012-10-16 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vmla_lane_f32, vmla_lane_s16,
vmla_lane_s32, vmla_lane_u16, vmla_lane_u32, vmlal_lane_s16,
vmlal_lane_s32, vmlal_lane_u16, vmlal_lane_u32,
vmls_lane_s16, vmls_lane_s32, vmls_lane_u16, vmls_lane_u32,
vmlsl_lane_s16, vmlsl_lane_s32, vmlsl_lane_u16,
vmlsl_lane_u32, vmul_lane_f32, vmul_lane_s16, vmul_lane_s32,
vmul_lane_u16, vmul_lane_u32, vmull_lane_s16, vmull_lane_s32,
vmull_lane_u16, vmull_lane_u32, vmulq_lane_f32, vmulq_lane_f64,
vmulq_lane_s16, vmulq_lane_s32, vmulq_lane_u16, vmulq_lane_u32,
vqdmlal_lane_s16, vqdmlal_lane_s32, vqdmlalh_lane_s16,
vqdmlsl_lane_s16, vqdmlsl_lane_s32, vqdmulh_lane_s16, vqdmulh_lane_s32,
vqdmulhq_lane_s16, vqdmulhq_lane_s32, vqdmull_lane_s16,
vqdmull_lane_s32, vqrdmulh_lane_s16, vqrdmulh_lane_s32,
vqrdmulhq_lane_s16, vqrdmulhq_lane_s32): Update prototype and
implementation.
2012-10-16 Ian Bolton <ian.bolton@arm.com>
* gcc/config/aarch64/aarch64.md
(<optab><ALLX:mode>_shft_<GPI:mode>): Restrict operands.
2012-10-16 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_split_doubleword_move):
Rename to aarch64_split_128bit_move.
(aarch64_split_128bit_move_p): New.
* config/aarch64/aarch64.c (aarch64_split_doubleword_move):
Rename to aarch64_split_128bit_move.
(aarch64_split_128bit_move_p): New.
* config/aarch64/aarch64.md: Adjust TImode move split.
2012-10-15 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Add predefine for
AArch64 code models.
2012-10-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vqdmlalh_lane_s16, vqdmlalh_s16,
vqdmlals_lane_s32, vqdmlals_s32, vqdmlslh_lane_s16, vqdmlslh_s16,
vqdmlsls_lane_s32, vqdmlsls_s32): Remove old temporary inline asm
implementations.
2012-10-05 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md (*fnmadd<mode>4): Add missing
constraints.
2012-10-04 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h: Rename vqml<as>l<sh>_* to
vqdml<as>l<sh>_*.
2012-10-04 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vfma_n_f32, vfmaq_n_f32, vfmaq_n_f64): New.
2012-10-04 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vbslq_f64): Fix parameter type.
2012-10-02 Tejas Belagod <tejas.belagod@arm.com>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* reload.c (find_reloads_subreg_address): Remove FORCE_REPLACE
parameter. Always replace normal subreg with memory reference
whenever possible. Return NULL otherwise.
(find_reloads_toplev): Always call find_reloads_subreg_address
for subregs of registers equivalent to a memory location.
Only recurse further if find_reloads_subreg_address fails.
(find_reloads_address_1): Only call find_reloads_subreg_address
for subregs of registers equivalent to a memory location.
Properly handle failure of find_reloads_subreg_address.
2012-10-01 Ian Bolton <ian.bolton@arm.com>
Richard Henderson <rth@redhat.com>
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Fix a
functional typo and refactor code in switch statement.
* config/aarch64/aarch64.md (add_losym): Handle symbol + offset.
* config/aarch64/predicates.md (aarch64_tls_ie_symref): Match const.
(aarch64_tls_le_symref): Likewise.
2012-09-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): Remove
duplicate.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.c (aarch64_shift_truncation_mask): Define.
(TARGET_SHIFT_TRUNCATION_MASK): Define.
* config/aarch64/aarch64.h (SHIFT_COUNT_TRUNCATED): Conditionalize on
TARGET_SIMD.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vrshrn_high_n_s16, vrshrn_high_n_s32)
(vrshrn_high_n_s64, vrshrn_high_n_u16, vrshrn_high_n_u32)
(vrshrn_high_n_u64, vshrn_high_n_s16, vshrn_high_n_s32)
(vshrn_high_n_s32, vshrn_high_n_s64, vshrn_high_n_u16, vshrn_high_n_u32)
(vshrn_high_n_u64): Fix template to reference correct operands.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vmovq_n_f64): Add.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vfmaq_lane_f64): Fix prototype and
assembler template accordingly.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_simd_imm_scalar_p): Declare.
* config/aarch64/aarch64.c (aarch64_simd_imm_scalar_p): New.
* config/aarch64/aarch64.md (*movdi_aarch64): Add alternative for moving
valid scalar immediate into a Advanved SIMD D-register.
* config/aarch64/constraints.md (Dd): New.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_cm<cmp><mode>): Tighten
predicate for operand 2 of the compare pattern to accept register
or zero.
* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Split Q-reg
vector value move contained in general registers.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.c (aarch64_simd_expand_builtin): Expand binary
operations' constant operand only if the predicate allows it.
2012-09-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_data):
Populate intrinsic table with struct loads and store descriptors.
(init_aarch64_simd_builtins): Remove cruft.
(aarch64_simd_expand_builtin): Expand the builtins.
* config/aarch64/aarch64-modes.def: Define new vector modes for register
lists.
* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_move): New.
(aarch64_simd_mem_operand_p): New.
(aarch64_simd_imm_zero_p): New.
(aarch64_output_move_struct): New.
(aarch64_simd_disambiguate_copy): New.
* config/aarch64/aarch64-simd.md (simd_mode): Add OI, CI and XI to the
list.
(mov<mode>): Tighten predicates for simd operand.
(movmisalign<mode>): Likewise.
(*aarch64_simd_mov<mode>): Tighten predicates and constraints for simd
operands.
(*aarch64_combinez<mode>): New.
(vec_load_lanesoi<mode>, vec_store_lanesoi<mode>)
(vec_load_lanesci<mode>, vec_store_lanesci<mode>)
(vec_load_lanesxi<mode>)
(vec_store_lanesxi<mode>, mov<mode>, *aarch64_mov<mode>)
(aarch64_ld2<mode>_dreg, aarch64_ld3<mode>_dreg)
(aarch64_ld4<mode>_dreg, aarch64_ld<VSTRUCT:nregs><VDC:mode>)
(aarch64_ld<VSTRUCT:nregs><VQ:mode>)
(aarch64_get_dreg<VSTRUCT:mode><VDC:mode>)
(aarch64_get_qreg<VSTRUCT:mode><VQ:mode>, aarch64_st2<mode>_dreg)
(aarch64_st3<mode>_dreg, aarch64_st4<mode>_dreg)
(aarch64_st<VSTRUCT:nregs><VDC:mode>)
(aarch64_st<VSTRUCT:nregs><VQ:mode>)
(aarch64_set_qreg<VSTRUCT:mode><VQ:mode>): New expanders and patterns
for vector struct loads and stores.
* config/aarch64/aarch64.c (aarch64_vect_struct_mode_p): New.
(aarch64_vector_mode_p): New.
(aarch64_array_mode_supported_p): New.
(aarch64_hard_regno_mode_ok): Check that reglists don't go out of
range and don't allocate general regs to large int modes.
(aarch64_classify_address): Restrict addressing modes of large int
modes to same as SIMD addressing modes.
(aarch64_print_operand): Print specifiers for register lists.
(aarch64_legitimize_reload_address): Treat large int modes simliar to
SIMD modes.
(aarch64_class_max_nregs): Return the correct max number of register
for a particular mode.
(aarch64_legitimate_constant_p): Do not allow large int modes
immediate values.
(aarch64_simd_imm_zero_p): New.
(aarch64_simd_mem_operand_p): Check if mem operand has a valid SIMD
addressing mode.
(aarch64_simd_disambiguate_copy): Copy values that span multiple
register with and without overlapping.
(aarch64_simd_attr_length_move): Length of instruction sequence
depending on the mode.
* config/aarch64/aarch64.h (AARCH64_VALID_SIMD_QREG_MODE): New.
* config/aarch64/aarch64.md (UNSPEC_VSTRUCTDUMMY, UNSPEC_LD2)
(UNSPEC_LD3, UNSPEC_LD4, UNSPEC_ST2, UNSPEC_ST3, UNSPEC_ST4): New.
* config/aarch64/arm_neon.h: Remove assembler implementation of vector
struct loads and stores and add new C implementations.
* config/aarch64/constraints.md (Utv): New memory constraint for SIMD
memory operands.
(Dz): New.
* config/aarch64/iterators.md (VDIC, VSTRUCT, DX): New mode iterators.
(Vendreg, nregs, VRL2, VRL3, VRL4, VSTRUCT_DREG): New mode attributes.
* config/aarch64/predicates.md (aarch64_simd_struct_operand): New.
(aarch64_simd_general_operand): New.
(aarch64_simd_nonimmediate_operand): New.
(aarch64_simd_reg_or_zero): New.
(aarch64_simd_imm_zero): New.
2012-09-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/aarch64/aarch64.md: Make unspec and unspecv constants
c_enums and split out to iterators.md and sync.md.
* config/aarch64/iterators.md: Add SIMD unspec c_enums.
* config/aarch64/sync.md: Add sync unspecv c_enums.
2012-09-18 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO.
* config/aarch64/aarch64.md (clrsb<mode>2): New pattern.
* config/aarch64/aarch64.md (rbit<mode>2): New pattern.
* config/aarch64/aarch64.md (ctz<mode>2): New pattern.
2012-09-18 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64-linux.h (MULTIARCH_TUPLE): Remove.
(STANDARD_STARTFILE_PREFIX_1): Likewise.
(STANDARD_STARTFILE_PREFIX_2): Likewise.
2012-09-17 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (csinc3<mode>): Turn into named
pattern.
* config/aarch64/aarch64.md (ffs<mode>2): New pattern.
2012-09-17 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (fmsub<mode>4): Rename fnma<mode>4.
* config/aarch64/aarch64.md (fnmsub<mode>4): Rename fms<mode>4.
* config/aarch64/aarch64.md (fnmadd<mode>4): Rename fnms<mode>4.
* config/aarch64/aarch64.md (*fnmadd<mode>4): New pattern.
2012-09-11 Sofiane Naci <sofiane.naci@arm.com>
* config.sub: Update to version 2010-08-18.
* config.guess: Update to version 2010-08-14.
2012-09-10 James Greenhalgh <james.greenhalgh@arm.com>
Richard Earnshaw <rearnsha@arm.com>
* common/config/aarch64/aarch64-common.c
(aarch_option_optimization_table): New.
(TARGET_OPTION_OPTIMIZATION_TABLE): Define.
* gcc/config.gcc ([aarch64] target_has_targetm_common): Set to yes.
* gcc/config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): New definition.
* gcc/config/aarch64/aarch64.c (TARGET_MIN_ANCHOR_OFFSET): Define.
(TARGET_MAX_ANCHOR_OFFSET): Likewise.
2012-09-10 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_classify_address):
Allow 16 byte modes in constant pool.
2012-07-23 Ian Bolton <ian.bolton@arm.com>
* gcc/config/aarch64/aarch64.c (aarch64_print_operand): Use
aarch64_classify_symbolic_expression for classifying operands.
* gcc/config/aarch64/aarch64.c
(aarch64_classify_symbolic_expression): New function.
* gcc/config/aarch64/aarch64.c (aarch64_symbolic_constant_p):
New function.
* gcc/config/aarch64/predicates.md (aarch64_valid_symref):
Symbol with constant offset is a valid symbol reference.
2012-07-17 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c
(aarch64_regno_ok_for_index_p): Handle NULL reg_renumber.
(aarch64_regno_ok_for_base_p): Likewise.
(offset_7bit_signed_scaled_p): New.
(offset_9bit_signed_unscaled_p): New.
(offset_12bit_unsigned_scaled_p): New.
(aarch64_classify_address): Replace pair_p with allow_reg_index_p.
Conservative test for valid TImode and TFmode addresses. Use
offset_7bit_signed_scaled_p offset_9bit_signed_unscaled_p and
offset_12bit_unsigned_scaled_p. Remove explicit TImode and TFmode
tests.
* config/aarch64/aarch64.md (movti_aarch64): Replace 'm' with 'Ump'.
(movtf_aarch64): Replace 'm' with 'Ump', replace 'Utf' with 'm'.
* config/aarch64/constraints.md (Utf): Remove.
(Ump)
2012-07-17 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs):
Move misplaced parenthesis.
2012-07-17 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>):
Do not emit lsl for a shift of 0.
(*aarch64_simd_mov<mode>): Likwise.
2012-07-04 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-linux.h (LINUX_TARGET_LINK_SPEC): Rename
LINUX_DYNAMIC_LINKER to GLIBC_DYNAMIC_LINKER.
2012-06-29 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.h (aarch64_cmodel): Fix enum name.
2012-06-22 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>,
aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal,
aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal,
aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull_lane<mode>_internal, aarch64_sqdmull_lane<mode>,
aarch64_sqdmull_laneq<mode>, aarch64_sqdmull2_lane<mode>_internal,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Change the
constraint of the indexed operand to use <vwl> instead of w.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs): Add case for
FP_LO_REGS class.
(aarch64_regno_regclass): Return FP_LO_REGS if register in V0 - V15.
(aarch64_secondary_reload): Change condition to check for both FP reg
classes.
(aarch64_class_max_nregs): Add case for FP_LO_REGS.
* config/aarch64/aarch64.h (reg_class): New register class FP_LO_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(FP_LO_REGNUM_P): New.
* config/aarch64/aarch64.md (V15_REGNUM): New.
* config/aarch64/constraints.md (x): New register constraint.
* config/aarch64/iterators.md (vwx): New.
2012-06-22 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vpadd_f64): Remove.
2012-06-22 Sofiane Naci <sofiane.naci@arm.com>
[AArch64] Update LINK_SPEC.
* config/aarch64/aarch64-linux.h (LINUX_TARGET_LINK_SPEC): Remove
%{version:-v}, %{b} and %{!dynamic-linker}.
2012-06-22 Sofiane Naci <sofiane.naci@arm.com>
[AArch64] Replace sprintf with snprintf.
* config/aarch64/aarch64.c
(aarch64_elf_asm_constructor): Replace sprintf with snprintf.
(aarch64_elf_asm_destructor): Likewise.
(aarch64_output_casesi): Likewise.
(aarch64_output_asm_insn): Likewise.
* config/aarch64/aarch64-builtins.c (init_aarch64_simd_builtins):
Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Replace
sprintf with snprintf, and fix code layout.
2012-06-22 Sofiane Naci <sofiane.naci@arm.com>
[AArch64] Fix documentation layout.
* doc/invoke.texi: Fix white spaces after dots.
Change aarch64*be-*-* to aarch64_be-*-*.
Add documentation for -mcmodel=tiny.
(-march): Fix formatting.
(-mcpu): Likewise.
(-mtune): Rephrase.
(-march and -mcpu feature modifiers): New subsection.
2012-06-22 Sofiane Naci <sofiane.naci@arm.com>
[AArch64] Use Enums for code models option selection.
* config/aarch64/aarch64-elf-raw.h (AARCH64_DEFAULT_MEM_MODEL): Delete.
* config/aarch64/aarch64-linux.h (AARCH64_DEFAULT_MEM_MODEL): Delete.
* config/aarch64/aarch64-opts.h (enum aarch64_code_model): New.
* config/aarch64/aarch64-protos.h: Update comments.
* config/aarch64/aarch64.c: Update comments.
(aarch64_default_mem_model): Rename to aarch64_code_model.
(aarch64_expand_mov_immediate): Remove error message.
(aarch64_select_rtx_section): Remove assertion and update comment.
(aarch64_override_options): Move memory model initialization from here.
(struct aarch64_mem_model): Delete.
(aarch64_memory_models[]): Delete.
(initialize_aarch64_memory_model): Rename to
initialize_aarch64_code_model and update.
(aarch64_classify_symbol): Handle AARCH64_CMODEL_TINY and
AARCH64_CMODEL_TINY_PIC
* config/aarch64/aarch64.h
(enum aarch64_memory_model): Delete.
(aarch64_default_mem_model): Rename to aarch64_cmodel.
(HAS_LONG_COND_BRANCH): Update.
(HAS_LONG_UNCOND_BRANCH): Update.
* config/aarch64/aarch64.opt
(cmodel): New.
(mcmodel): Update.
2012-06-22 Sofiane Naci <sofiane.naci@arm.com>
[AArch64] Use Enums for TLS option selection.
* config/aarch64/aarch64-opts.h (enum aarch64_tls_type): New.
* config/aarch64/aarch64.c
(aarch64_tls_dialect): Remove.
(tls_symbolic_operand_type): Update comment.
(aarch64_override_options): Remove TLS option setup code.
* config/aarch64/aarch64.h
(TARGET_TLS_TRADITIONAL): Remove.
(TARGET_TLS_DESC): Update definition.
(enum tls_dialect): Remove.
(enum tls_dialect aarch64_tls_dialect) Remove.
* config/aarch64/aarch64.opt
(tls_type): New.
(mtls-dialect): Update.
2012-05-25 Ian Bolton <ian.bolton@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen,thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* common/config/aarch64/aarch64-common.c: New file.
* config/aarch64/aarch64-arches.def: New file.
* config/aarch64/aarch64-builtins.c: New file.
* config/aarch64/aarch64-cores.def: New file.
* config/aarch64/aarch64-elf-raw.h: New file.
* config/aarch64/aarch64-elf.h: New file.
* config/aarch64/aarch64-generic.md: New file.
* config/aarch64/aarch64-linux.h: New file.
* config/aarch64/aarch64-modes.def: New file.
* config/aarch64/aarch64-option-extensions.def: New file.
* config/aarch64/aarch64-opts.h: New file.
* config/aarch64/aarch64-protos.h: New file.
* config/aarch64/aarch64-simd.md: New file.
* config/aarch64/aarch64-tune.md: New file.
* config/aarch64/aarch64.c: New file.
* config/aarch64/aarch64.h: New file.
* config/aarch64/aarch64.md: New file.
* config/aarch64/aarch64.opt: New file.
* config/aarch64/arm_neon.h: New file.
* config/aarch64/constraints.md: New file.
* config/aarch64/gentune.sh: New file.
* config/aarch64/iterators.md: New file.
* config/aarch64/large.md: New file.
* config/aarch64/predicates.md: New file.
* config/aarch64/small.md: New file.
* config/aarch64/sync.md: New file.
* config/aarch64/t-aarch64-linux: New file.
* config/aarch64/t-aarch64: New file.
* config.gcc: Add AArch64.
* configure.ac: Add AArch64 TLS support detection.
* configure: Regenerate.
* doc/extend.texi (Complex Numbers): Add AArch64.
* doc/invoke.texi (AArch64 Options): New.
* doc/md.texi (Machine Constraints): Add AArch64.
* read-rtl.c (rtx_list): New data structure.
(int_iterator_mapping): New data structure.
(int_iterator_data): New. List of int iterator details.
(num_int_iterator_data): New.
(ints): New group list.
(find_int): New. Find an int iterator in a list.
(dummy_uses_int_iterator): Dummy handle.
(dummy_apply_int_iterator): Dummy handle.
(uses_int_iterator_p): New.
(apply_iterator_to_rtx): Handle case for rtx field specifier 'i'.
(initialize_iterators): Initialize int iterators data struts.
(find_int_iterator): New. Find an Int iterators from a hash-table.
(add_int_iterator: Add int iterator to database.
(read_rtx): Parse and read int iterators mapping and attributes.
Initialize int iterators group's hash-table. Memory management.
(read_rtx_code): Handle case for rtl field specifier 'i'.
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