1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
|
2014-12-11 Michael Meissner <meissner@linux.vnet.ibm.com>
Merge up to ibm/gcc-4_9-branch, subversion id 218646.
* REVISION: Update subversion id.
2014-12-09 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_secondary_reload): Clear entire
secondary_reload_info structure instead of just setting a few
fields to 0. Add an assertion checking that the secondary reload
function is in range.
2014-12-05 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_emit_move): Do not split TFmode
constant moves if -mupper-regs-df.
* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Optimize moving
0.0L to TFmode.
(movtd_64bit_nodm): Likewise.
(mov<mode>_32bit, FMOVE128 case): Likewise.
2014-12-02 Michael Meissner <meissner@linux.vnet.ibm.com>
Clone branch from at 8.0 branch, subversion id 218285 (FSF
subversion id 217046)
* REVISION: Update file.
[gcc, patch #1]
2014-11-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (easy_fp_constant): Delete redunant
tests for 0.0.
[gcc, patch #2]
2014-11-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_R): Move secondary reload support
insns to rs6000.md from vector.md.
(reload_<VEC_R:mode>_<P:mptrsize>_store): Likewise.
(reload_<VEC_R:mode>_<P:mptrsize>_load): Likewise.
(vec_reload_and_plus_<mptrsize>): Likewise.
* config/rs6000/rs6000.md (RELOAD): New mode iterator for all of
the types that have secondary reload address support to load up a
base register.
(reload_<RELOAD:mode>_<P:mptrsize>_store): Move the reload
handlers here from vector.md, and expand the types we generate
reload handlers for.
(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
(vec_reload_and_plus_<mptrsize>): Likewise.
[gcc, patch #3]
2014-11-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_float<VSi><mode>2): Only provide the
vector forms of the instructions. Move VSX scalar forms to
rs6000.md, and add support for -mupper-regs-sf.
(vsx_floatuns<VSi><mode>2): Likewise.
(vsx_fix_trunc<mode><VSi>2): Likewise.
(vsx_fixuns_trunc<mode><VSi>2): Likewise.
(vsx_float_fix_<mode>2): Delete DF version, rename to
vsx_float_fix_v2df2.
(vsx_float_fix_v2df2): Likewise.
* config/rs6000/rs6000.md (Fa): New mode attribute to give
constraint for the Altivec registers for a type.
(extendsfdf2_fpr): Use correct constraint.
(copysign<mode>3_fcpsgn): For SFmode, use correct xscpsgndp
instruction.
(floatsi<mode>2_lfiwax): Add support for -mupper-regs-{sf,df}.
Generate the non-VSX instruction if all registers were FPRs. Do
not use the patterns in vsx.md for scalar operations.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(fix_trunc<mode>di2_fctidz): Likewise.
(fixuns_trunc<mode>di2_fctiduz): Likewise.
(fctiwz_<mode>): Likewise.
(fctiwuz_<mode>): Likewise.
(friz): Likewise.
(floatdidf2_fpr): Likewise.
(floatdidf2_mem): Likewise.
(floatunsdidf2): Likewise.
(floatunsdidf2_fcfidu): Likewise.
(floatunsdidf2_mem): Likewise.
(floatdisf2_fcfids): Likewise.
(floatdisf2_mem): Likewise.
(floatdisf2_internal1): Add explicit test for not FCFIDS to make
it more obvious that the code is for pre-ISA 2.06 machines.
(floatdisf2_internal2): Likewise.
(floatunsdisf2_fcfidus): Add support for -mupper-regs-{sf,df}.
Generate the non-VSX instruction if all registers were FPRs. Do
not use the patterns in vsx.md for scalar operations.
(floatunsdisf2_mem): Likewise.
[gcc, patch #4]
2014-11-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (RELOAD_REG_AND_M16): Add support for
Altivec style vector loads that ignore the bottom 3 bits of the
address.
(rs6000_debug_addr_mask): New function to print the addr_mask
values if debugging.
(rs6000_debug_print_mode): Call rs6000_debug_addr_mask to print
out addr_mask.
(rs6000_setup_reg_addr_masks): Add support for Altivec style
vector loads that ignore the bottom 3 bits of the address.
(rs6000_init_hard_regno_mode_ok): Rework DFmode support if
-mupper-regs-df. Add support for -mupper-regs-sf. Rearrange code
placement for direct move support.
(rs6000_option_override_internal): Add checks for -mupper-regs-df
requiring -mvsx, and -mupper-regs-sf requiring -mpower8-vector.
(rs6000_secondary_reload_fail): Add ATTRIBUTE_NORETURN.
[gcc, patch #5]
2014-11-11 Michael Meissner <meissner@linux.vnet.ibm.com>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/rs6000/rs6000.c (rs6000_secondary_reload_toc_costs):
Helper function to identify costs of a TOC load for secondary
reload support.
(rs6000_secondary_reload_memory): Helper function for secondary
reload, to determine if a particular memory operation is directly
handled by the hardware, or if it needs support from secondary
reload to create a valid address.
(rs6000_secondary_reload): Rework code, to be clearer. If the
appropriate -mupper-regs-{sf,df} is used, use FPR registers to
reload scalar values, since the FPR registers have D-form
addressing. Move most of the code handling memory to the function
rs6000_secondary_reload_memory, and use the reg_addr structure to
determine what type of address modes are supported. Print more
debug information if -mdebug=addr.
(rs6000_secondary_reload_inner): Rework entire function to be more
general. Use the reg_addr bits to determine what type of
addressing is supported.
(rs6000_preferred_reload_class): Rework. Move constant handling
into a single place. Prefer using FLOAT_REGS for scalar floating
point.
(rs6000_secondary_reload_class): Use a FPR register to move a
value from an Altivec register to a GPR, and vice versa. Move VSX
handling above traditional floating point.
* config/rs6000/rs6000.md (mov<mode>_hardfloat, FMOVE32 case):
Delete some spaces in the constraints.
(DF->DF move peephole2): Disable if -mupper-regs-{sf,df} to
allow using FPR registers to load/store an Altivec register for
scalar floating point types.
(SF->SF move peephole2): Likewise.
[gcc, patch #6]
2014-11-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.opt (-mupper-regs-df): Make option public.
(-mupper-regs-sf): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__UPPER_REGS_DF__ if -mupper-regs-df. Define __UPPER_REGS_SF__ if
-mupper-regs-sf.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs-{sf,df}.
[gcc, patch #8]
2014-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (memory_fp_constant): New predicate
to return true if the operand is a floating point constant that
must be put into the constant pool, before register allocation
occurs.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Enable
-mupper-regs-df by default.
(ISA_2_7_MASKS_SERVER): Enable -mupper-regs-sf by default.
(POWERPC_MASKS): Add -mupper-regs-{sf,df} as options set by the
various -mcpu=... options.
(power7 cpu): Enable -mupper-regs-df by default.
* config/rs6000/rs6000.opt (-mupper-regs): New combination option
that sets -mupper-regs-sf and -mupper-regs-df by default if the
cpu supports the instructions.
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Allow
pre-increment and pre-decrement on floating point, even if the
-mupper-regs-{sf,df} options were used.
(rs6000_option_override_internal): If -mupper-regs, set both
-mupper-regs-sf and -mupper-regs-df, depending on the underlying
cpu.
* config/rs6000/rs6000.md (DFmode splitter): Add a define_split to
move floating point constants to the constant pool before register
allocation. Normally constants are put into the pool immediately,
but -ffast-math delays putting them into the constant pool for the
reciprocal approximation support.
(SFmode splitter): Likewise.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs.
[pr63965 fix]
2014-11-20 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
[pr64019 fix]
2014-12-01 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/64019
* config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Do
not create LO_SUM address for constant addresses if the type can
go in Altivec registers.
|
