diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-09 16:02:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-09 16:16:22 +0100 |
| commit | 9f0d0c373f667739445aca08677ff6c29dbb2379 (patch) | |
| tree | 7bc15b48d9b3d82a5fec781dfe034c66084238f8 | |
| parent | 5008398952a83df4a39cdbdc29772fea9f4e7abd (diff) | |
hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure
Move the GICv3 parent_irq and parent_fiq pointers into the
GICv3CPUState structure rather than giving them their own array.
This will make it easy to assert the IRQ and FIQ lines for a
particular CPU interface without having to know or calculate
the CPU index for the GICv3CPUState we are working on.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
| -rw-r--r-- | hw/intc/arm_gicv3_common.c | 7 | ||||
| -rw-r--r-- | include/hw/intc/arm_gicv3_common.h | 5 |
2 files changed, 4 insertions, 8 deletions
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index bf6949f8cd..1557833173 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -72,14 +72,11 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; qdev_init_gpio_in(DEVICE(s), handler, i); - s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq)); - s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq)); - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_irq[i]); + sysbus_init_irq(sbd, &s->cpu[i].parent_irq); } for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_fiq[i]); + sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); } memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index bd364a7e02..cc6ac74e63 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -134,6 +134,8 @@ typedef struct GICv3CPUState GICv3CPUState; struct GICv3CPUState { GICv3State *gic; CPUState *cpu; + qemu_irq parent_irq; + qemu_irq parent_fiq; /* Redistributor */ uint32_t level; /* Current IRQ level */ @@ -168,9 +170,6 @@ struct GICv3State { SysBusDevice parent_obj; /*< public >*/ - qemu_irq *parent_irq; - qemu_irq *parent_fiq; - MemoryRegion iomem_dist; /* Distributor */ MemoryRegion iomem_redist; /* Redistributors */ |