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authoredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2008-03-01 17:25:33 +0000
committeredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2008-03-01 17:25:33 +0000
commitbbaf29c76994ef762523bc8893a88cac701c87e7 (patch)
tree5d39be7749d8f177f79402bca5da5bc2388e27f8 /target-cris
parentbffd92fed9393021200915586be8d1b0cc711286 (diff)
* target-cris/op.c: Make sure the bit-test insn only updates the XNZ flags.
* target-cris/helper.c: Update ERP for user-mode simulation aswell. * hw/etraxfs_timer.c: Support multiple timers. * hw/etraxfs_ser.c: Multiple ports, the data just goes to stdout. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4004 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris')
-rw-r--r--target-cris/helper.c18
-rw-r--r--target-cris/op.c7
2 files changed, 14 insertions, 11 deletions
diff --git a/target-cris/helper.c b/target-cris/helper.c
index e7eac08e68..7482e0893f 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -32,22 +32,23 @@
void do_interrupt (CPUState *env)
{
- env->exception_index = -1;
+ env->exception_index = -1;
+ env->pregs[PR_ERP] = env->pc;
}
int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
{
- env->exception_index = 0xaa;
- env->debug1 = address;
- cpu_dump_state(env, stderr, fprintf, 0);
- printf("%s addr=%x env->pc=%x\n", __func__, address, env->pc);
- return 1;
+ env->exception_index = 0xaa;
+ env->debug1 = address;
+ cpu_dump_state(env, stderr, fprintf, 0);
+ env->pregs[PR_ERP] = env->pc;
+ return 1;
}
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
- return addr;
+ return addr;
}
#else /* !CONFIG_USER_ONLY */
@@ -61,7 +62,6 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
address &= TARGET_PAGE_MASK;
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-// printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu);
miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
if (miss)
{
@@ -73,7 +73,6 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
{
phy = res.phy;
}
-// printf ("a=%x phy=%x\n", address, phy);
return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
}
@@ -113,7 +112,6 @@ void do_interrupt(CPUState *env)
break;
case EXCP_MMU_MISS:
-// printf ("MMU miss\n");
irqnum = 4;
ebp = env->pregs[PR_EBP];
isr = ldl_code(ebp + irqnum * 4);
diff --git a/target-cris/op.c b/target-cris/op.c
index 36cfa3f20c..aeb80de4a3 100644
--- a/target-cris/op.c
+++ b/target-cris/op.c
@@ -967,6 +967,8 @@ void OPPROTO op_btst_T0_T1 (void)
The N flag is set according to the selected bit in the dest reg.
The Z flag is set if the selected bit and all bits to the right are
zero.
+ The X flag is cleared.
+ Other flags are left untouched.
The destination reg is not affected.*/
unsigned int fz, sbit, bset, mask, masked_t0;
@@ -975,8 +977,11 @@ void OPPROTO op_btst_T0_T1 (void)
mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
masked_t0 = T0 & mask;
fz = !(masked_t0 | bset);
+
+ /* Clear the X, N and Z flags. */
+ T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
/* Set the N and Z flags accordingly. */
- T0 = (bset << 3) | (fz << 2);
+ T0 |= (bset << 3) | (fz << 2);
RETURN();
}