Age | Commit message (Collapse) | Author |
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The boot wrapper suffers from a few problems when it comes to
setup the secondary CPUs, as only the boot CPU hits the non-secure
setup path.
Move the non-secure setup to the common path, taking care of only
configuring GICD_IGROUPR0 on secondary CPUs.
Also set bit 18 in NSACR to allow the SMP bit to be set in the
Auxiliary Control Register (A15 specific).
Tested on A15 model v6.1.70.
Cc: Christopher Dall <cdall@cs.columbia.edu>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Use callee-save by implementing a small stack space in the monitor
instead.
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This API allows only setting the HVBAR and switching to non-secure mode:
The non-secure privileged mode needs only write access to the HVBAR to
configure its own hypervisor state, given that the MMU is disabled in
Hyp mode.
All callers can switch to non-secure mode, but setting the HVBAR
requires VTTBR.VMID==0, otherwise the call simply returns.
Overall API convention:
- r7 == 0xfffffff0
- r0 the new HVBAR value
- r4-r11 are preserved
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Only set CROSS_COMPILE if it's not already set in the environment and
set it to arm-unknown-eabi- per default.
Set "arch_extension sec" in boot.S code to allow newer compilers to
accept the smc #0 instruction.
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Move the writing of the HVBAR to the top, so we can simply strip off the rest
afterwards.
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These registers must also be initialized by a hypervisor for it to run code in
HYP mode.
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SMC API is this:
- r7: monitor call number
- r0-r3: arguments
- r0-r1: return value
- r4-r11: preserved
SMC Permissions:
- All calls except switching to non-secure mode, requires VTTBR.VMID == 0,
otherwise the calls are essentially no-ops.
SMC API numbers are this:
- 0xffffffff: Switch to non-secure mode, SCR is: 0x31
(controlled by hypervisor to let SMC pass through hyp mode)
- 0xfffffff0: Read HTTBR (same order as mrrc r0,r1)
- 0xfffffff1: Write HTTBR (same order as mcrr r0,r1)
- 0xfffffff2: Read HTCR
- 0xfffffff3: Write HTCR
- 0xfffffff4: Read HMAIR0
- 0xfffffff5: Write HMAIR0
- 0xfffffff6: Read HMAIR1
- 0xfffffff7: Write HMAIR1
- 0xfffffff8: Read HSCTLR
- 0xfffffff9: Write HSCTLR
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Use 0xf0000000 instead of 0x0 as the monitor base address.
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Warning: This doesn't yet work.
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Makefile.
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configurations.
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protocol but without WFI since the GIC isn't set up.
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kernel command line.
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