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authorPeter Maydell <peter.maydell@linaro.org>2020-04-03 11:04:00 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-06-05 15:34:35 +0100
commitf142dc624f8c6347a507d6cf69ae849027df7062 (patch)
treedd2f477da92aca7f4b9090dc7181624eb3bc3d27
parentb748e08aa0f3d3d9931bb08ac6b28a707cdd0426 (diff)
arm.risu, thumb.risu: Add v8.2 DP and FHM insns
Add coverage for the v8.2 DP and v8.2 FHM insns in the Neon extension space. (We already had the v8.1 VQRDMLAH/VQRDLSH and the v8.3 VCADD/VCMLA, so this brings the risu coverage into line with what QEMU has implemented so far.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--arm.risu18
-rw-r--r--thumb.risu18
2 files changed, 36 insertions, 0 deletions
diff --git a/arm.risu b/arm.risu
index c16d245..f8b6deb 100644
--- a/arm.risu
+++ b/arm.risu
@@ -862,6 +862,24 @@ VQRDMLSH A1 111100110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4
VQRDMLSH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4
#
+# ARMv8.2 extensions
+#
+@v8_2_dp
+
+VUDOT A1 1111110 00 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 1 vm:4
+VSDOT A1 1111110 00 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 0 vm:4
+
+VUDOT_s A1 11111110 0 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 1 vm:4
+VSDOT_s A1 11111110 0 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 0 vm:4
+
+@v8_2_fhm
+
+VFMAL A1 1111110 00 d:1 10 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+VFMSL A1 1111110 01 d:1 10 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+VFMAL_s A1 11111110 0 d:1 00 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+VFMSL_s A1 11111110 1 d:1 00 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+
+#
# ARMv8.3 extensions
#
@v8_3_compnum
diff --git a/thumb.risu b/thumb.risu
index b8afa59..357b791 100644
--- a/thumb.risu
+++ b/thumb.risu
@@ -450,6 +450,24 @@ VQRDMLSH T1 111111110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4
VQRDMLSH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4
#
+# ARMv8.2 extensions
+#
+@v8_2_dp
+
+VUDOT A1 1111110 00 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 1 vm:4
+VSDOT A1 1111110 00 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 0 vm:4
+
+VUDOT_s A1 11111110 0 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 1 vm:4
+VSDOT_s A1 11111110 0 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 0 vm:4
+
+@v8_2_fhm
+
+VFMAL A1 1111110 00 d:1 10 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+VFMSL A1 1111110 01 d:1 10 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+VFMAL_s A1 11111110 0 d:1 00 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+VFMSL_s A1 11111110 1 d:1 00 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
+
+#
# ARMv8.3 extensions
#
@v8_3_compnum