diff options
| author | Rob Herring <robh@kernel.org> | 2015-07-10 11:34:55 -0500 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2015-07-10 15:46:30 -0500 |
| commit | a0a050b0ec1fc810a215da6466655c310529d667 (patch) | |
| tree | 00237c9a1ef16b05decfab6b79339bbefe0e417d | |
| parent | 8b635da59f05e3a16fdeca15f3213389566671fe (diff) | |
clk: mmp: add display clock gatespxa1928-drm
This more accurately models the clock tree and fixes DRM init on B0 Si
which adds some clock gating bits.
Signed-off-by: Rob Herring <robh@kernel.org>
| -rw-r--r-- | drivers/clk/mmp/clk-of-pxa1928.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c index fefc976d32b2..59e358440a98 100644 --- a/drivers/clk/mmp/clk-of-pxa1928.c +++ b/drivers/clk/mmp/clk-of-pxa1928.c @@ -172,13 +172,19 @@ static struct mmp_param_mux_clk apmu_mux_clks[] = { static struct mmp_param_div_clk apmu_div_clks[] = { {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock}, - {PXA1928_CLK_VDMA, "vdma_div", "vdma_mux", 0, PXA1928_CLK_DISP0 * 4, 24, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, - {PXA1928_CLK_DISP0, "disp0_div", "disp0_mux", 0, PXA1928_CLK_DISP0 * 4, 8, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, - {PXA1928_CLK_DISP1, "disp1_div", "disp1_mux", 0, PXA1928_CLK_DISP0 * 4, 16, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, - {PXA1928_CLK_DISP_AXI, "disp_axi_div", "disp_axi_mux", 0, PXA1928_CLK_DISP1 * 4, 0, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, + {0, "vdma_div", "vdma_mux", 0, PXA1928_CLK_DISP0 * 4, 24, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, + {0, "disp0_div", "disp0_mux", 0, PXA1928_CLK_DISP0 * 4, 8, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, + {0, "disp1_div", "disp1_mux", 0, PXA1928_CLK_DISP0 * 4, 16, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, + {0, "disp_axi_div", "disp_axi_mux", 0, PXA1928_CLK_DISP1 * 4, 0, 3, CLK_DIVIDER_ONE_BASED, &disp_lock}, }; static struct mmp_param_gate_clk apmu_gate_clks[] = { + {PXA1928_CLK_VDMA, "vdma", "vdma_div", CLK_SET_RATE_PARENT, PXA1928_CLK_DISP0 * 4, BIT(27), BIT(27), 0, 0, &disp_lock}, + {PXA1928_CLK_DISP0, "disp0", "disp0_div", CLK_SET_RATE_PARENT, PXA1928_CLK_DISP0 * 4, BIT(15), BIT(15), 0, 0, &disp_lock}, + {PXA1928_CLK_DISP1, "disp1", "disp1_div", CLK_SET_RATE_PARENT, PXA1928_CLK_DISP0 * 4, BIT(23), BIT(23), 0, 0, &disp_lock}, + {PXA1928_CLK_DISP_AXI, "disp_axi", "disp_axi_div", CLK_SET_RATE_PARENT, PXA1928_CLK_DISP1 * 4, BIT(7), BIT(7), 0, 0, &disp_lock}, + {PXA1928_CLK_DSI_ESC, "dsi_esc", "dsi_esc_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_DISP1 * 4, BIT(4), BIT(4), 0, 0, &disp_lock}, + {PXA1928_CLK_USB, "usb_clk", "usb_pll", 0, PXA1928_CLK_USB * 4, 0x9, 0x9, 0x0, 0, &usb_lock}, {PXA1928_CLK_HSIC, "hsic_clk", "usb_pll", 0, PXA1928_CLK_HSIC * 4, 0x9, 0x9, 0x0, 0, &usb_lock}, /* The gate clocks has mux parent. */ |