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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-03-31 10:44:09 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-04-08 15:22:56 +0100 |
| commit | 65a9c0e96a9fe033936f40b7603e0ae267b97d96 (patch) | |
| tree | 2317b487f3fd5895d0af80a354a3365150904c47 /docs/firmware-design.md | |
| parent | e6e54a18f80318e2fcf98f4f8810705618cdea79 (diff) | |
Revert "Move architecture timer setup to platform-specific code"
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5
because it introduced a bug: the CNTFRQ_EL0 register was no
longer programmed by all CPUs. bl31_platform_setup() function
is invoked only in the cold boot path and consequently only
on the primary cpu.
A subsequent commit will correctly implement the necessary changes
to the counter frequency setup code.
Fixes ARM-software/tf-issues#125
Conflicts:
docs/firmware-design.md
plat/fvp/bl31_plat_setup.c
Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
Diffstat (limited to 'docs/firmware-design.md')
| -rw-r--r-- | docs/firmware-design.md | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index e92042d..2bf57ca 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -151,16 +151,19 @@ BL1 performs minimal architectural initialization as follows. and Advanced SIMD execution are configured to not trap to EL3 by clearing the `CPTR_EL3.TFP` bit. + - `CNTFRQ_EL0`. The `CNTFRQ_EL0` register is programmed with the base + frequency of the system counter, which is retrieved from the first entry + in the frequency modes table. + + - Generic Timer. The system level implementation of the generic timer is + enabled through the memory mapped interface. + #### Platform initialization -BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests -from the CCI-400 slave interface corresponding to the cluster that includes -the primary CPU. BL1 also initializes UART0 (PL011 console), which enables -access to the `printf` family of functions in BL1. The `CNTFRQ_EL0` register is -programmed with the base frequency of the system counter, which is retrieved -from the first entry in the frequency modes table. The system level -implementation of the generic timer is enabled through the memory mapped -interface. +BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from +the CCI-400 slave interface corresponding to the cluster that includes the +primary CPU. BL1 also initializes UART0 (PL011 console), which enables access to +the `printf` family of functions in BL1. #### BL2 image load and execution |