diff options
| -rw-r--r-- | docs/plat/nvidia-tegra.md | 11 | ||||
| -rw-r--r-- | docs/spd/optee-dispatcher.md (renamed from docs/optee-dispatcher.md) | 0 | ||||
| -rw-r--r-- | docs/spd/tlk-dispatcher.md (renamed from docs/tlk-dispatcher.md) | 5 | ||||
| -rw-r--r-- | docs/user-guide.md | 2 | ||||
| -rw-r--r-- | include/plat/arm/css/common/css_def.h | 26 | ||||
| -rw-r--r-- | plat/arm/css/common/css_scp_bootloader.c | 4 | ||||
| -rw-r--r-- | plat/arm/css/common/css_scpi.c | 4 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/drivers/memctrl/memctrl.c | 79 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_bl31_setup.c | 38 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_common.mk | 1 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_sip_calls.c | 105 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/drivers/memctrl.h | 5 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/platform_def.h | 5 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/tegra_private.h | 7 |
14 files changed, 276 insertions, 16 deletions
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index 242e8db..e4f9a05 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -15,7 +15,16 @@ Directory structure * plat/nvidia/tegra/common - Common code for all Tegra SoCs * plat/nvidia/tegra/soc/txxx - Chip specific code +Trusted OS dispatcher +===================== +Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of +them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd' +on the command line while preparing a bl31 image. This allows other Trusted OS +vendors to use the upstream code and include their dispatchers in the image +without changing any makefiles. + Preparing the BL31 image to run on Tegra SoCs =================================================== CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ -TARGET_SOC=<target-soc e.g. t210> all +TARGET_SOC=<target-soc e.g. t210> BL32=<path-to-trusted-os-binary> \ +SPD=<dispatcher e.g. tlkd> all diff --git a/docs/optee-dispatcher.md b/docs/spd/optee-dispatcher.md index c154f6b..c154f6b 100644 --- a/docs/optee-dispatcher.md +++ b/docs/spd/optee-dispatcher.md diff --git a/docs/tlk-dispatcher.md b/docs/spd/tlk-dispatcher.md index a2212b5..890b35e 100644 --- a/docs/tlk-dispatcher.md +++ b/docs/spd/tlk-dispatcher.md @@ -10,10 +10,11 @@ In order to compile TLK-D, we need a BL32 image to be present. Since, TLKD just needs to compile, any BL32 image would do. To use TLK as the BL32, please refer to the "Build TLK" section. -Once a BL32 is ready, TLKD can be compiled using the following command: +Once a BL32 is ready, TLKD can be included in the image using the following +command: CROSS_COMPILE=<path_to_linaro_chain>/bin/aarch64-none-elf- make NEED_BL1=0 -NEED_BL2=0 BL32=<path_to_BL32_image> PLAT=<platform> all +NEED_BL2=0 BL32=<path_to_BL32_image> PLAT=<platform> SPD=tlkd all _ Trusted Little Kernel (TLK) =========================== diff --git a/docs/user-guide.md b/docs/user-guide.md index c1cadbb..9a9334f 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -322,7 +322,7 @@ performed. #### ARM development platform specific build options -* `ARM_TSP_RAM_LOCATION_ID`: location of the TSP binary. Options: +* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options: - `tsram` : Trusted SRAM (default option) - `tdram` : Trusted DRAM (if available) - `dram` : Secure region in DRAM (configured by the TrustZone controller) diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 056c00d..268438f 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -37,11 +37,9 @@ /************************************************************************* * Definitions common to all ARM Compute SubSystems (CSS) *************************************************************************/ -#define MHU_SECURE_BASE ARM_SHARED_RAM_BASE -#define MHU_SECURE_SIZE ARM_SHARED_RAM_SIZE #define MHU_PAYLOAD_CACHED 0 -#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE +#define TRUSTED_MAILBOXES_BASE ARM_TRUSTED_SRAM_BASE #define TRUSTED_MAILBOX_SHIFT 4 #define NSROM_BASE 0x1f000000 @@ -66,11 +64,29 @@ #define CSS_IRQ_TZC 80 #define CSS_IRQ_TZ_WDOG 86 -/* SCP <=> AP boot configuration */ -#define SCP_BOOT_CFG_ADDR 0x04000080 +/* + * SCP <=> AP boot configuration + * + * The SCP/AP boot configuration is a 32-bit word located at a known offset from + * the start of the Trusted SRAM. Part of this configuration is which CPU is the + * primary, according to the shift and mask definitions below. + * + * Note that the value stored at this address is only valid at boot time, before + * the BL3-0 image is transferred to SCP. + */ +#define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80) #define PRIMARY_CPU_SHIFT 8 #define PRIMARY_CPU_BIT_WIDTH 4 +/* + * Base address of the first memory region used for communication between AP + * and SCP. Used by the BOM and SCPI protocols. + * + * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which + * means the SCP/AP configuration data gets overwritten when the AP initiates + * communication with the SCP. + */ +#define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ CSS_DEVICE_BASE, \ diff --git a/plat/arm/css/common/css_scp_bootloader.c b/plat/arm/css/common/css_scp_bootloader.c index 6cf1667..acc7351 100644 --- a/plat/arm/css/common/css_scp_bootloader.c +++ b/plat/arm/css/common/css_scp_bootloader.c @@ -60,7 +60,7 @@ typedef struct { * Unlike the SCPI protocol, the boot protocol uses the same memory region * for both AP -> SCP and SCP -> AP transfers; define the address of this... */ -#define BOM_SHARED_MEM (MHU_SECURE_BASE + 0x0080) +#define BOM_SHARED_MEM SCP_COM_SHARED_MEM_BASE #define BOM_CMD_HEADER ((bom_cmd_t *) BOM_SHARED_MEM) #define BOM_CMD_PAYLOAD ((void *) (BOM_SHARED_MEM + sizeof(bom_cmd_t))) @@ -181,7 +181,7 @@ int scp_bootloader_transfer(void *image, unsigned int image_size) BOM_CMD_HEADER->id = BOOT_CMD_DATA; cmd_data_payload = BOM_CMD_PAYLOAD; - cmd_data_payload->offset = (uintptr_t) image - MHU_SECURE_BASE; + cmd_data_payload->offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE; cmd_data_payload->block_size = image_size; scp_boot_message_send(sizeof(*cmd_data_payload)); diff --git a/plat/arm/css/common/css_scpi.c b/plat/arm/css/common/css_scpi.c index 9127259..0a4eafe 100644 --- a/plat/arm/css/common/css_scpi.c +++ b/plat/arm/css/common/css_scpi.c @@ -37,8 +37,8 @@ #include "css_mhu.h" #include "css_scpi.h" -#define SCPI_SHARED_MEM_SCP_TO_AP (MHU_SECURE_BASE + 0x0080) -#define SCPI_SHARED_MEM_AP_TO_SCP (MHU_SECURE_BASE + 0x0180) +#define SCPI_SHARED_MEM_SCP_TO_AP SCP_COM_SHARED_MEM_BASE +#define SCPI_SHARED_MEM_AP_TO_SCP (SCP_COM_SHARED_MEM_BASE + 0x100) #define SCPI_CMD_HEADER_AP_TO_SCP \ ((scpi_cmd_t *) SCPI_SHARED_MEM_AP_TO_SCP) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c index 9a8ba66..fff8951 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c @@ -28,11 +28,23 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <arch_helpers.h> #include <assert.h> #include <debug.h> #include <mmio.h> #include <memctrl.h> +#include <string.h> #include <tegra_def.h> +#include <xlat_tables.h> + +extern void zeromem16(void *mem, unsigned int length); + +#define TEGRA_GPU_RESET_REG_OFFSET 0x28c +#define GPU_RESET_BIT (1 << 24) + +/* Video Memory base and size (live values) */ +static uintptr_t video_mem_base; +static uint64_t video_mem_size; /* * Init SMMU. @@ -71,6 +83,10 @@ void tegra_memctrl_setup(void) tegra_mc_write_32(MC_SMMU_CONFIG_0, MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + + /* video memory carveout */ + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); } /* @@ -90,3 +106,66 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); } + +/* + * Program the Video Memory carveout region + * + * phys_base = physical base of aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); + uintptr_t vmem_end_new = phys_base + size_in_bytes; + uint32_t regval; + + /* + * The GPU is the user of the Video Memory region. In order to + * transition to the new memory region smoothly, we program the + * new base/size ONLY if the GPU is in reset mode. + */ + regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); + if ((regval & GPU_RESET_BIT) == 0) { + ERROR("GPU not in reset! Video Memory setup failed\n"); + return; + } + + /* + * Setup the Memory controller to restrict CPU accesses to the Video + * Memory region + */ + INFO("Configuring Video Memory Carveout\n"); + + /* + * Configure Memory Controller directly for the first time. + */ + if (video_mem_base == 0) + goto done; + + /* + * Clear the old regions now being exposed. The following cases + * can occur - + * + * 1. clear whole old region (no overlap with new region) + * 2. clear old sub-region below new base + * 3. clear old sub-region above new end + */ + INFO("Cleaning previous Video Memory Carveout\n"); + + disable_mmu_el3(); + if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) + zeromem16((void *)video_mem_base, video_mem_size << 20); + else if (video_mem_base < phys_base) + zeromem16((void *)video_mem_base, phys_base - video_mem_base); + else if (vmem_end_old > vmem_end_new) + zeromem16((void *)vmem_end_new, vmem_end_old - vmem_end_new); + enable_mmu_el3(0); + +done: + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); + + /* store new values */ + video_mem_base = phys_base; + video_mem_size = size_in_bytes >> 20; +} diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 628dc2a..dea8457 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -37,6 +37,7 @@ #include <cortex_a57.h> #include <cortex_a53.h> #include <debug.h> +#include <errno.h> #include <memctrl.h> #include <mmio.h> #include <platform.h> @@ -82,7 +83,7 @@ extern uint64_t tegra_bl31_phys_base; #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) #endif -static entry_point_info_t bl33_image_ep_info; +static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { (uint64_t)TZDRAM_SIZE, (uintptr_t)NULL }; @@ -102,6 +103,9 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) if (type == NON_SECURE) return &bl33_image_ep_info; + if (type == SECURE) + return &bl32_image_ep_info; + return NULL; } @@ -134,10 +138,11 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, plat_crash_console_init(); /* - * Copy BL3-3 entry point information. + * Copy BL3-3, BL3-2 entry point information. * They are stored in Secure RAM, in BL2's address space. */ bl33_image_ep_info = *from_bl2->bl33_ep_info; + bl32_image_ep_info = *from_bl2->bl32_ep_info; /* * Parse platform specific parameters - TZDRAM aperture size and @@ -226,3 +231,32 @@ void bl31_plat_arch_setup(void) /* enable the MMU */ enable_mmu_el3(0); } + +/******************************************************************************* + * Check if the given NS DRAM range is valid + ******************************************************************************/ +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) +{ + uint64_t end = base + size_in_bytes - 1; + + /* + * Check if the NS DRAM address is valid + */ + if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || + (base >= end)) { + ERROR("NS address is out-of-bounds!\n"); + return -EFAULT; + } + + /* + * TZDRAM aperture contains the BL31 and BL32 images, so we need + * to check if the NS DRAM range overlaps the TZDRAM aperture. + */ + if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { + ERROR("NS address overlaps TZDRAM!\n"); + return -ENOTSUP; + } + + /* valid NS address */ + return 0; +} diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index b1ce51f..12d684f 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -59,4 +59,5 @@ BL31_SOURCES += drivers/arm/gic/arm_gic.c \ ${COMMON_DIR}/tegra_bl31_setup.c \ ${COMMON_DIR}/tegra_gic.c \ ${COMMON_DIR}/tegra_pm.c \ + ${COMMON_DIR}/tegra_sip_calls.c \ ${COMMON_DIR}/tegra_topology.c diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c new file mode 100644 index 0000000..1d79c80 --- /dev/null +++ b/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <context_mgmt.h> +#include <debug.h> +#include <errno.h> +#include <memctrl.h> +#include <runtime_svc.h> +#include <tegra_private.h> + +#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 + +/******************************************************************************* + * This function is responsible for handling all SiP calls from the NS world + ******************************************************************************/ +uint64_t tegra_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + int err; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) + SMC_RET1(handle, SMC_UNK); + + switch (smc_fid) { + + case TEGRA_SIP_NEW_VIDEOMEM_REGION: + + /* + * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) + * or falls outside of the valid DRAM range + */ + err = bl31_check_ns_address(x1, x2); + if (err) + SMC_RET1(handle, err); + + /* + * Check if Video Memory is aligned to 1MB. + */ + if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { + ERROR("Unaligned Video Memory base address!\n"); + SMC_RET1(handle, -ENOTSUP); + } + + /* new video memory carveout settings */ + tegra_memctrl_videomem_setup(x1, x2); + + SMC_RET1(handle, 0); + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tegra_sip_fast, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + tegra_sip_handler +); diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index 867f09e..26c8057 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -64,6 +64,10 @@ #define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG1_0 0x74 +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + static inline uint32_t tegra_mc_read_32(uint32_t off) { return mmio_read_32(TEGRA_MC_BASE + off); @@ -76,5 +80,6 @@ static inline void tegra_mc_write_32(uint32_t off, uint32_t val) void tegra_memctrl_setup(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); #endif /* __MEMCTRL_H__ */ diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 6be777e..d4b0ce2 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -69,8 +69,11 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ +#define BL31_SIZE 0x20000 #define BL31_BASE TZDRAM_BASE -#define BL31_LIMIT (TZDRAM_BASE + 0x11FFF) +#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) +#define BL32_BASE (TZDRAM_BASE + BL31_SIZE) +#define BL32_LIMIT TZDRAM_END /******************************************************************************* * Platform specific page table and MMU setup constants diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 484879e..fa29fbb 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -34,6 +34,12 @@ #include <xlat_tables.h> #include <platform_def.h> +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE 0x80000000 +#define TEGRA_DRAM_END 0x27FFFFFFF + typedef struct plat_params_from_bl2 { uint64_t tzdram_size; uintptr_t bl32_params; @@ -66,5 +72,6 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr); /* Declarations for tegra_bl31_setup.c */ plat_params_from_bl2_t *bl31_get_plat_params(void); +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); #endif /* __TEGRA_PRIVATE_H__ */ |