hdmicap

Signed-off-by: Andy Green <andy.green@linaro.org>

4 files changed, 702 insertions, 70 deletions

diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts
index 8ba2e11f889d..f623be7f08e5 100644
--- a/arch/arm/boot/dts/zynq-zturn.dts
+++ b/arch/arm/boot/dts/zynq-zturn.dts
@@ -172,6 +172,29 @@
 };
 
 &amba {
+axi_dma_0: axidma@40400000 {
+        compatible = "xlnx,axi-dma-1.00.a";
+        #dma-cells = <1>;
+        reg = <0x40400000 0x10000>;
+        dma-channel@40400030 {
+                compatible = "xlnx,axi-dma-s2mm-channel";
+		interrupt-parent = <&intc>;
+                interrupts = <0 31 4>;
+                xlnx,datawidth = <32>;
+		//xlnx,include-sg;
+        };
+};
+
+
+	hdmicap {
+		compatible = "linaro,hdmicap";
+		reg = <0x43c10000 0x1000>;
+		clocks = <&clkc 15>, <&clkc 16>;
+		clock-names = "a", "b", "c", "d";
+	        interrupt-parent = <&intc>;
+       		interrupts = <0 29 4>;
+		dma = <&axi_dma_0>;
+	};
 
 	gpio-leds {
 		compatible = "gpio-leds";
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6f50ea..95aeefc4c4b3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -12,7 +12,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_VIRT=y
-CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
@@ -20,14 +19,15 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_39X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
+CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_AT91=y
 CONFIG_SOC_SAMA5D3=y
 CONFIG_SOC_SAMA5D4=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_CYGNUS=y
-CONFIG_ARCH_BCM_21664=y
-CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
+CONFIG_ARCH_BCM_281XX=y
+CONFIG_ARCH_BCM_21664=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_MACH_BERLIN_BG2=y
@@ -37,9 +37,9 @@ CONFIG_ARCH_DIGICOLOR=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
-CONFIG_ARCH_HIX5HD2=y
 CONFIG_ARCH_HIP01=y
 CONFIG_ARCH_HIP04=y
+CONFIG_ARCH_HIX5HD2=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MESON=y
 CONFIG_ARCH_MXC=y
@@ -49,8 +49,9 @@ CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
 CONFIG_SOC_IMX6SX=y
-CONFIG_SOC_VF610=y
 CONFIG_SOC_LS1021A=y
+CONFIG_SOC_VF610=y
+CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
 CONFIG_SOC_OMAP5=y
@@ -58,7 +59,6 @@ CONFIG_SOC_AM33XX=y
 CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_MSM8X60=y
 CONFIG_ARCH_MSM8960=y
 CONFIG_ARCH_MSM8974=y
@@ -90,26 +90,19 @@ CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
 CONFIG_ARCH_TEGRA_124_SOC=y
-CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_ARCH_U8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
-CONFIG_MACH_UX500_DT=y
 CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_VEXPRESS_CA9X4=y
 CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TRUSTED_FOUNDATIONS=y
-CONFIG_PCI=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_KEYSTONE=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PCI_TEGRA=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PCI_RCAR_GEN2_PCIE=y
-CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_KEYSTONE=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=16
 CONFIG_HIGHPTE=y
@@ -120,12 +113,12 @@ CONFIG_KEXEC=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_STAT_DETAILS=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT=y
 CONFIG_CPU_IDLE=y
 CONFIG_ARM_CPUIDLE=y
-CONFIG_NEON=y
-CONFIG_KERNEL_MODE_NEON=y
 CONFIG_ARM_ZYNQ_CPUIDLE=y
 CONFIG_ARM_EXYNOS_CPUIDLE=y
+CONFIG_KERNEL_MODE_NEON=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -143,9 +136,6 @@ CONFIG_IPV6_MIP6=m
 CONFIG_IPV6_TUNNEL=m
 CONFIG_IPV6_MULTIPLE_TABLES=y
 CONFIG_CAN=y
-CONFIG_CAN_RAW=y
-CONFIG_CAN_BCM=y
-CONFIG_CAN_DEV=y
 CONFIG_CAN_AT91=m
 CONFIG_CAN_XILINXCAN=y
 CONFIG_CAN_MCP251X=y
@@ -185,7 +175,6 @@ CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_SUNXI_SID=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
@@ -196,10 +185,10 @@ CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
 CONFIG_SATA_RCAR=y
 CONFIG_NETDEVICES=y
-CONFIG_HIX5HD2_GMAC=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_MACB=y
 CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_IGB=y
 CONFIG_MV643XX_ETH=y
 CONFIG_MVNETA=y
@@ -230,8 +219,8 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_QT1070=m
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_TEGRA=y
-CONFIG_KEYBOARD_SPEAR=y
 CONFIG_KEYBOARD_ST_KEYSCAN=y
+CONFIG_KEYBOARD_SPEAR=y
 CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_MOUSE_CYAPA=m
@@ -284,17 +273,16 @@ CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
 CONFIG_SERIAL_ST_ASC=y
 CONFIG_SERIAL_ST_ASC_CONSOLE=y
 CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_DAVINCI=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=m
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_AT91=m
 CONFIG_I2C_CADENCE=y
+CONFIG_I2C_DAVINCI=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_DIGICOLOR=m
 CONFIG_I2C_GPIO=m
-CONFIG_I2C_EXYNOS5=y
 CONFIG_I2C_MV64XXX=y
 CONFIG_I2C_RIIC=y
 CONFIG_I2C_S3C2410=y
@@ -328,21 +316,20 @@ CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_PINCTRL_APQ8084=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_GPIO_DAVINCI=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_EM=y
 CONFIG_GPIO_RCAR=y
+CONFIG_GPIO_SYSCON=y
 CONFIG_GPIO_XILINX=y
 CONFIG_GPIO_ZYNQ=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_PCF857X=y
-CONFIG_GPIO_TWL4030=y
 CONFIG_GPIO_PALMAS=y
-CONFIG_GPIO_SYSCON=y
 CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=y
 CONFIG_BATTERY_SBS=y
 CONFIG_BATTERY_MAX17040=m
 CONFIG_BATTERY_MAX17042=m
@@ -353,6 +340,7 @@ CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_POWER_RESET_GPIO_RESTART=y
 CONFIG_POWER_RESET_KEYSTONE=y
+CONFIG_POWER_RESET_SYSCON=y
 CONFIG_POWER_RESET_RMOBILE=y
 CONFIG_SENSORS_LM90=y
 CONFIG_SENSORS_LM95245=y
@@ -360,16 +348,16 @@ CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
-CONFIG_DAVINCI_WATCHDOG=m
 CONFIG_EXYNOS_THERMAL=m
 CONFIG_ST_THERMAL_SYSCFG=y
 CONFIG_ST_THERMAL_MEMMAP=y
 CONFIG_WATCHDOG=y
 CONFIG_XILINX_WATCHDOG=y
 CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_DAVINCI_WATCHDOG=m
 CONFIG_ORION_WATCHDOG=y
-CONFIG_ST_LPC_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
+CONFIG_ST_LPC_WATCHDOG=y
 CONFIG_MESON_WATCHDOG=y
 CONFIG_MFD_AS3711=y
 CONFIG_MFD_AS3722=y
@@ -395,8 +383,6 @@ CONFIG_REGULATOR_AXP20X=y
 CONFIG_REGULATOR_BCM590XX=y
 CONFIG_REGULATOR_DA9210=y
 CONFIG_REGULATOR_GPIO=y
-CONFIG_MFD_SYSCON=y
-CONFIG_POWER_RESET_SYSCON=y
 CONFIG_REGULATOR_MAX14577=m
 CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_MAX8973=y
@@ -417,8 +403,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_CONTROLLER=y
 CONFIG_VIDEO_V4L2_SUBDEV_API=y
 CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_USB_VIDEO_CLASS=y
-CONFIG_USB_GSPCA=y
+CONFIG_USB_VIDEO_CLASS=m
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=m
 CONFIG_SOC_CAMERA_PLATFORM=m
@@ -432,20 +417,18 @@ CONFIG_DRM=y
 CONFIG_DRM_PTN3460=m
 CONFIG_DRM_PS8622=m
 CONFIG_DRM_EXYNOS=m
-CONFIG_DRM_EXYNOS_DSI=y
 CONFIG_DRM_EXYNOS_FIMD=y
+CONFIG_DRM_EXYNOS_DSI=y
 CONFIG_DRM_EXYNOS_HDMI=y
 CONFIG_DRM_RCAR_DU=m
 CONFIG_DRM_TEGRA=y
-CONFIG_DRM_PANEL_S6E8AA0=m
 CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_S6E8AA0=m
 CONFIG_FB_ARMCLCD=y
 CONFIG_FB_WM8505=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FB_SIMPLE=y
 CONFIG_FB_SH_MOBILE_MERAM=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_LCD_PLATFORM=m
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_BACKLIGHT_AS3711=y
@@ -454,7 +437,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_SOUND=m
 CONFIG_SND=m
 CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_SOC=m
 CONFIG_SND_ATMEL_SOC=m
 CONFIG_SND_ATMEL_SOC_WM8904=m
@@ -473,14 +456,11 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_MVEBU=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_EXYNOS=y
-CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_EHCI_HCD_STI=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_ISP1760=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_EHCI_EXYNOS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_STI=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_EXYNOS=m
 CONFIG_USB_R8A66597_HCD=m
 CONFIG_USB_RENESAS_USBHS=m
@@ -488,11 +468,9 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=y
 CONFIG_AB8500_USB=y
 CONFIG_KEYSTONE_USB_PHY=y
-CONFIG_OMAP_USB3=y
-CONFIG_SAMSUNG_USB2PHY=y
-CONFIG_SAMSUNG_USB3PHY=y
 CONFIG_USB_GPIO_VBUS=y
 CONFIG_USB_ISP1301=y
 CONFIG_USB_MXS_PHY=y
@@ -508,9 +486,9 @@ CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_DOVE=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_PXAV3=y
 CONFIG_MMC_SDHCI_SPEAR=y
-CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_MMC_SDHCI_ST=y
@@ -521,7 +499,6 @@ CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_IDMAC=y
-CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SH_MMCIF=y
@@ -552,15 +529,14 @@ CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_MAX77802=m
 CONFIG_RTC_DRV_RS5C372=m
 CONFIG_RTC_DRV_PALMAS=y
-CONFIG_RTC_DRV_ST_LPC=y
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_TPS6586X=y
 CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_S35390A=m
 CONFIG_RTC_DRV_RX8581=m
 CONFIG_RTC_DRV_EM3027=y
-CONFIG_RTC_DRV_DIGICOLOR=m
 CONFIG_RTC_DRV_S5M=m
+CONFIG_RTC_DRV_DIGICOLOR=m
 CONFIG_RTC_DRV_S3C=m
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_AT91RM9200=m
@@ -570,6 +546,7 @@ CONFIG_RTC_DRV_SUN6I=y
 CONFIG_RTC_DRV_SUNXI=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_ST_LPC=y
 CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_AT_HDMAC=y
@@ -587,6 +564,7 @@ CONFIG_IMX_DMA=y
 CONFIG_MXS_DMA=y
 CONFIG_DMA_OMAP=y
 CONFIG_XILINX_VDMA=y
+CONFIG_XILINX_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
@@ -595,23 +573,21 @@ CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
 CONFIG_NVEC_POWER=y
 CONFIG_NVEC_PAZ00=y
-CONFIG_QCOM_GSBI=y
-CONFIG_QCOM_PM=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_CHROME_PLATFORMS=y
 CONFIG_CROS_EC_CHARDEV=m
 CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_COMMON_CLK_MAX77802=m
 CONFIG_COMMON_CLK_S2MPS11=m
+CONFIG_COMMON_CLK_QCOM=y
 CONFIG_APQ_MMCC_8084=y
 CONFIG_MSM_GCC_8660=y
 CONFIG_MSM_MMCC_8960=y
 CONFIG_MSM_MMCC_8974=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_PM=y
 CONFIG_PM_DEVFREQ=y
 CONFIG_ARM_TEGRA_DEVFREQ=m
-CONFIG_MEMORY=y
 CONFIG_TI_AEMIF=y
 CONFIG_IIO=y
 CONFIG_AT91_ADC=m
@@ -624,17 +600,18 @@ CONFIG_PWM_RENESAS_TPU=y
 CONFIG_PWM_SAMSUNG=m
 CONFIG_PWM_TEGRA=y
 CONFIG_PWM_VT8500=y
-CONFIG_PHY_HIX5HD2_SATA=y
-CONFIG_OMAP_USB2=y
-CONFIG_TI_PIPE3=y
+CONFIG_KEYSTONE_IRQ=y
 CONFIG_PHY_MIPHY28LP=y
 CONFIG_PHY_MIPHY365X=y
 CONFIG_PHY_RCAR_GEN2=m
-CONFIG_PHY_STIH41X_USB=y
-CONFIG_PHY_STIH407_USB=y
+CONFIG_OMAP_USB2=y
+CONFIG_TI_PIPE3=y
+CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_SUN9I_USB=y
 CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHY_STIH407_USB=y
+CONFIG_PHY_STIH41X_USB=y
 CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
@@ -642,7 +619,6 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_UBIFS_FS=y
-CONFIG_TMPFS=y
 CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_XZ=y
@@ -657,20 +633,14 @@ CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_LOCKUP_DETECTOR=y
-CONFIG_CRYPTO_DEV_TEGRA_AES=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_KEYSTONE_IRQ=y
+CONFIG_CRYPTO_DEV_ATMEL_AES=m
+CONFIG_CRYPTO_DEV_ATMEL_TDES=m
+CONFIG_CRYPTO_DEV_ATMEL_SHA=m
 CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM=m
 CONFIG_CRYPTO_SHA1_ARM_NEON=m
 CONFIG_CRYPTO_SHA1_ARM_CE=m
 CONFIG_CRYPTO_SHA2_ARM_CE=m
-CONFIG_CRYPTO_SHA256_ARM=m
 CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
 CONFIG_CRYPTO_AES_ARM_BS=m
 CONFIG_CRYPTO_AES_ARM_CE=m
 CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_DEV_ATMEL_AES=m
-CONFIG_CRYPTO_DEV_ATMEL_TDES=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA=m
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d056fb7186fe..75cf6ec29aa8 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_GENWQE)		+= genwqe/
 obj-$(CONFIG_ECHO)		+= echo/
 obj-$(CONFIG_VEXPRESS_SYSCFG)	+= vexpress-syscfg.o
 obj-$(CONFIG_CXL_BASE)		+= cxl/
+obj-y += hdmicap.o
diff --git a/drivers/misc/hdmicap.c b/drivers/misc/hdmicap.c
new file mode 100644
index 000000000000..bc6b87f51f8c
--- /dev/null
+++ b/drivers/misc/hdmicap.c
@@ -0,0 +1,638 @@
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/amba/xilinx_dma.h>
+
+struct hdmicap_chip {
+	struct device *dev;
+	void __iomem *base;
+	phys_addr_t pa_base;
+	int irq;
+	int phase;
+	void __iomem *buf;
+	struct device_node *dma_node;
+	dma_addr_t dma_handle;
+	int sync_polarities;
+	int has_not_lost_pllsync;
+
+	u32 escape_capture_timestamp;
+};
+
+struct measurements {
+	int valid;
+	int htotal;
+	int hblank;
+	int hact;
+	int hsa;
+	int hfp;
+	int hbp;
+	int h_line_measured;
+
+	int vtotal;
+	int vblank;
+	int vact;
+	int vsa;
+	int vfp;
+	int vbp;
+	int v_frame_measured;
+
+	int channel_escapes[3];
+	u32 px_clocks_escapes_sampled;
+
+	int pixel_clk_hz;
+	int pixels_in_frame;
+	int data_in_frame;
+	int data_in_vb;
+};
+
+static int is_synchronized(struct hdmicap_chip *pc);
+
+static irqreturn_t hdmicap_isr(int irq, void *data)
+{
+        struct hdmicap_chip *pc = data;
+	u32 status = readl(pc->base + 8);
+
+	if (!(status & BIT(31)))
+		pc->has_not_lost_pllsync = 0;
+
+	/* clears all the interrupt sources */
+	writel(0, pc->base + 0xc);
+
+	return IRQ_HANDLED;
+}
+
+static int _get_measurements(struct hdmicap_chip *pc, struct measurements *m)
+{
+	u32 avg, u, period_ps;
+
+	m->valid = 1;
+
+	avg = readl(pc->base + 0x30) + readl(pc->base + 0x34) +
+	      readl(pc->base + 0x38) + readl(pc->base + 0x3c);
+
+	m->pixel_clk_hz = 0;
+
+	if (avg) {
+		u64 u = 1000000000000ul;
+		period_ps = (4 * (u32)655360000) / avg;
+		if (period_ps) {
+			do_div(u, period_ps);
+			m->pixel_clk_hz = (u32)u;
+		}
+	}
+
+	/* disable measurement updates while we read them */
+	writel(BIT(0), pc->base + 0x18);
+
+	m->htotal = (readl(pc->base + 0x18) >> 16) + 1;
+	m->hsa = readl(pc->base + 0x18) & 0xffff;
+	m->hfp = readl(pc->base + 0x1c) >> 16;
+	m->hbp = (readl(pc->base + 0x1c) & 0xffff) + 2;
+	m->h_line_measured = readl(pc->base + 0x50) & 0xffff;
+
+	m->hblank = m->hsa + m->hfp + m->hbp;
+	m->hact = m->htotal - m->hblank;
+
+	m->vtotal = (readl(pc->base + 0x10) >> 16) + 1;
+	m->vsa = readl(pc->base + 0x10) & 0xffff;
+	m->vfp = (readl(pc->base + 0x14) >> 16) + 1;
+	m->vbp = readl(pc->base + 0x14) & 0xffff;
+	m->v_frame_measured = (readl(pc->base + 0x50) >> 16) & 0xffff;
+
+	m->vblank = m->vsa + m->vfp + m->vbp;
+	m->vact = m->vtotal - m->vblank;
+
+	m->pixels_in_frame = readl(pc->base + 0x24) + 1;
+	m->data_in_vb = readl(pc->base + 0x20) + 1;
+	m->data_in_frame = readl(pc->base + 0x28) + 1;
+
+	/* capture / clear channel escape info */
+	writel(BIT(0), pc->base + 0x14);
+	ndelay(100);
+
+	u = readl(pc->base + 0x40);
+	m->channel_escapes[0] = readl(pc->base + 0x44);
+	m->channel_escapes[1] = readl(pc->base + 0x48);
+	m->channel_escapes[2] = readl(pc->base + 0x4c);
+
+	m->px_clocks_escapes_sampled = u - pc->escape_capture_timestamp;
+	pc->escape_capture_timestamp = u;
+
+	/* re-enable measurement updates  */
+	writel(0, pc->base + 0x18);
+
+	return 0;
+}
+
+static int get_measurements(struct hdmicap_chip *pc, struct measurements *m)
+{
+	/* if PLL not locked, no meaningful measurements possible */
+
+	m->valid = 0;
+	if (is_synchronized(pc) < 0)
+		return -EINVAL;
+
+	return _get_measurements(pc, m);
+}
+
+static int find_sync_polarity(struct hdmicap_chip *pc)
+{
+	int highest = 0, best = -1, sample, n;
+	struct measurements m;
+
+	if (!(readl(pc->base + 8) & BIT(31)))
+		return -EINVAL;
+
+	/* look for best h / vsync */
+
+	for (n = 0; n < 4; n++) {
+		writel(4 | n, pc->base + 0x8);
+		writel(0 | n, pc->base + 0x8);
+		usleep_range(40000, 50000);
+
+		_get_measurements(pc, &m);
+
+		if (m.hact < 32 || m.vact < 32)
+			continue;
+		if (m.hblank < 5)
+			continue;
+		if (m.vblank < 2)
+			continue;
+		if (!m.hbp || !m.hfp)
+			continue;
+		if (!m.vbp || !m.vfp)
+			continue;
+
+		/* look at ratio of blanking to total */
+
+		sample = ((m.htotal * 10) / m.hblank) +
+			 ((m.vtotal * 10) / m.vblank);
+		pr_err("n %d -> %d\n", n, sample);
+		if (sample > highest) {
+			highest = sample;
+			best = n;
+		}
+	}
+
+	pc->sync_polarities = best;
+
+	writel(BIT(2) | (best & 3), pc->base + 0x8);
+
+	return best;
+}
+
+static int is_synchronized(struct hdmicap_chip *pc)
+{
+	int n;
+
+	/* right now he is unsync'd, nothing to do but fail */
+
+	if (!(readl(pc->base + 8) & BIT(31)))
+		return -EINVAL;
+
+	/* if he's still OK from last time, just use that */
+
+	if (pc->has_not_lost_pllsync && pc->sync_polarities >= 0)
+		return 0;
+
+	/* he has lost and regained PLL sync... init */
+
+	n = find_sync_polarity(pc);
+	pr_err("resync'd to sync polarity %d\n", n);
+
+	pc->has_not_lost_pllsync = pc->sync_polarities >= 0;
+	msleep(40); /* give it time to get a full frame */
+
+	return 0;
+}
+
+static int set_phase(struct hdmicap_chip *pc, int phase)
+{
+	int to;
+
+	if (!(readl(pc->base + 8) & BIT(31)))
+		return -EINVAL;
+
+	writel(phase, pc->base);
+	to = 200;
+	while ((readl(pc->base + 4) >> 24) != phase && --to)
+		usleep_range(10, 20);
+
+	if (!to) {
+		dev_err(pc->dev, "%s: timeout setting phase\n",
+				__func__);
+		return -ETIME;
+	}
+
+	pc->phase = phase;
+
+	return 0;
+}
+
+static int scan(struct hdmicap_chip *pc)
+{
+	int n;
+
+	n = set_phase(pc, 240);
+	if (n < 0)
+		return n;
+
+	return 0;
+}
+
+
+static ssize_t hdmicap_attr_show(struct device *dev,
+                                struct device_attribute *attr,
+                                char *buf)
+{
+	struct hdmicap_chip *pc = dev_get_drvdata(dev);
+	struct measurements m;
+	char h = '-', v = '-';
+
+	if (get_measurements(pc, &m))
+		return -EINVAL;
+
+        if (!strcmp(attr->attr.name, "phase"))
+		return sprintf(buf, "%d", pc->phase);
+
+        if (!strcmp(attr->attr.name, "sync_offset"))
+		return sprintf(buf, "%d", (readl(pc->base + 4) >> 12) & 0xf);
+
+        if (!strcmp(attr->attr.name, "state")) {
+
+		if (pc->sync_polarities & 1)
+			h = '+';
+		if (pc->sync_polarities & 2)
+			v = '+';
+
+		return sprintf(buf, "H: %c (%d), V: %c (%d), "
+			"H[tot:%d, act:%d, bl:%d, sa:%d, fp:%d, bp:%d], "
+			"V[tot:%d, act:%d, bl:%d, sa:%d, fp:%d, bp:%d], "
+			"%d.%dMHz, px in frame %d (%d.%03d x Htot), "
+			"data in active frame %d (%d.%03d/line), (%d in VB), "
+			"ch0: %d, ch1: %d, ch2: %d, (t=%d)"
+			"0x%08x 0x%08X 0x%08x 0x%08x\n",
+			h, m.h_line_measured, v, m.v_frame_measured,
+			m.htotal, m.hact, m.hblank, m.hsa, m.hfp, m.hbp,
+			m.vtotal, m.vact, m.vblank, m.vsa, m.vfp, m.vbp,
+			m.pixel_clk_hz / 1000000, m.pixel_clk_hz % 1000000,
+			m.pixels_in_frame,
+			m.pixels_in_frame / m.htotal,
+			((m.pixels_in_frame * 1000) / m.htotal) % 1000,
+			m.data_in_frame - m.data_in_vb,
+			(m.data_in_frame - m.data_in_vb) / m.vact,
+			(((m.data_in_frame - m.data_in_vb) * 1000) / m.vact) % 1000,
+			m.data_in_vb,
+			m.channel_escapes[0],
+			m.channel_escapes[1],
+			m.channel_escapes[2],
+			m.px_clocks_escapes_sampled,
+
+			readl(pc->base + 0),
+			readl(pc->base + 4),
+			readl(pc->base + 8),
+			readl(pc->base + 0xc)
+		);
+	}
+
+	return -ENOENT;
+}
+
+static bool hdmicap_dma_filter_fn(struct dma_chan *chan, void *filter_param)
+{
+	struct hdmicap_chip *pc = filter_param;
+
+	if (chan->device->dev->of_node == pc->dma_node) {
+		dev_err(chan->device->dev, "Selected DMA\n");
+		return true;
+	}
+
+	return false;
+}
+
+static void hdmicap_slave_callback(void *completion)
+{
+	pr_err("completion\n");
+        complete(completion);
+}
+
+
+static ssize_t hdmicap_attr_store(struct device *dev,
+                                 struct device_attribute *attr,
+                                 const char *instr,
+                                 size_t bytes)
+{
+	int m, n = simple_strtol(instr, NULL, 10);
+	struct hdmicap_chip *pc = dev_get_drvdata(dev);
+	int only_raw = 0; //BIT(3);
+        dma_addr_t dma_handle;
+	struct dma_chan *dc;
+	//struct dma_slave_config dsc;
+	struct dma_async_tx_descriptor *atd;
+	dma_cookie_t cookie;
+	dma_cap_mask_t mask;
+	size_t size = 64; //542700 * 4;
+	struct xilinx_dma_config config;
+	struct scatterlist sg[1];
+	struct completion comp;
+	unsigned long tmo = msecs_to_jiffies(3000);
+
+        if (!strcmp(attr->attr.name, "grab")) {
+		for (n = 0; n < 1024; n++)
+			((u32 *)pc->buf)[n] = 0x12345678;
+
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_SLAVE, mask);
+		dma_cap_set(DMA_PRIVATE, mask);
+		dc = dma_request_channel(mask, hdmicap_dma_filter_fn, pc);
+		if (!dc || IS_ERR(dc)) {
+			pr_err("failed to get dc\n");
+			return -ENOENT;
+		}
+
+	        dma_handle = dma_map_single(dc->device->dev, pc->buf, size,
+					    DMA_FROM_DEVICE);
+	        if (dma_mapping_error(dev, dma_handle)) {
+                	pr_err("problems with dma mapping\n");
+			return -ENOENT;
+        	}
+		sg_init_table(sg, 1);
+		sg_dma_address(&sg[0]) = dma_handle;
+		sg_dma_len(&sg[0]) = size;
+#if 0
+		memset(&dsc, 0, sizeof dsc);
+
+        	dsc.direction = DMA_DEV_TO_MEM;
+        	//dsc.src_addr = 0;
+        	dsc.dst_addr = dma_handle;
+        	//dsc.src_addr_width = 4;
+        	dsc.dst_addr_width = 4;
+        	//dsc.src_maxburst = 1;
+        	dsc.dst_maxburst = 1;
+        	//dsc.device_fc = true;
+
+		n = dmaengine_slave_config(dc, &dsc);
+		if (n < 0) {
+			pr_err("problem getting slave config %d\n", n);
+			return -ENOENT;
+		}
+#endif
+		memset(&config, 0, sizeof config);
+                config.coalesc = 0;
+                config.delay = 0;
+//		config.reset = 1;
+//                xilinx_dma_channel_set_config(dc, &config);
+		config.reset = 0;
+		xilinx_dma_channel_set_config(dc, &config);
+
+		atd = dc->device->device_prep_slave_sg(dc, sg, 1,
+				DMA_DEV_TO_MEM,
+				DMA_CTRL_ACK | DMA_PREP_INTERRUPT,
+//				0,
+				NULL);
+
+#if 0
+		atd = dmaengine_prep_dma_cyclic(dc, dma_handle, size,
+						4, DMA_FROM_DEVICE,
+						DMA_CTRL_ACK); 
+#endif
+		if (!atd || IS_ERR(atd)) {
+			pr_err("problem with prep\n");
+			return -ENOENT;
+		}
+		init_completion(&comp);
+		atd->callback = hdmicap_slave_callback;
+		atd->callback_param = &comp;
+		cookie = atd->tx_submit(atd);
+
+		pr_err("pre-reset: armed %d, triggered %d, empty %d, full %d\n",
+			!!(readl(pc->base + 8) & BIT(24)),
+			!!(readl(pc->base + 8) & BIT(25)),
+			!!(readl(pc->base + 8) & BIT(26)),
+			!!(readl(pc->base + 8) & BIT(27)));
+
+		/* fifo reset + capture only raw */
+		writel(BIT(5) |BIT(4) | only_raw, pc->base + 8);
+		writel(BIT(5) | only_raw, pc->base + 8);
+
+		pr_err("post-reset: armed %d, triggered %d, empty %d, full %d\n",
+			!!(readl(pc->base + 8) & BIT(24)),
+			!!(readl(pc->base + 8) & BIT(25)),
+			!!(readl(pc->base + 8) & BIT(26)),
+			!!(readl(pc->base + 8) & BIT(27)));
+
+
+		/* DMA length in 32-bit px */
+		writel(3 /*(size >> 2) - 1*/, pc->base + 0x10);
+
+		dma_async_issue_pending(dc);
+#if 0
+		cookie = dmaengine_submit(atd);
+		if (dma_submit_error(cookie)) {
+			pr_err("failed at dmaengine_submit %d\n", (int)cookie);
+			return -ENOENT;
+		}
+		dma_async_issue_pending(dc);
+#endif
+
+		/* ARM it */
+		writel(BIT(0), pc->base + 4);
+
+		pr_err("post-arm: armed %d, triggered %d, empty %d, full %d\n",
+			!!(readl(pc->base + 8) & BIT(24)),
+			!!(readl(pc->base + 8) & BIT(25)),
+			!!(readl(pc->base + 8) & BIT(26)),
+			!!(readl(pc->base + 8) & BIT(27)));
+
+		tmo = wait_for_completion_timeout(&comp, tmo);
+
+		n = dma_async_is_tx_complete(dc, cookie, NULL, NULL);
+		pr_err("got status %d\n", n);
+
+		pr_err("end: armed %d, triggered %d, empty %d, full %d\n",
+			!!(readl(pc->base + 8) & BIT(24)),
+			!!(readl(pc->base + 8) & BIT(25)),
+			!!(readl(pc->base + 8) & BIT(26)),
+			!!(readl(pc->base + 8) & BIT(27)));
+
+		if (n == DMA_IN_PROGRESS) {
+			pr_err("terminating all\n");
+			dc->device->device_terminate_all(dc);
+		}
+
+		dma_unmap_single(dc->device->dev,
+				 dma_handle, size, DMA_FROM_DEVICE);
+		pr_err("unmapped\n");
+		dma_release_channel(dc);
+
+		//pr_err("channel released\n");
+
+		//if (n != DMA_COMPLETE) {
+		//	pr_err("DMA failed\n");
+		//	return -ENOENT;
+		//}
+
+		for (n = 0; n < 8; n++) {
+			m = ((u32 *)pc->buf)[n];
+			if (m & BIT(31))
+				pr_info("%06X\n", m & 0xffffff);
+			else
+				pr_info("%03X %03X %03X\n",
+			   (m >> 20) & 0x3ff, (m >> 10) & 0x3ff, m & 0x3ff);
+		}
+
+#if 0
+		// first one is invalid (all 0)
+		readl(pc->base + 0x2c);
+
+		// read until empty
+		for (n = 0; n < 1024 && !(readl(pc->base + 8) & BIT(26)); n++) {
+			m = readl(pc->base + 0x2c);
+			if (m & BIT(31))
+				pr_info("%06X\n", m & 0xffffff);
+			else
+				pr_info("%03X %03X %03X\n",
+			   (m >> 20) & 0x3ff, (m >> 10) & 0x3ff, m & 0x3ff);
+		}
+#endif
+		return bytes;
+	}
+
+        if (!strcmp(attr->attr.name, "phase")) {
+		n = set_phase(pc, n);
+		if (n < 0)
+			return n;
+		return bytes;
+	}
+
+        if (!strcmp(attr->attr.name, "sync_offset") && n < 10) {
+		writel(BIT(3) | (n << 4) | BIT(1), pc->base + 4);
+		return bytes;
+	}
+
+        if (!strcmp(attr->attr.name, "state")) {
+
+		scan(pc);
+
+                writel(BIT(2) | n, pc->base + 0x8);
+ 
+		return bytes;
+	}
+
+     return -ENOENT;
+}
+
+static DEVICE_ATTR(state, S_IRUGO | S_IWUSR,
+		   hdmicap_attr_show, hdmicap_attr_store);
+static DEVICE_ATTR(sync_offset, S_IRUGO | S_IWUSR,
+		   hdmicap_attr_show, hdmicap_attr_store);
+static DEVICE_ATTR(phase, S_IRUGO | S_IWUSR,
+		   hdmicap_attr_show, hdmicap_attr_store);
+static DEVICE_ATTR(grab, S_IRUGO | S_IWUSR,
+		   hdmicap_attr_show, hdmicap_attr_store);
+
+static struct attribute *attrs[] = {
+	&dev_attr_state.attr,
+	&dev_attr_sync_offset.attr,
+	&dev_attr_phase.attr,
+	&dev_attr_grab.attr,
+	NULL
+};
+
+static const struct attribute_group group = {
+        .attrs  = attrs,
+};
+
+static int hdmicap_probe(struct platform_device *pdev)
+{
+	struct hdmicap_chip *pc;
+	struct resource *r;
+	int ret = 0;
+
+	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
+	if (!pc)
+		return -ENOMEM;
+
+	pc->dev = &pdev->dev;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pc->pa_base = r->start;
+	pc->base = devm_ioremap_resource(&pdev->dev, r);
+	if (IS_ERR(pc->base))
+		return PTR_ERR(pc->base);
+
+	pc->buf = dma_alloc_coherent(pc->dev, SZ_8M,
+				     &pc->dma_handle, GFP_KERNEL);
+	if (IS_ERR(pc->buf) || !pc->buf) {
+		dev_err(pc->dev, "Failed to alloc buf\n");
+		return -ENOMEM;
+	}
+
+	/* clear any pending IRQs */
+	writel(0, pc->base + 0xc);
+
+	/* max it out first to ensure we know where it is */
+	set_phase(pc, 255);
+	/* back off to the middle */
+	set_phase(pc, 128);
+
+	pc->irq = irq_of_parse_and_map(pc->dev->of_node, 0);
+	ret = devm_request_irq(pc->dev, pc->irq, hdmicap_isr, 0, "hdmicap", pc);
+
+	if (ret) {
+		dev_err(pc->dev,
+			"Failed to register IRQ handler. Aborting.\n");
+		return -ENODEV;
+	}
+
+	pc->dma_node = of_parse_phandle(pc->dev->of_node, "dma", 0);
+
+	devm_clk_get(pc->dev, "a");
+	devm_clk_get(pc->dev, "b");
+
+	dev_set_drvdata(&pdev->dev, pc);
+
+	scan(pc);
+
+        ret = sysfs_create_group(&pdev->dev.kobj, &group);
+
+	return ret;
+}
+
+static int hdmicap_remove(struct platform_device *pdev)
+{
+	struct hdmicap_chip *pc = dev_get_drvdata(&pdev->dev);
+
+	dma_free_coherent(pc->dev, SZ_8M, pc->buf, pc->dma_handle);
+
+	return 0;
+}
+
+static const struct of_device_id hdmicap_dt_ids[] = {
+	{ .compatible = "linaro,hdmicap" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, hdmicap_dt_ids);
+
+static struct platform_driver hdmicap_driver = {
+	.driver = {
+		.name = "m8m-hdmicap",
+		.of_match_table = hdmicap_dt_ids,
+	},
+	.probe = hdmicap_probe,
+	.remove = hdmicap_remove,
+};
+module_platform_driver(hdmicap_driver);
+
+MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
+MODULE_DESCRIPTION("Linaro HDMICAP driver");
+MODULE_LICENSE("GPL v2");