diff options
author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-28 13:49:00 +0100 |
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committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-12 16:52:47 +0000 |
commit | 75eb74d60c3e45397c24bff3ddbf9d6338b875cf (patch) | |
tree | 966f09262a42b5b2b65c9b0cf286ca871c9a6438 | |
parent | e576ca0da1374cae5bcc3489b6bda2f33842d977 (diff) |
SynQuacer: retrieve DRAM info from SCP
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-rw-r--r-- | plat/arm/common/arm_bl31_setup.c | 8 | ||||
-rw-r--r-- | plat/arm/common/arm_pm.c | 3 | ||||
-rw-r--r-- | plat/arm/css/common/css_scpi.c | 44 | ||||
-rw-r--r-- | plat/arm/css/enterprise/include/css_enterprise_def.h | 26 |
4 files changed, 81 insertions, 0 deletions
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index aa5af548..8eb3926e 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -240,7 +240,15 @@ void bl31_platform_setup(void) void bl31_plat_runtime_setup(void) { + struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; + arm_bl31_plat_runtime_setup(); + + scpi_get_draminfo(di); + + /* override to reflect what is in use by Trusted Firmware */ + di->base1 = ARM_NS_DRAM1_BASE; + di->size1 = ARM_NS_DRAM1_SIZE; } /******************************************************************************* diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 1e756a9e..4f43bddf 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -146,6 +146,9 @@ int arm_validate_ns_entrypoint(uintptr_t entrypoint) if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) return PSCI_E_SUCCESS; + if ((entrypoint >= ARM_DRAM3_BASE) && (entrypoint < + (ARM_DRAM3_BASE + ARM_DRAM3_SIZE))) + return PSCI_E_SUCCESS; return PSCI_E_INVALID_ADDRESS; } diff --git a/plat/arm/css/common/css_scpi.c b/plat/arm/css/common/css_scpi.c index 02d573c9..7b6ebf94 100644 --- a/plat/arm/css/common/css_scpi.c +++ b/plat/arm/css/common/css_scpi.c @@ -188,3 +188,47 @@ uint32_t scpi_sys_power_state(scpi_system_state_t system_state) return response.status; } + +uint32_t scpi_get_draminfo(struct draminfo *info) +{ + scpi_cmd_t *cmd; + struct { + scpi_cmd_t cmd; + struct draminfo info; + } response; + uint32_t mhu_status; + + scpi_secure_message_start(); + + /* Populate the command header */ + cmd = SCPI_CMD_HEADER_AP_TO_SCP; + cmd->id = SCPI_CMD_GET_DRAMINFO; + cmd->set = SCPI_SET_EXTENDED; + cmd->sender = 0; + cmd->size = 0; + + scpi_secure_message_send(0); + + mhu_status = mhu_secure_message_wait(); + + /* Expect an SCPI message, reject any other protocol */ + if (mhu_status != (1 << SCPI_MHU_SLOT_ID)) { + ERROR("MHU: Unexpected protocol (MHU status: 0x%x)\n", + mhu_status); + panic(); + } + + /* Ensure that any read to the SCPI payload area is done after reading + * the MHU register. If these 2 reads were reordered then the CPU would + * read invalid payload data */ + dmbld(); + + memcpy(&response, (void *)SCPI_SHARED_MEM_SCP_TO_AP, sizeof(response)); + + scpi_secure_message_end(); + + if (response.cmd.status == SCP_OK) + *info = response.info; + + return response.cmd.status; +} diff --git a/plat/arm/css/enterprise/include/css_enterprise_def.h b/plat/arm/css/enterprise/include/css_enterprise_def.h index 33a2fd6a..98d8657f 100644 --- a/plat/arm/css/enterprise/include/css_enterprise_def.h +++ b/plat/arm/css/enterprise/include/css_enterprise_def.h @@ -89,4 +89,30 @@ 32, /* Cluster 9 */ \ 15, /* Cluster 10 */ \ 33 /* Cluster 11 */ + +#define ARM_DRAM3_BASE MAKE_ULL(0x8800000000) +#define ARM_DRAM3_SIZE MAKE_ULL(0x800000000) +#define ARM_DRAM3_END (ARM_DRAM3_BASE + \ + ARM_DRAM3_SIZE - 1) + +#define DRAMINFO_BASE 0x2E00FFC0 + +#define SCPI_CMD_GET_DRAMINFO 0x1 + +#ifndef __ASSEMBLY__ +struct draminfo { + uint32_t num_regions; + uint32_t reserved; + uint64_t base1; + uint64_t size1; + uint64_t base2; + uint64_t size2; + uint64_t base3; + uint64_t size3; +}; + +uint32_t scpi_get_draminfo(struct draminfo *info); + +#endif + #endif /* __CSS_ENTERPRISE_DEF_H__ */ |