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/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CSS_ENTERPRISE_DEF_H__
#define __CSS_ENTERPRISE_DEF_H__
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
#else
/*# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000*/
# define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
#endif
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
# define PLAT_ARM_MAX_BL2_SIZE 0xC000
#endif
#define PLAT_ARM_NSTIMER_FRAME_ID 0
#define PLAT_CSS_MHU_BASE 0x45000000
#define PLAT_ARM_CCN_BASE 0x32000000
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
#define PLAT_MAX_PWR_LVL 1
#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
CSS_IRQ_MHU
#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
#define CSS_ENTERPRISE_DEVICE_BASE (0x20000000)
#define CSS_ENTERPRISE_DEVICE_SIZE (0x20000000)
#define CSS_ENTERPRISE_MAP_DEVICE MAP_REGION_FLAT( \
CSS_ENTERPRISE_DEVICE_BASE, \
CSS_ENTERPRISE_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
#define ENTERPRISE_BOOT_CFG_ADDR 0x45410000
#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6
/* GIC related constants */
#define PLAT_ARM_GICD_BASE 0x30000000
#define PLAT_ARM_GICC_BASE 0x2C000000
/* Map Ashbrook cluster ID to CCN node ID */
#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP \
0, /* Cluster 0 */ \
18, /* Cluster 1 */ \
11, /* Cluster 2 */ \
29, /* Cluster 3 */ \
35, /* Cluster 4 */ \
17, /* Cluster 5 */ \
12, /* Cluster 6 */ \
30, /* Cluster 7 */ \
14, /* Cluster 8 */ \
32, /* Cluster 9 */ \
15, /* Cluster 10 */ \
33 /* Cluster 11 */
#define ARM_DRAM3_BASE MAKE_ULL(0x8800000000)
#define ARM_DRAM3_SIZE MAKE_ULL(0x800000000)
#define ARM_DRAM3_END (ARM_DRAM3_BASE + \
ARM_DRAM3_SIZE - 1)
#define DRAMINFO_BASE 0x2E00FFC0
#define SCPI_CMD_GET_DRAMINFO 0x1
#ifndef __ASSEMBLY__
struct draminfo {
uint32_t num_regions;
uint32_t reserved;
uint64_t base1;
uint64_t size1;
uint64_t base2;
uint64_t size2;
uint64_t base3;
uint64_t size3;
};
uint32_t scpi_get_draminfo(struct draminfo *info);
#endif
#endif /* __CSS_ENTERPRISE_DEF_H__ */
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